TW201724212A - Selective oxidation multi-height fin field effect transistor device - Google Patents

Abstract

A method comprising: forming a non-planar device conduction channel of a multi-gate device on a substrate, the channel comprising a height dimension defined from a base layer on a surface of the substrate; modifying the range to be less than an entire portion of the channel; and A stack is formed on the via, the gate stack including a dielectric material and a gate electrode. The device comprises: a non-planar multi-gate device on the substrate, comprising a channel comprising a height dimension defining a conductive portion and an oxidized portion and a gate stack disposed on the channel, the gate stack comprising a dielectric material and a gate electrode.

Description

Selective oxidation multi-height fin field effect transistor device

A semiconductor device including a non-planar semiconductor device having a channel region having a low energy bandgap cladding layer.

Over the past few decades, the scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry. Scaling to smaller and smaller features can increase the density of functional units over a limited area of the semiconductor wafer. For example, a reduced transistor size can bond a greater number of memory devices on a wafer, enabling the production of products with more capacity. However, devices with continuously increasing capacity are not without problems. The need to optimize the performance of individual devices is becoming increasingly important.

Future circuit devices, such as central processing unit devices, are expected to have both high performance devices and low capacitance, low power devices integrated in a single die or wafer. Currently, three-dimensional non-planar metal oxide semiconductor field effect transistors (MOSFETs) typically utilize a single height of fins. Single height fins have a tendency to limit design and require sacrifice.

A‧‧‧ device

B‧‧‧ device

H‧‧‧ Height

H1‧‧‧ Height

H‧‧‧height

100‧‧‧ structure

110‧‧‧Substrate

120‧‧‧buffer layer

130‧‧‧Fin

140‧‧‧ dielectric materials

145‧‧‧gate electrode area

150‧‧‧ spacers

155‧‧‧Doping area

160A‧‧‧ junction area

160B‧‧‧ junction area

165‧‧‧ catalyst layer

170‧‧‧ Sacrificial filling layer

175‧‧‧Oxidized parts

180‧‧‧gate electrode

185‧‧‧ dielectric layer

190‧‧‧ dielectric layer

200‧‧‧ device

260A‧‧‧ junction area

260B‧‧‧ junction area

275‧‧‧Modified area

300‧‧‧Interconnects

302‧‧‧Substrate

304‧‧‧Substrate

306‧‧‧ Ball Grid Array

308‧‧‧Metal interconnection

310‧‧‧through hole

400‧‧‧ computing device

402‧‧‧Integrated circuit die

404‧‧‧Central Processing Unit

406‧‧‧ on-die memory

408‧‧‧Communication chip

410‧‧‧ volatile memory

412‧‧‧ Non-volatile memory

414‧‧‧Graphic Processing Unit

416‧‧‧Digital Signal Processor

420‧‧‧ chipsets

422‧‧‧Antenna

424‧‧‧Touch screen display

426‧‧‧Touch screen display controller

428‧‧‧Battery

430‧‧‧ compass

432‧‧‧ motion sensor

434‧‧‧Speaker

436‧‧‧ camera

438‧‧‧User input device

440‧‧‧Many storage devices

442‧‧‧ cryptographic processor

444‧‧‧Global Positioning System

1300‧‧‧Fin

1310‧‧‧Fin

1800‧‧‧gate electrode

2300‧‧‧Fin

1 is a top perspective side view of a portion of a substrate, ie, for example, a portion of an integrated circuit die or wafer on a wafer and having a portion of a three-dimensional circuit device formed on the substrate.

Figure 2 is a cross-sectional side view showing the structure of the straight line 2-2' of Figure 1.

Figure 3 is a structural view of the straight-through line 3-3' of Figure 1.

Figure 4 is a structural view of Figure 2 after introduction of a catalyst layer on the fin of the device.

Figure 5 is a structural view of Figure 3 after introduction of a catalyst layer on the fin of the device.

Figure 6 is a block diagram of Figure 4 after a portion of the catalyst layer has been removed or recessed.

Figure 7 is a block diagram of Figure 5 after a portion of the catalyst layer has been removed or recessed.

Figure 8 is a structural view of Figure 6 after modifying a portion of the fin.

Figure 9 is a structural view of Figure 7 after modifying a portion of the fin.

Figure 10 is a structural view of Figure 8 after removal of the catalyst layer, introduction of a dielectric material to the modified portion of the fin in the gate electrode region, and introduction of a gate stack on the fin.

Figure 11 is a block diagram of Figure 9 after removal of the catalyst layer, introduction of a dielectric material to the modified portion of the fin in the gate electrode region, and introduction of a gate stack on the fin.

Figure 12 is an enlarged view of the structure of Figure 11 to illustrate the presence of two devices on a substrate.

Figure 13 is a cross-sectional view showing another embodiment of the device structure.

14 is an interconnect that implements one or more embodiments.

Figure 15 is a diagram of an embodiment of a computing device.

SUMMARY OF THE INVENTION AND EMBODIMENT

Embodiments described herein relate to non-planar semiconductor devices (eg, three-dimensional devices) having a target or predetermined fin or channel height, and non-planar semiconductors that fabricate targets or predetermined fins or channel heights on the substrate. A method of apparatus, wherein the fin height can be one of a plurality of fin heights of a device on a substrate. In one such embodiment, the gate stack of the non-planar device surrounds the channel region of the fin (such as a three-gate or fin field effect transistor device, etc.). This method enables the incorporation of three-dimensional devices having different fin heights on the wafer or die, such as high performance devices requiring high current with low capacitance, lower power devices, and the like.

1-11 illustrate a method or process for modifying the fin or channel height of a non-planar multi-gate semiconductor device from an initial fin height to a target fin height that is different from the initial fin height. In one embodiment, the device is a three-dimensional metal oxide semiconductor field effect transistor (MOSFET), and is an isolation device or one of a plurality of nested devices. As is known, with respect to a typical integrated circuit, both an N-channel transistor and a P-channel transistor can be fabricated on a single substrate to form a complementary metal oxide semiconductor (CMOS) integrated circuit. Moreover, other interconnects can be fabricated to integrate such devices into the integrated circuit.

Figure 1 is a portion of an integrated circuit die or wafer, for example, on a wafer. A top perspective view of a portion of a silicon germanium or silicon germanium on insulator (SOI) substrate. In particular, Figure 1 is a structure 100 of a substrate 110 comprising germanium or SOI. The covered substrate 110 is an optional buffer layer 120. In one embodiment, the buffer layer is a buffer layer that is introduced onto the substrate 110 by growth techniques in one embodiment. The buffer layer 120 has a representative thickness on the order of hundreds of nanometers (nm).

In the embodiment shown in FIG. 1, disposed on the surface of the buffer layer 120 is a portion of a transistor device, such as an N-type transistor device or a P-type transistor device. In this embodiment, common to the N-type or P-type transistor devices is the fins 130 disposed on the surface (surface 125) of the buffer layer 120. A representative material for the fins 130 is a Group III-V semiconductor material such as an indium gallium arsenide (InGaAs) material or the like. In an embodiment, the fin 130 has a length dimension L that is greater than the height dimension H. Representative length ranges are on the order of 10 nm to 1 mm (mm), and representative height ranges are on the order of 5 nm to 200 nm. The fins 130 also have a width W representative of a grade of 4-10 nm. As illustrated, the fins 130 are three-dimensional bodies that extend from the surface 125 of the substrate 110 (or alternatively from the buffer layer 120). The three-dimensional body shown in Figure 1 is a rectangular body, but it should be understood that in the processing of such a body, the available tools may not be able to achieve a positive rectangle and may result in other shapes. Representative shapes include, but are not limited to, trapezoids (eg, the bottom edge is larger than the top edge) and the arch shape.

In one embodiment, disposed on the fin 130 is a dielectric material 140 such as cerium oxide, or a dielectric material (low-k dielectric) having a dielectric constant (k) less than cerium oxide. Dielectric material 140 was introduced to fit The thickness of the gate electrode structure. Figure 1 is a spacer 150 defining a region of a gate electrode. Typically, the spacers 150 are deposited along with a sacrificial or false gate electrode on a designated channel region of the fin 130 (as the fin or channel 1300 is considered to be the same), and then the junction region and the introduction interface are formed. Electrical material 140. Thus, for the purposes of this embodiment, such sacrificial or dummy gate electrodes are deposited in advance in the gate electrode region 145, and the junction regions are formed as desired according to conventional processing techniques, followed by deposition of dielectric material 140. In the illustration shown in FIG. 1, the sacrificial or dummy gate has been removed, such as by an etch process, leaving the fins or channels 1300 exposed in the gate electrode region 145.

Figure 2 is a cross-sectional side view showing the structure of the straight line 2-2' of Figure 1. Figure 3 is a structural view of the straight-through line 3-3' of Figure 1. Referring to Figure 2, structure 100 illustrates a fin or channel 1300 having a height H disposed between junction region 160A and junction region 160B (source and drain regions, respectively). Junction regions 160A and 160B may be doped Group III-V compound material regions. Below each of junction area 160A and junction area 160B is a dopant or implant region 155. The junction regions and dopants/implants are formed according to conventional processing. Overlay or on junction region 160A/160B (as seen) is dielectric material 140 and spacer 150 defining gate electrode region 145. 3 illustrates the structure 100 taken through the fins or channels 1300 in the gate electrode region 145, and the fins 130 on the substrate having the height H illustrated.

4 and 5 respectively illustrate the structure of FIGS. 2 and 3 after introduction (eg, deposition) of the catalyst layer 165 on the fin 1300. In one embodiment, the catalyst layer 165 is selected to enhance the fin shape. An oxidized material of the material of the article 1300. In one embodiment, the material that oxidizes the material of the fins 1300 is a material selected to reduce the oxidation temperature of the fin material. Typically, the fin material of the semiconductor will oxidize in a hydrogen and oxygen environment at about 1000 °C. In an embodiment, the catalyst layer 165 is a material that will promote oxidation of the material of the fins 1300 at a temperature below 1000 ° C, such as a grade of 600 ° C or lower (eg, 500 ° C), and the like. A suitable material for the catalyst layer is alumina (Al ₂ O ₃ ). Typically, the catalyst layer of alumina can be introduced to a thickness of the order of 10 nm or less via an atomic layer deposition process. As shown in FIG. 5, a catalyst layer 165 is conformally deposited on the fins 1300, and in one embodiment is a base layer of the substrate in the gate electrode region 145 (on the buffer layer 120).

6 and 7 illustrate the structures of Figs. 4 and 5, respectively, after removing or recessing a portion of the catalyst layer 165. In an embodiment, the catalyst layer 165 is lowered to a modified height selected for the fins 1300. Typically, catalyst layer 165 is recessed by introducing a sacrificial fill layer into the gate electrode region followed by dry etching and wet etching. As shown, the catalyst layer 165 is formed on the fins 1300 from its base layer to a tip that is smaller than the fins. FIG. 7 illustrates the sacrificial fill layer 170 introduced to the height of the catalyst layer 165. Suitable materials for the sacrificial fill layer 170 include flowable oxides such as carbon thermal masks and the like. As shown in FIG. 7, after the recess process, the catalyst layer 165 is maintained around the bottom of the fins 1300.

8 and 9 respectively illustrate FIG. 6 and FIG. 6 after modification of the sacrificial fill layer and a portion of the fin 1300 by, for example, selective etching. The structure of Figure 7. The modification is after the removal of the sacrificial filling layer. In this embodiment, the modification is the oxidation of the lower portion of the fin 1300. In one embodiment, the oxidation of a portion of the fins 1300 is performed at a temperature below the conventional oxidation temperature (eg, a temperature below 1000 °C). The lower portion of the oxide fin 1300 is oxidized in the temperature, for example, below the oxidation temperature of the material, via the presence of the catalyst layer 165. 8 and 9 illustrate an oxidized portion 175 of the fin 1300. After modification, the fins 1300 have active portions (e.g., non-oxidized sites) having a height h.

10 and 11 respectively illustrate FIG. 8 and FIG. 8 after removing the catalyst layer 165 by, for example, a selective etching process and introducing a dielectric material into the gate electrode region to the height of the modified portion 175 of the fin 1300. The structure of 9. After the dielectric layer 185 is introduced in the gate electrode region, the gate stack is introduced (e.g., deposited) on the structure including the gate dielectric and the gate electrode. In an embodiment, the gate electrode 180 of the gate electrode stack is composed of a metal gate, and the gate dielectric layer 190 is made of a material having a dielectric constant greater than the dielectric constant of the cerium oxide (high-k material). Composed of. For example, in one embodiment, the gate dielectric layer 190 is comprised of, for example, but not limited to, hafnium oxide, hafnium oxynitride, niobate, hafnium oxide, zirconium oxide, zirconium silicate, hafnium oxide, tantalum It is composed of materials such as titanate, strontium titanate, strontium titanate, cerium oxide, aluminum oxide, lead lanthanum oxide, lead zinc silicate, or a combination thereof. In an embodiment, the gate electrode 180 is composed of, for example, but not limited to, metal nitride, metal carbide, metal telluride, metal aluminide, hafnium, zirconium, titanium, hafnium, aluminum, lanthanum, palladium, platinum, A metal layer such as cobalt, nickel, or a conductive metal oxide.

As shown in FIGS. 10 and 11, the active portion of the fin 1300 has a height h with a gate electrode 180 surrounding the fin. As shown, the modified height h of the fins 1300 is less than the starting height h of the fins 1300, such as shown in Figures 2 and 3, for example.

Figure 12 illustrates an enlarged view of the structure of Figure 11 to illustrate the presence of two devices on a substrate. Device A is the device shown in FIG. Device B is a second three-dimensional or non-planar multi-gate device that includes a channel or fin 1310 and a gate electrode 1800. Device A has a modified fin height h. The device B on the same substrate has a fin height H (fin 1310) that is greater than the modified fin height h of the device A. Thus, a method for integrating devices of different fin heights on the same substrate is illustrated in accordance with the processing described herein. Device A has a fin or channel that is typically shorter than device B. Typically, device A can be used in applications that require lower capacitance and want less leakage. An example is a device for graphics applications. Device B is typically used for high performance applications where high current is desired. In the drawings, device A has a fin height h that is about half the size of the fin height of device B. It should be understood that the fin height can be modified to any desired height, including half the height, three quarters of the height, one quarter of the height, and the like.

Figure 13 illustrates a cross-sectional view of another embodiment of the device structure. In this embodiment, a non-planar semiconductor such as a three-dimensional fin field effect transistor utilizes a modified region below the junction region to isolate the channel of the device. Referring to Figure 13, device 200 includes a fin 2300 as a channel region. The fin 2300 has a fin height H1, and the junction area 260A and the junction area 2601B are on opposite sides of the fin. In addition to having an implant or dopant zone under each junction area In addition to the face, the device also includes a modification zone 275. In one embodiment, modification zone 275 is an oxidized zone that can be generally formed as described above with reference to Figures 2-11. In an embodiment, the modification of the fin 2300 is only on its base layer such that the fin (channel) has a maximum target fin height. In this embodiment, the oxidation of the structure includes not only the bottom of the fins 2300, but also the oxidized regions below the junction regions 260A and 260B. It will be appreciated that in other embodiments, larger portions of the fin 2300 may be modified (e.g., oxidized) if desired.

In another embodiment, in addition to forming the structure 200 in accordance with the processes described above with reference to Figures 2-11, the bottom of the fin and the area under the junction area may be performed prior to forming the junction regions 260A and 260B. Oxidation.

Figure 14 illustrates an interconnect including one or more embodiments. The interconnect 300 is an intermediate substrate for bridging the first substrate 302 to the second substrate 304. The first substrate 302 can be, for example, an integrated circuit die. The second substrate 304 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of the interconnect 300 is to extend the connection to a wider pitch or to reroute connections to different connections. For example, interconnect 300 can couple integrated circuit dies to a ball grid array (BGA) 306 that can then be coupled to second substrate 304. In some embodiments, the first and second substrates 302/304 are attached to opposite sides of the interconnect 300. In other embodiments, the first and second substrates 302/304 are attached to the same side of the interconnect 300. In other embodiments, three or more substrates are interconnected by interconnect 300.

The interconnect 300 is made of epoxy resin, glass fiber reinforced epoxy resin, A ceramic material, or a polymer material such as polyimide, is formed. In other implementations, the interconnect system is formed from alternating hard or flexible materials including the same materials described above for use in a semiconductor substrate, such as tantalum, niobium, and other Group III-V and Group IV materials.

The interconnect includes metal interconnects 308 and vias 310, including but not limited to germanium vias (TSVs) 312. The interconnect 300 can additionally include a shackle device 314 that includes both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, electrical conductors, fuses, diodes, transformers, inductors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, inductors, and MEMS devices can also be formed on interconnect 300.

According to an embodiment, the apparatus or process disclosed herein may be used in the fabrication of interconnect 300.

FIG. 15 illustrates a computing device 400 in accordance with an embodiment. Computing device 400 can include some components. In an embodiment, the components are attached to one or more motherboards. In another embodiment, these components are fabricated onto a single single wafer system (SoC) die other than a motherboard. Components in computing device 400 include, but are not limited to, integrated circuit die 402 and at least one communication die 408. In some embodiments, the communication die 408 is fabricated as part of the integrated circuit die 402. The integrated circuit die 402 can include a CPU 404 and on-die memory 406 (usually used as a cache memory), such as by an intrusive DRAM (eDRAM (Intrusive Dynamic Random Access Memory)). ) or spin transfer torque memory (STTM) Or STTM-RAM (self-rotating torque random access memory)).

Computing device 400 can include other components that may or may not be physically and electrically coupled to a motherboard or fabricated within a SoC die. These other components include, but are not limited to, volatile memory 410 (eg, DRAM), non-volatile memory 412 (eg, ROM or flash memory), graphics processing unit 414 (GPU), digital signal processor 416 a cryptographic processor 442 (a specialized processor that performs an encryption algorithm in a hard body), a chipset 420, an antenna 422, a display or touchscreen display 424, a touchscreen controller 426, a battery 428, or other power source, power An amplifier (not shown), a global positioning system (GPS) device 444, a compass 430, a motion coprocessor or sensor 432 (which may include an accelerometer, a gyroscope, and a compass), a speaker 434, a camera 436, user input Device 438 (such as a keyboard, mouse, electronic pen, and touch pad, etc.), and a large number of storage devices 440 (such as a hard disk drive, a compact disc (CD), a digital versatile disc (DVD), and the like) .

The communication chip 408 is capable of wireless communication to transfer data to and from the computing device 400. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, and the like that can communicate data via modulated non-solid-state media via the use of modulated electromagnetic radiation. The term does not imply that the associated device does not contain any lines, but in some embodiments may not include lines. The communication chip 408 can implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11, Home), WiMAX (IEEE 802.16, Home), IEEE 802.20, Long Term Evolution Technology (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and above . Computing device 400 can include a plurality of communication chips 408. For example, the first communication chip 408 is specific to shorter range wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip 408 is dedicated to longer range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE. , Ev-DO and others.

Processor 404 of computing device 400 includes one or more devices, such as a transistor or metal interconnect, etc., formed in accordance with embodiments described herein, including having a fin height tailored for a particular application (eg, A three-dimensional multi-gate transistor device with different fin heights on the processor 404). The term "processor" may mean any device or portion of a device that processes electronic data from a register and/or memory to convert that electronic data into a memory and/or memory. Other electronic materials.

The communication die 408 may also include one or more devices, such as a transistor or metal interconnect, etc., formed in accordance with the embodiments described above, including a three-dimensional crystal device including modified or tailored fin heights. .

In other embodiments, another component that is framed within computing device 400 can include one or more devices, such as a transistor or metal interconnect, etc., formed in accordance with the embodiments described above, including A three-dimensional transistor device that modifies or trims the height of the fin.

In various embodiments, computing device 400 can be a laptop, a small notebook, a notebook, an ultra-thin notebook, a smart phone, a tablet Brain, personal digital assistant (PDA), mini mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable Music player, or digital video recorder. In other implementations, computing device 400 can be any other electronic device that processes data.

example

The examples below are related to the examples.

Example 1 includes a method of forming a non-planar conductive channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base layer on a surface of the substrate; modified to a range smaller than the entire portion of the channel; and a gate A stack is formed on the via, and the gate stack includes a dielectric material and a gate electrode.

In Example 2, the modification of Example 1 includes oxidation, and before the oxidation is less than the entire portion of the channel, the method includes forming a layer of catalyst material on the channel, wherein the catalyst material comprises a property having oxidation of the material that will enhance the channel. material.

In Example 3, the oxidation channel of Example 2 includes a temperature that passes the channel through the oxidation temperature of the material below the channel.

In Example 4, this layer of the catalyst material of Example 2 was formed only in the base layer of the channel.

In Example 5, this layer of the catalyst material of Example 2 was formed on a channel from the base layer of the channel to a height below the apex of the channel.

In Example 6, this layer of the catalyst material of Example 5 was formed in the pass. Half of the length of the road.

In Example 7, forming the catalyst layer of Example 3 includes depositing a catalyst layer over the entire height dimension of the channel; and after deposition, the method includes removing the layer of catalyst material from a portion of the height dimension of the channel.

In Example 8, the channel of Example 1 or Example 2 is disposed between the junction regions on the substrate, and the method further includes a portion of the substrate under the oxide junction region.

In Example 9, the method of Example 1 or Example 2 prior to forming the gate stack includes introducing a dielectric material adjacent to the channel to the height of the oxidized portion of the equivalent channel.

Example 10 is a method comprising forming a non-planar conductive channel of a multi-gate device on a substrate; a portion of the oxidized channel, the portion being oxidized by a channel measured from a surface of the substrate below a total height dimension of the channel The height dimension is defined; and the gate stack is formed on the channel, and the gate stack includes a dielectric material and a gate electrode.

In Example 11, the method of Example 10 prior to oxidizing less than the entire portion of the channel comprises forming a layer of catalyst material on the channel, wherein the catalyst material comprises a material having the property of oxidizing the material of the enhanced channel.

In Example 12, the oxidation channel of Example 11 included a temperature at which the channel passed the oxidation temperature of the material below the channel.

In Example 13, the forming of the layer of catalyst material on the channel of Example 11 includes depositing the layer of catalyst material over the entire portion of the channel; and prior to oxidizing, the method further includes removing the layer of the catalyst material portion.

In Example 14, the removing of a portion of this layer of catalyst material of Example 13 includes removing the layer from at least half of the total height dimension of the channel.

In Example 15, the channels of any of Examples 10-14 are disposed between the junction regions on the substrate, and the method further includes a portion of the substrate under the oxide junction regions.

In Example 16, prior to forming the gate stack, the method of any of Examples 10-15 includes introducing a dielectric material adjacent the channel to a height of an oxidized portion of the equivalent channel.

Example 17 is an apparatus comprising a non-planar multi-gate device on a substrate, the channel comprising a channel comprising a height dimension defining a conductive portion and a modified portion and a gate stack disposed on the channel, the gate stack comprising a dielectric material and a gate Polar electrode.

In Example 18, the gate stack of Example 17 was disposed only on the conductive portion of the channel.

In Example 19, the modified portion of the channel of Example 17 or Example 18 is disposed between the substrate and the conductive portion of the channel.

In Example 20, the multi-gate device of Example 17 or Example 18 is a first multi-gate device, the device further includes a second multi-gate device, the second multi-gate device includes a channel, and the channel includes a height dimension greater than the first The conductive portion of the height of the conductive portion of the multi-gate device.

In Example 21, the modified portion of the channel of Example 17 or Example 18 was oxidized.

In Example 22, the multi-gate device of Example 17 or Example 18 is packaged separately. The junction area on each of the opposite sides of the channel oxidizes the area under the junction area.

The illustrations of the above-described illustrations, including the description of the abstract, are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although the specific embodiments of the invention and the examples for the invention are disclosed herein, it will be understood by those skilled in the art that various equivalent modifications are possible within the scope.

These modifications can be made in accordance with the above detailed description. The words used in the following claims are not to be construed as limiting the invention to the particular embodiments disclosed. Rather, the scope of the invention is to be determined solely by the scope of the appended claims.

100‧‧‧ structure

110‧‧‧Substrate

120‧‧‧buffer layer

125‧‧‧ surface

130‧‧‧Fin

140‧‧‧ dielectric materials

145‧‧‧gate electrode area

150‧‧‧ spacers

Claims (22)

A method comprising: forming a non-planar conductive channel of a multi-gate device on a substrate, the channel comprising a height dimension defined from a base layer on a surface of the substrate; modifying to a range less than an entire portion of the channel; A gate stack is formed on the via, the gate stack comprising a dielectric material and a gate electrode. The method of claim 1, wherein the modifying comprises oxidizing, and before the oxidation is less than the entire portion of the channel, the method comprises forming a layer of catalyst material on the channel, wherein the catalyst material comprises having A material that oxidizes the properties of the material of the channel. The method of claim 2, wherein oxidizing the channel comprises passing the channel through a temperature below an oxidation temperature of a material of the channel. The method of claim 2, wherein the layer of the catalyst material is formed only on the base layer of the channel. The method of claim 2, wherein the layer of the catalyst material is formed on the channel from the base layer of the channel to a height below an apex of the channel. The method of claim 5, wherein the layer of the catalyst material is formed on one half of the length of the channel. The method of claim 3, wherein forming the catalyst layer comprises depositing the catalyst layer over the entire height dimension of the channel, and after deposition, the method includes the height dimension from the channel A portion of the inch removes the layer of the catalyst material. The method of claim 1, wherein the channel is disposed between junction regions on the substrate, the method further comprising oxidizing a portion of the substrate under the junction regions. The method of claim 1, wherein prior to forming the gate stack, the method includes introducing a dielectric material adjacent the channel to a height corresponding to the oxidized portion of the channel. A method comprising: forming a non-planar conductive channel of a multi-gate device on a substrate; oxidizing a portion of the channel, the portion being oxidized is measured by a surface of the substrate from a total height dimension below the channel The height dimension of the channel is defined; and a gate stack is formed on the channel, the gate stack comprising a dielectric material and a gate electrode. The method of claim 10, wherein, prior to oxidizing less than the entire portion of the channel, the method comprises forming a layer of catalyst material on the channel, wherein the catalyst material comprises oxidizing a material having a channel that will enhance the channel The material of the characteristics. The method of claim 11, wherein oxidizing the channel comprises passing the channel through a temperature below an oxidation temperature of a material of the channel. The method of claim 11, wherein forming the layer of the catalyst material on the channel comprises depositing the layer of the catalyst material over the entire portion of the channel, and prior to oxidizing, the method Further comprising a portion of the layer from which the catalyst material is removed. The method of claim 13, wherein removing a portion of the layer of the catalyst material comprises removing the layer from at least half of the total height dimension of the channel. The method of claim 10, wherein the channel is disposed between the junction regions on the substrate, the method further comprising oxidizing a portion of the substrate under the junction regions. The method of claim 10, wherein prior to forming the gate stack, the method includes introducing a dielectric material adjacent the channel to a height corresponding to the oxidized portion of the channel. A device comprising: a non-planar multi-gate device on a substrate, the channel comprising a channel comprising a height dimension defining a conductive portion and a modified portion and a gate stack disposed on the channel, the gate stack comprising a dielectric material And gate electrode. The device of claim 17, wherein the gate stack is disposed only on the conductive portion of the channel. The device of claim 17, wherein the modified portion of the channel is disposed between the substrate and the conductive portion of the channel. The device of claim 17, wherein the multi-gate device is a first multi-gate device, the device further comprising a second multi-gate device, the second multi-gate device comprising a channel, the channel comprising The height dimension is greater than the conductive portion of the height dimension of the conductive portion of the first plurality of gate devices. The device of claim 17, wherein the modified portion of the channel is oxidized. The apparatus of claim 17, wherein the multi-gate device further comprises a junction region on each of the opposite sides of the channel, the region under the junction region being oxidized.