TW201716910A - Clock providing system - Google Patents

Abstract

A clock providing system including a multi-cell chip and a clock providing apparatus is provided. The multi-cell chip includes a semiconductor subtract, a plurality of cells and a plurality of signal transmission line sets. The cells are disposed on the semiconductor substrate. A separation space is existed between any two adjacent cells. Each of the signal transmission line sets is disposed in the separation space and configured to perform signal transmission between two adjacent cells. The multi-cell chip may be cleaved into multiple sub-chips by cutting parts of the signal transmission line sets along parts of the separation spaces. Parts of the plurality of sub-chips is still operable. The clock providing apparatus is coupled to at least one interface cell of the cells. The clock providing apparatus provides an operational clock signal to each of the cells through the at least one interface cell and the signal transmission line sets.

Description

Clock supply system

This invention relates to a clock supply system, and more particularly to a clock supply system for a multi-cell wafer.

In today's era of information explosion, integrated circuits have been inextricably linked to everyday life. Electronic products consisting of integrated circuit components are often used in food and clothing. As semiconductor process technology continues to evolve, more and more arithmetic processing units can be integrated into a single wafer and fabricated using high-order semiconductor process technology. Due to the cost of manufacturing high-order semiconductor processes (such as photomasks), current solutions are mostly based on high computational considerations to design wafers. If the user designs the wafer based on high computational power considerations, for example, integrating multiple arithmetic processing units into the wafer, the cost of the high-computation wafer will be high, and it is not suitable for low-cost and low-computing power requirements. In the electronics. That is to say, after the current design or fabrication of the wafer is completed, the current scheme can no longer provide the user with an elastic choice between the wafer computing power and the wafer cost.

In addition, such arithmetic processing units in the wafer need to be coupled to a clock source. Thereby, the clock source can simultaneously supply the clock signals required for the operation of the arithmetic processing units, so that the arithmetic processing units can operate normally. However, when such arithmetic processing units are operated together in the same time zone in response to the received clock signal, the electronic product may be caused to reduce the transient stability of the power system of the electronic product due to excessive instantaneous power consumption.

In view of the above, the present invention provides a clock supply system capable of providing a working clock signal required for operation of a multi-cell wafer in a clock supply system, wherein the multi-cell wafer is connected to the required power source and signal and can be used. (operable). When the poly unit wafer has not been re-cut, the data can be dispersed in a plurality of unit cells in the poly unit wafer. The signals of different unit cells in the multi-cell wafer can be transmitted through the signal transmission line group between the unit cells. In addition, the user can elastically cut the polycrystalline silicon wafer in units of unit cells according to actual applications, required computing power or cost considerations, and cut into a plurality of sub-wafers, wherein the cut portions are cut. The sub-chip can still be used after it has been connected to the required power and signal (still operational). In addition, the clock supply system can reduce the instantaneous power consumption, and can also reduce the switching noise generated when the working clock signals of each unit cell in the clock supply system are simultaneously changed, thereby improving the overall stability of the clock supply system. degree. In addition, the clock transmission mode between the unit cells can be adjusted by changing the preset clock selection order in each unit cell. Therefore, the flexibility of the design of the clock supply system can be increased.

The clock supply system of the present invention may include a multi-cell wafer and a clock supply device. The poly unit cell wafer may include a semiconductor substrate, a plurality of unit cells, and a plurality of signal transmission line groups. These unit cells can be arranged on a semiconductor substrate. Each unit cell may have at least one space between adjacent cells. Each signal transmission line group can be disposed in a space between adjacent cells, and can be used for signal transmission between adjacent cells. The above polycrystalline cell wafer is usable (operable), and the polycrystalline cell wafer can be cut through a portion of the spaced spaces to cut off some of the signal transmission line groups, so that the polycrystalline silicon wafer can be segmented. It is a plurality of sub-wafers, wherein the sub-wafers of the diced portions are still usable (still operational). The clock supply device can couple at least one of the unit cells of the unit cells. The clock supply device can provide a working clock signal required for each unit cell to operate through at least one interface cell and the signal transmission line group.

In an embodiment of the invention, each of the unit cells may have a plurality of pads. At least one of the pads on each of the at least one interface cells can be coupled to the clock supply to receive the at least one first clock signal.

In an embodiment of the invention, when each unit cell determines that the at least one first clock signal is received from the clock supply device, each unit cell may select the at least one first clock signal as the unit cell. Working clock signal, each unit cell can use the at least one first clock signal as at least one second clock signal and transmit to the first adjacent unit cell along the first direction, and each unit cell can The at least one first clock signal is transmitted as at least one third clock signal and transmitted to the second adjacent unit cell in the second direction.

In an embodiment of the invention, when each unit cell determines that at least one first clock signal is not received from the clock supply device, each unit cell can determine whether at least one of the third adjacent unit cells is received. Two clock signals. If the determination result is yes, each unit cell may select the at least one second clock signal as the working clock signal of each unit cell, and each unit cell may perform the at least one second clock signal along the first direction. Transfer to the first adjacent unit cell. If the determination result is no, each unit cell may select at least one third clock signal from the fourth adjacent unit cell as the working clock signal of each unit cell, and each unit cell may perform the at least one third clock. The signal is transmitted along the first direction to the first adjacent unit cell, and each unit cell can transmit the at least one third clock signal to the second adjacent unit cell along the second direction.

In an embodiment of the present invention, when each unit cell determines that the at least one first clock signal is received from the clock supply device, each unit cell may generate at least one second according to the at least one first clock signal. a second synchronization signal of the clock signal, each unit cell may generate a third synchronization signal corresponding to the at least one third clock signal according to the at least one first clock signal, and each unit cell may follow the second synchronization signal One direction is transmitted to the first adjacent unit cell, and each unit cell can transmit the third synchronization signal in the second direction to the second adjacent unit cell. Each of the unit cells may select the at least one first clock signal as an input clock signal of each unit cell, and each unit cell may select a second synchronization signal or a third synchronization signal as an input synchronization signal of each unit cell. And according to the production of the working clock signal of each unit cell. The period of the second synchronization signal and the period of the third synchronization signal are greater than the period of the at least one first clock signal, and the period of the second synchronization signal and the period of the third synchronization signal are periods of the at least one first clock signal Integer multiple.

In an embodiment of the invention, when each unit cell determines that the at least one first clock signal is not received from the clock supply device, each unit cell can determine whether at least one is received from the third adjacent unit cell. The second clock signal and the second synchronization signal. If the determination result is yes, each unit cell may select at least one second clock signal and the second synchronization signal to respectively serve as an input clock signal and an input synchronization signal of each unit cell, and accordingly generate a working clock of each unit cell. And transmitting at least a second clock signal and the second synchronization signal to the first adjacent unit cell along the first direction. If the determination result is no, each unit cell may select at least one third clock signal and the third synchronization signal from the fourth adjacent unit cell as the input clock signal and the input synchronization signal of each unit cell respectively. To generate a working clock signal of each unit cell, each unit cell can transmit at least a third clock signal and a third synchronization signal to the first adjacent unit cell along the first direction, and each unit cell can be at least A third clock signal and a third synchronization signal are transmitted along the second direction to the second adjacent unit cell.

In an embodiment of the invention, each of the unit cells may generate a working clock signal according to the input clock signal and the input synchronization signal, so that each unit cell can react to the working clock signal and input the period of the synchronization signal. Operate in different time zones or at different time points within.

In an embodiment of the invention, when each unit cell determines that the at least one first clock signal is received from the clock supply device, each unit cell may select the at least one first clock signal as the unit cell. The clock signal is operated, and each of the unit cells can use the at least one first clock signal as at least one second clock signal and transmit to all adjacent unit cells.

In an embodiment of the invention, when each unit cell determines that the at least one first clock signal is not received from the clock supply device, each unit cell may select one of the partially adjacent unit cells. The at least one second clock signal is used as the working clock signal of each unit cell, and each unit cell can transmit the selected at least one second clock signal to the remaining adjacent unit cells.

In an embodiment of the invention, the frequency or phase of the at least one first clock signal received by each of the at least one interface cell from the clock supply device is not completely the same.

In an embodiment of the invention, the at least one first clock signal received by each of the at least one interface cell from the clock supply device is a differential pair signal.

Based on the above, the clock supply device of the embodiment of the present invention can provide a working clock signal required for operation of each unit cell in the poly unit cell by transmitting at least one interface cell and a signal transmission line group in the poly unit wafer. The multi-cell wafer is usable (operable) after it is connected to the required power and signal. When the poly unit wafer has not been re-cut, the data can be dispersed in a plurality of unit cells in the poly unit wafer. The signals of different unit cells in the multi-cell wafer can be transmitted through the signal transmission line group between the unit cells. In addition, the user can elastically cut the polycrystalline silicon wafer in units of unit cells according to actual applications, required computing power or cost considerations, and cut into a plurality of sub-wafers, wherein the cut portions are cut. The sub-chip can still be used after it has been connected to the required power and signal (still operational). Moreover, the clock transmission mode between the unit cells can be adjusted by changing the preset clock selection order in each unit cell. Therefore, the flexibility of the design of the clock supply system can be increased. In addition, each unit cell can adjust the working clock signal according to its own operational requirements or physical characteristics, so that each unit cell can operate at different time segments or at different time points. In this way, the instantaneous power consumption of the clock supply system can be reduced, and the switching noise generated when the working clock signals of the respective cells are simultaneously changed can be reduced, thereby improving the overall stability of the clock supply system.

The above described features and advantages of the invention will be apparent from the following description.

DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to the exemplary embodiments embodiments In addition, wherever possible, the same reference numerals in the drawings

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a clock supply system 100 according to an embodiment of the invention. The clock supply system 100 can include a multi-cell wafer 110 and a clock supply device 120. The poly unit wafer 110 may include a semiconductor substrate SUB, a plurality of unit cells 111 to 114, and a plurality of signal transmission line groups OCI1 to OCI4, but the invention is not limited thereto. The cells 111-114 may be disposed and arranged on the semiconductor substrate SUB with at least one spaced space between adjacent cells. In addition, each of the signal transmission line groups OCI1 to OCI4 can be disposed in a space between adjacent cells, and can be used as a medium for signal transmission operations between adjacent cells (for example, a clock transmission operation or a data transmission operation). . It will be appreciated that the poly cell wafer 110 is usable (operable) after the desired power and signal are connected.

For example, the signal transmission line group OCI1 may be disposed on a space between the unit cell 111 and the unit cell 112 adjacent thereto. The signal transmission line group OCI1 can be coupled to the cells 111, 112 and act as a medium for signal transmission operations between the cells 111, 112, such as clock transmission actions or data transmission actions. When the poly unit wafer 110 has not been re-cut, the material may be dispersed in a plurality of unit cells (e.g., unit cells 111 to 114) in the poly unit wafer 110. In addition, the space between adjacent cells can provide a space for cutting as a scribe line. In other words, when the required number of unit cells can be small, part of the space can be cut by the cutting action to cut off part of the signal transmission line group (for example, signal transmission line group OCI2, OCI4), so as to The cell wafer 110 is diced into a plurality of sub-wafers, and the diced sub-wafers are still usable (still operational) after the required power and signal are connected.

Each of the signal transmission line groups OCI1 to OCI4 may include a plurality of wires which may be formed using one or more layers of patterned metal layers covering the semiconductor substrate SUB. In addition, each of the cells 111-114 may have a plurality of pads PAD, which may be disposed on the surface layers of the cells 111-114.

There may be at least one interface unit cell (e.g., unit cell 111) in unit cells 111-114. The clock supply device 120 can be coupled to the interface cell (cell 111) and can provide the cell 111 through the signal transmission line group OCI1~OCI4 between the interface cell (cell 111) and the cells 111-114. ~114 working clock signal required for operation.

Incidentally, the number and arrangement of the cells 111-114 of the polycrystalline cell wafer 110 shown in FIG. 1 are merely an example and are not intended to limit the present invention. In fact, the number and arrangement of the unit cells of the poly unit cell proposed by the present invention can be adjusted by the designer according to actual application or design requirements.

In an exemplary embodiment of the present invention, the clock supply device 120 can be electrically connected to the pad PAD (eg, the pad PAD1) on the interface cell (cell 111) through the package wiring, but the present invention Not limited to this. In another exemplary embodiment of the present invention, the clock supply device 120 can also pass through a flip chip wafer bonding technique and a pad PAD (eg, pad PAD1) on the interface cell (cell 111). Produce an electrical connection. The invention does not limit the electrical connection of the clock supply device 120 to the pad PAD on the interface cell (cell 111).

In the exemplary embodiment shown in FIG. 1 , the cell 111 can be coupled to the clock supply device 120 through one of the pads PAD1 to receive the first clock signal PAD_CKI1, wherein the first clock signal PAD_CKI1 can be For example, a full swing digital signal, but the invention is not limited thereto.

1 and FIG. 2, FIG. 2 is a schematic diagram of a clock supply system 100' according to another embodiment of the present invention. The clock supply system 100' shown in FIG. 2 can also include a multi-cell wafer 110 and a clock supply device 120. The poly unit wafer 110 may include a semiconductor substrate SUB, a plurality of unit cells 111 to 114, and a plurality of signal transmission line groups OCI1 to OCI4. However, compared to FIG. 1, the unit cell 111 of FIG. 2 can be coupled to the clock supply device 120 through the two pads PAD1, PAD2 to receive the first clock signals PAD_CKI1, PAD_CKI2, respectively, wherein the first clock signal PAD_CKI1, PAD_CKI2 may be, for example, a small swing of a differential pair of signals. In this way, under the premise of not affecting the frequency of the first clock signals PAD_CKI1, PAD_CKI2, the clock supply system 100' can use the clock supply device 120 with lower driving capability to achieve power saving and reduce hardware cost. effect. In addition, the clock supply system 100 shown in FIG. 1 is similar to the operation mode of the clock supply system 100' shown in FIG. 2, so only the operation of the clock supply system 100 shown in FIG. 1 will be described in detail below. The clock supply system 100' shown in FIG. 2 can be derived in the same manner.

Please refer to FIG. 1 and FIG. 3 at the same time. FIG. 3 is a flow chart of clock transmission between cells according to an embodiment of the invention. After the clock supply system 100 is started, in step S320, each unit cell can determine whether the first clock signal is received from the clock supply device. Taking FIG. 1 as an example, the cells 111-114 can respectively determine whether the first clock signal PAD_CKI1 is received from the clock supply device 120, wherein the unit cell 111 can determine that the first time can be received from the clock supply device 120. The pulse signal PAD_CKI1, and the cells 112-114 can determine that the first clock signal PAD_CKI1 is not received from the clock supply device 120.

If the result of the determination in step S320 is YES, step S330 is performed. Taking the unit cell 111 of FIG. 1 as an example, the unit cell 111 can select the first clock signal PAD_CKI1 as the working clock signal of the unit cell 111; the unit cell 111 can use the first clock signal PAD_CKI1 as the second clock. The signal OCI_HCK is transmitted along the first direction (eg, to the right of the unit cell 111) to the first adjacent unit cell (eg, the unit cell 112), and the unit cell 111 can use the first clock signal PAD_CKI1 as the third time. The pulse signal OCI_VCK is transmitted along a second direction (eg, above the unit cell 111) to a second adjacent unit cell (eg, cell 113).

If the result of the determination in step S320 is NO, step S340 is performed. Taking the cells 112, 113 of FIG. 1 as an example, the cells 112, 113 can then determine whether a second clock signal OCI_HCK is received from the third adjacent cell, wherein the third adjacent cell can be, for example, Adjacent unit cells located on the left side of the unit cells 112, 113, but the invention is not limited thereto. For example, the third adjacent unit cell of unit cell 112 can be, for example, unit cell 111, while the third adjacent unit cell of unit cell 113 is not present. Since the unit cell 111 can transmit the second clock signal OCI_HCK to the unit cell 112 in step S330, the unit cell 112 can determine in step 340 that the second clock signal OCI_HCK can be received from the unit cell 111. In addition, since the left cell of the cell 113 does not exist, the cell 113 can judge in step 340 that the second clock signal OCI_HCK is not received.

If the result of the determination in step S340 is YES, step S350 is performed. Taking the unit cell 112 of FIG. 1 as an example, the unit cell 112 may select the second clock signal OCI_HCK from the third adjacent unit cell (ie, the unit cell 111) as the working clock signal of the unit cell 112, and the crystal Cell 112 may transmit second clock signal OCI_HCK in a first direction (eg, to the right) to a first adjacent unit cell (eg, a unit cell to the right of unit cell 112, not shown).

If the result of the determination in step S340 is NO, step S360 is performed. Taking the unit cell 113 of FIG. 1 as an example, the unit cell 113 can select a third clock signal from the fourth adjacent unit cell as the working clock signal of the unit cell 113, wherein the fourth adjacent unit cell can be For example, adjacent cells are located below the unit cell 113, but the invention is not limited thereto. For example, the fourth adjacent unit cell of unit cell 113 can be, for example, unit cell 111. Since the unit cell 111 can transfer the third clock signal OCI_VCK to the unit cell 113 in step S330, the unit cell 113 can select the third clock signal OCI_VCK from the unit cell 111 as the working clock signal of the unit cell 113. . The unit cell 113 may transmit the third clock signal OCI_VCK as the second clock signal OCI_HCK and transmit it along the first direction (eg, the right side of the unit cell 113) to the first adjacent unit cell (cell 114), and The unit cell 113 can transmit the third clock signal OCI_VCK in a second direction (eg, above) to a second adjacent unit cell (eg, a unit cell above the unit cell 113, not shown).

Similarly, the unit cell 114 can determine in step 340 that the second clock signal OCI_HCK can be received from the unit cell 113, so the unit cell 114 can select the second clock signal OCI_HCK from the unit cell 113 in step 350 to do The working clock signal of the unit cell 114, and the unit cell 114 can transmit the second clock signal OCI_HCK along the first direction (eg, the right side) to the first adjacent unit cell (eg, the unit cell to the right of the unit cell 114) , not shown).

In this way, the cells 111-114 shown in FIG. 1 can obtain the working clock signals required for their operation according to the clock transmission mode shown in FIG. 3, respectively. Incidentally, in the above exemplary embodiment of the present invention, the unit cell 111 is an interface unit cell, the first direction is right, the second direction is upward, and the first adjacent unit cell of each unit cell is located in each crystal. The right side of the cell, the second adjacent unit cell of each unit cell is located above each unit cell, the third adjacent unit cell of each unit cell is located on the left side of each unit cell, and the fourth adjacent unit cell of each unit cell is located at each The underside of the unit cell is merely an example and is not intended to limit the invention.

It is worth mentioning that when the unit cells 111-114 shown in Fig. 1 react to their own working clock signals and operate together at the same time zone or at the same time point, the clock supply system 100 may be caused. The instantaneous power consumption is too large to reduce the transient stability of the power supply network of the clock supply system 100. In addition, if the operating clock signals of the respective cells 111-114 are rotated at the same time point, the switching noise generated by the cells may be coupled to the signal transmission line group OCI1 through the semiconductor substrate SUB. ~OCI4, thereby reducing the signal transmission quality of the signal transmission line group OCI1~OCI4, especially in the case where the working clock signals of the respective unit cells 111-114 are high frequency signals.

Therefore, in an exemplary embodiment of the present invention, each of the unit cells 111-114 can adjust its working clock signal according to its own operational requirements or physical characteristics (such as temperature, but not limited thereto), so that each unit cell The cells 111-114 can operate at different time segments or at different points in time. In this way, the instantaneous power consumption of the clock supply system 100 can be reduced, and the switching noise generated when the operating clock signals of the respective cells 111-114 are rotated at the same time point can be reduced.

Furthermore, please refer to FIG. 1 and FIG. 4 at the same time. FIG. 4 is a schematic diagram of a clock waveform according to an embodiment of the invention. Taking the unit cell 111 of FIG. 1 as an example, when the unit cell 111 determines that the first clock signal PAD_CKI1 can be received from the clock supply device 120 (that is, the unit cell 111 is an interface unit cell), the unit cell 111 can be The one-shot signal PAD_CKI1 generates a second synchronization signal OCI_HSYNC corresponding to the second clock signal OCI_HCK. In addition, the unit cell 111 may also generate a third synchronization signal OCI_VSYNC corresponding to the third clock signal OCI_VCK according to the first clock signal PAD_CKI1. That is, the second synchronization signal OCI_HSYNC and the third synchronization signal OCI_VSYNC may be generated by the interface cell (ie, the cell 111).

Similarly to the transmission mode of the clock signal described above with respect to FIG. 3, the unit cell 111 can also transmit the second synchronization signal OCI_HSYNC along the first direction (eg, the right side) to the first adjacent unit cell (cell 112). And the unit cell 111 can also transmit the third synchronization signal OCI_VSYNC along the second direction (eg, above) to the second adjacent unit cell (cell 113). Therefore, the transmission manner of the synchronization signal (for example, the second synchronization signal OCI_HSYNC or the third synchronization signal OCI_VSYNC) between the unit cells can be deduced by referring to the related descriptions of FIG. 1 and FIG. 3 above, and details are not described herein again.

As shown in FIG. 4, the period NT of the second synchronization signal OCI_HSYNC and the period NT of the third synchronization signal OCI_VSYNC is greater than the period T (or unit period T) of the first clock signal PAD_CKI1, and the period NT of the second synchronization signal OCI_HSYNC The period NT with the third synchronization signal OCI_VSYNC is an integer multiple (multiple of N) of the period T of the first clock signal PAD_CKI1, wherein the multiple N may be, for example, 256, but is not limited thereto. It is worth mentioning here that the multiple N can be a parameter stored in the unit cell 111 and can be set according to actual application or design requirements.

In addition to this, the unit cell 111 can select the first clock signal PAD_CKI1 as the input clock signal of the unit cell 111. The unit cell 111 may select the second synchronization signal OCI_HSYNC or the third synchronization signal OCI_VSYNC as the input synchronization signal of the unit cell 111, and accordingly generate the operational clock signal of the unit cell 111. The cells 112, 114 may select the second clock signal OCI_HCK as the input clock signal for the cells 112, 114. The cells 112, 114 may select the second synchronization signal OCI_HSYNC as the input sync signal for the cells 112, 114 and thereby generate the operational clock signals for the cells 112, 114. Similarly, the cell 113 can select the third clock signal OCI_VCK as the input clock signal for the cell 113. The cell 113 can select the third sync signal OCI_VSYNC as the input sync signal of the cell 113 and accordingly generate the operational clock signal of the cell 113.

In an embodiment of the present invention, the cells 111-114 can be operated in a burst mode without considering reducing the operating voltage of the cells 111-114 and reducing the frequency of the working clock signal. . As shown in FIG. 5A, FIG. 5A is a timing diagram of the operation of the cells 111-114 in the burst mode according to an embodiment of the invention. The unit cells 111~114 can start to continuously operate K unit periods T (ie, K×T after the input synchronization signal SYNC is triggered and delayed by M unit periods T (ie, M×T) according to the generated working clock signal OPCK. ). The values M and K of the respective unit cells 111 to 114 may be parameters stored in the respective unit cells 111 to 114, and are positive integers. The value M of each of the unit cells 111-114 can be set to different values according to actual application or design requirements, and the value K of each unit cell 111-114 can also be set to different values according to actual application or design requirements, so that Each of the cells 111-114 can operate at different time segments among the periods NT of the input sync signal SYNC. In this way, the instantaneous power consumption of the clock supply system 100 can be reduced, and the switching noise generated when the operating clock signals OPCK of the respective cells 111 to 114 are turned can be reduced.

For example, it is assumed here that the period NT of the input synchronization signal SYNC is 256 unit periods T. In order to allow each of the cells 111-114 to operate in different time segments of the period NT (ie, 256 unit periods T) of the input sync signal SYNC, the cell 111 can be triggered and delayed by 2 at the input sync signal SYNC. After the unit period T, the continuous operation of 10 unit periods T is started; the unit cell 112 can be continuously operated for 20 unit periods T after the input synchronization signal SYNC is triggered and delayed by 21 unit periods T; the unit cell 113 can be input. After the synchronization signal SYNC is triggered and delayed by 50 unit periods T, 60 consecutive unit periods T are continuously operated; and the unit cell 114 can be continuously operated for 100 unit periods after the input synchronization signal SYNC is triggered and delayed by 120 unit periods T. T.

In another embodiment of the invention, the cells 111-114 can also be operated in a continuous mode of lower operating voltage. Please refer to FIG. 5B. FIG. 5B is a timing diagram of the operation of the cells 111-114 in the continuous mode according to another embodiment of the invention. In detail, this embodiment can reduce the frequency of the working clock signal OPCK of the unit cells 111-114 and the phase of the working clock signal OPCK of the unit cells 111-114 to reduce the instantaneous power consumption of the clock supply system 100. And reducing the efficiency of switching noise generated when the operating clock signals of the respective cells 111-114 are in the OPCK transition state.

As shown in FIG. 5B, the cells 111-114 can start to work after the input synchronization signal SYNC is triggered and delayed by M unit periods T (ie, M×T) according to the generated working clock signal OPCK, and after starting work, It works once every K unit periods T (ie, K×T), wherein the duty cycle of the working clock signal OPCK of the unit cells 111-114 can be 50% (ie, (K×T)÷2 ), but the invention is not limited thereto. The values M and K of the respective unit cells 111 to 114 may be parameters stored in the respective unit cells 111 to 114, and are positive integers. The value M of each of the unit cells 111-114 can be set to different values according to actual application or design requirements, and the value K of each unit cell 111-114 can also be set to different values according to actual application or design requirements, so that Each of the cells 111-114 can operate at different time points in the period NT of the input synchronization signal SYNC to reduce the instantaneous power consumption of the clock supply system 100, and can reduce the operating clock signals of the respective cells 111-114. Switching noise generated when OPCK is in transition.

For example, it is also assumed that the period NT of the input synchronization signal SYNC is 256 unit periods T. In order to allow each of the cells 111-114 to operate at different time points in the period NT (ie, 256 unit periods T) of the input sync signal SYNC, the unit cell 111 can be triggered and delayed by 2 units at the input sync signal SYNC. After the period T, the operation starts and runs every 20 unit periods T after starting the operation; the unit cell 112 can be started after the input synchronization signal SYNC is triggered and delayed by 4 unit periods T, and every time after starting operation, 20 unit cycles T are operated once; the cell 113 can be started after the input sync signal SYNC is triggered and delayed by 6 unit periods T, and operates every 20 unit periods T after starting operation; and the cell can be made 114 starts operation after the input sync signal SYNC is triggered and delayed by 8 unit periods T, and operates every 20 unit periods T after starting operation.

Please refer to FIG. 6. FIG. 6 is a schematic diagram of clock transmission between cells according to another embodiment of the present invention. Similar to the architecture of the clock supply system 100 shown in FIG. 1, the clock supply system 200 shown in FIG. 6 can also include a multi-cell wafer 210 and a clock supply device 220. The poly cell wafer 210 may also include a semiconductor substrate SUB, a plurality of unit cells 211 to 219, and a plurality of signal transmission line groups OCI. Therefore, the architecture of the clock supply system 200 shown in FIG. 6 can refer to the related description of FIG. 1 above, and details are not described below. However, the clock transmission mode between the unit cells 211 to 219 shown in FIG. 6 is different from that of FIGS. 1 and 3, wherein the arrow direction shown in FIG. 6 is the clock transmission direction in the clock supply system 200. .

As shown in FIG. 6, the cells 211 to 219 can respectively determine whether the first clock signal PAD_CKI1 is received from the clock supply device 220, wherein the cell 215 (ie, the interface cell) can determine the self-clockable device. 220 receives the first clock signal PAD_CKI1, and the cells 211~214, 216~219 can determine that the first clock signal PAD_CKI1 is not received from the clock supply device 220.

Since the unit cell 215 can receive the first clock signal PAD_CKI1 from the clock supply device 220, the unit cell 215 can select the first clock signal PAD_CKI1 as the working clock signal of the unit cell 215. In addition, unit cell 215 can use first clock signal PAD_CKI1 as second clock signal OCI_CK and transmit to all adjacent unit cells (eg, cells 212, 214, 216, 218).

The unit cells 211 to 214 and 216 to 219 may select the second clock signal OCI_CK from one of the adjacent unit cells as the working clock signal of the unit cells 211 to 214 and 216 to 219. And the cells 211~214, 216~219 can transmit the selected second clock signal OCI_CK to the remaining adjacent unit cells.

For example, unit cell 212 may select a second clock signal OCI_CK from one of the adjacent unit cells (ie, unit cell 215) and transmit a second clock signal OCI_CK from unit cell 215 to the remaining adjacent ones. The unit cells (i.e., the unit cells 211, 213 and the unit cell (not shown) located below the unit cell 212). The cell 214 may select a second clock signal OCI_CK from one of the adjacent cells (ie, cell 215) and transmit a second clock signal OCI_CK from the cell 215 to the remaining adjacent cells (ie, The unit cells 211, 217 and the unit cell (not shown) located to the left of the unit cell 214. In particular, since the unit cell 211 can receive the second clock signal OCI_CK from two adjacent unit cells (ie, the unit cells 212, 214), the unit cell 211 can be selected according to a preset clock selection order. a second clock signal OCI_CK of one of the adjacent unit cells (for example, a second clock signal OCI_CK from the unit cell 212 may be selected), and the selected second clock signal OCI_CK is transmitted to the remaining adjacent unit cells (ie, a unit cell (not shown) located to the left and below the unit cell 211). The clock transmission mode of the cell 213, 216~219 can be referred to the above description by analogy, so it will not be described again. It can be seen that the polycrystalline cell wafer 210 can be centered on the interface cell (ie, the cell 215), and sequentially transmits the second clock signal OCI_CK to the poly cell through the signal transmission line group OCI and the adjacent unit cell. The remaining unit cells 211 to 214, 216 to 219 of the wafer 210.

It should be particularly noted that the clock transmission mode between the unit cells described in the above embodiments of FIG. 3 and FIG. 6 is merely an example and is not intended to limit the present invention. The clock transmission mode between the unit cells of the present invention can be adjusted by changing the preset clock selection order in each unit cell.

Please refer to FIG. 7. FIG. 7 is a schematic diagram of clock transmission inside the clock supply system 300 according to another embodiment of the invention. Similar to the architecture of the clock supply system 200 shown in FIG. 6, the clock supply system 300 shown in FIG. 7 can also include a multi-cell wafer 310 and a clock supply device 320. The poly unit wafer 310 may also include a semiconductor substrate SUB, a plurality of unit cells 311 to 319, and a plurality of signal transmission line groups OCI.

However, compared to the unit cells 211 to 219 shown in FIG. 6 having only one interface unit cell (for example, the unit cell 215), the unit cells 311 to 319 shown in FIG. 7 may have a plurality of interface unit cells (for example, crystal grains). Cells 311, 315, 319). The clock supply device 320 can be coupled to the interface cells (cells 311, 315, 319) and can pass through between the interface cells (cells 311, 315, 319) and the cells 311-319. The signal transmission line group OCI provides the working clock signal required for the operation of the unit cells 311~319.

In particular, the frequency or phase of the first clock signals PAD_CKI31, PAD_CKI32, and PAD_CKI33 received by the unit cells 311, 315, and 319 from the clock supply device 320 may be identical or not identical, depending on the actual application or design. Depending on the needs. In addition, the clock transmission mode between the unit cells 311 to 319 shown in FIG. 7 can be referred to the related description of FIG. 1 to FIG. 6, and details are not described below. It should be noted that the number and arrangement positions of the interface cells in the embodiment shown in FIG. 7 are only an example and are not intended to limit the present invention. In other words, the designer can adjust the number and arrangement position of the interface cells in the poly unit wafer 310 according to actual application or design requirements.

In summary, the clock supply device of the embodiment of the present invention can provide the working clock required for each cell operation in the multi-cell wafer through at least one interface cell and signal transmission line group in the poly unit wafer. The signal, in which the multi-cell wafer is connected to the required power and signal, is usable (operable). When the poly unit wafer has not been re-cut, the data can be dispersed in a plurality of unit cells in the poly unit wafer. The signals of different unit cells in the multi-cell wafer can be transmitted through the signal transmission line group between the unit cells. In addition, the user can elastically cut the polycrystalline silicon wafer in units of unit cells according to actual applications, required computing power or cost considerations, and cut into a plurality of sub-wafers, wherein the cut portions are cut. The sub-chip can still be used after it has been connected to the required power and signal (still operational). Moreover, the clock transmission mode between the unit cells can be adjusted by changing the preset clock selection order in each unit cell. Therefore, the flexibility of the design of the clock supply system can be increased. In addition, each unit cell can adjust the working clock signal according to its own operational requirements or physical characteristics, so that each unit cell can operate at different time segments or at different time points. In this way, the instantaneous power consumption of the clock supply system can be reduced, and the switching noise generated when the working clock signals of the respective cells are simultaneously changed can be reduced, thereby improving the overall stability of the clock supply system.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 100', 200, 300‧‧‧ clock supply system
110, 210, 310‧‧‧Multi-cell wafer
111~114, 211~219, 311~319‧‧‧ unit cell
120, 220, 320‧‧‧ clock supply device
M, K‧‧‧ values
OCI, OCI1~OCI4‧‧‧ Signal Transmission Line Group
OCI_HCK, OCI_CK‧‧‧ second clock signal
OCI_HSYNC‧‧‧Second sync signal
OCI_VCK‧‧‧ third clock signal
OCI_VSYNC‧‧‧ third synchronization signal
OPCK‧‧‧ working clock signal
PAD, PAD1, PAD2‧‧‧ pads
PAD_CKI1, PAD_CKI2, PAD_CKI31~PAD_CKI33‧‧‧ first clock signal
SUB‧‧‧Semiconductor substrate
SYNC‧‧‧ input sync signal
S320, S330, S340, S350, S360‧‧ steps
T‧‧‧ cycle, unit period
NT‧‧ cycle

The following drawings are a part of the specification of the invention, and illustrate the embodiments of the invention FIG. 1 is a schematic diagram of a clock supply system according to an embodiment of the invention. 2 is a schematic diagram of a clock supply system according to another embodiment of the invention. FIG. 3 is a flow chart of clock transmission between cells according to an embodiment of the invention. FIG. 4 is a schematic diagram of a clock waveform according to an embodiment of the invention. FIG. 5A is a timing diagram of a cell operating in a burst mode according to an embodiment of the invention. FIG. 5B is a timing diagram of cell operation in a continuous mode according to another embodiment of the invention. FIG. 6 is a schematic diagram of clock transmission between cells according to another embodiment of the invention. FIG. 7 is a schematic diagram of clock transmission inside a clock supply system according to another embodiment of the invention.

100‧‧‧clock supply system

110‧‧‧Multicell wafer

111~114‧‧‧cell

120‧‧‧clock supply device

OCI1~OCI4‧‧‧Signal transmission line group

OCI_HCK‧‧‧second clock signal

OCI_HSYNC‧‧‧Second sync signal

OCI_VCK‧‧‧ third clock signal

OCI_VSYNC‧‧‧ third synchronization signal

PAD, PAD1‧‧‧ pads

PAD_CKI1‧‧‧First clock signal

SUB‧‧‧Semiconductor substrate

Claims (11)

A clock supply system comprising: a polycrystalline wafer comprising: a semiconductor substrate; a plurality of unit cells arranged on the semiconductor substrate, each of the cells having at least one space between adjacent cells; a plurality of signal transmission line groups, each of the signal transmission line groups being disposed on the space between adjacent cells, and configured to perform a signal transmission operation between adjacent cells, wherein the poly unit wafer is usable, and the The polycrystalline silicon wafer is cut through a portion of the spaced spaces to cut a portion of the signal transmission line groups, such that the poly unit wafer is divided into a plurality of sub-wafers, wherein the sub-wafers of the cut portions are still usable And a clock supply device coupled to at least one of the unit cells, wherein the clock supply device provides the operation of each of the unit cells through the at least one interface cell and the signal transmission line groups A working clock signal. The clock supply system of claim 1, wherein each of the unit cells has a plurality of pads, and at least one of the pads on each of the at least one interface cells is coupled thereto The pulse supply device receives at least one first clock signal. The clock supply system of claim 2, wherein: when each of the unit cells determines that the at least one first clock signal is received from the clock supply device, each of the unit cells selects the at least one a clock signal as the working clock signal of each of the unit cells, each of the unit cells transmitting the at least one first clock signal as at least one second clock signal and transmitting to the first direction An adjacent unit cell, and each of the unit cells transmits the at least one first clock signal as at least a third clock signal and in a second direction to the second adjacent unit cell. The clock supply system of claim 3, wherein: when each of the unit cells determines that the at least one first clock signal is not received from the clock supply device, each of the unit cells determines whether The three adjacent cells receive the at least one second clock signal. If the determination result is yes, each of the cells selects the at least one second clock signal as the working clock signal of each of the unit cells. And each of the unit cells transmits the at least one second clock signal to the first adjacent unit cell along the first direction; if the determination result is no, each of the unit cells is selected from the fourth adjacent unit cell The at least one third clock signal is used as the working clock signal of each of the unit cells, and each of the unit cells transmits the at least one third clock signal to the first adjacent crystal along the first direction And each of the cells transmits the at least one third clock signal along the second direction to the second adjacent unit cell. The clock supply system of claim 3, wherein: when each of the unit cells determines that the at least one first clock signal is received from the clock supply device, each of the unit cells is according to the at least one a clock signal generates a second synchronization signal corresponding to the at least one second clock signal, and each of the unit cells generates a third corresponding to the at least one third clock signal according to the at least one first clock signal a synchronization signal, each of the cells transmits the second synchronization signal to the first adjacent unit cell along the first direction, and each of the unit cells transmits the third synchronization signal to the second direction along the second direction a second adjacent unit cell, wherein each of the unit cells selects the at least one first clock signal as an input clock signal of each of the unit cells, and each of the unit cells selects the second synchronization signal or the first The three synchronization signals are used as an input synchronization signal of each of the unit cells, and accordingly, the working clock signal of each of the unit cells is generated, wherein a period of the second synchronization signal and a period of the third synchronization signal are greater than the At least one period of the first clock signal, and the second synchronization signal The period of the number and the period of the third synchronization signal are integer multiples of the period of the at least one first clock signal. The clock supply system of claim 5, wherein, when each of the unit cells determines that the at least one first clock signal is not received from the clock supply device, each of the unit cells determines whether it is from the third The adjacent unit cell receives the at least one second clock signal and the second synchronization signal. If the determination result is yes, each of the unit cells selects the at least one second clock signal and the second synchronization signal to respectively perform An input clock signal and an input synchronization signal for each of the unit cells are generated to generate the working clock signal of each of the unit cells, and the at least one second clock signal and the second synchronization signal are along the Transmitting to the first adjacent unit cell in a first direction; if the determination result is no, each of the unit cells selects the at least one third clock signal from the fourth adjacent unit cell and the third synchronization signal respectively The input clock signal of each of the unit cells and the input synchronization signal are used to generate the working clock signal of each of the unit cells, and each of the unit cells synchronizes the at least one third clock signal with the third Transmitting a signal to the first adjacent unit cell along the first direction, and The cell of the at least one third clock signal and the third sync signal is transmitted along the second direction to the second adjacent cell. The clock supply system of claim 6, wherein each of the unit cells generates the working clock signal according to the input clock signal and the input synchronization signal, so that each of the unit cells reacts to the working time. The pulse signals operate at different time segments or at different time points within the period of the input sync signal. The clock supply system of claim 2, wherein, when each of the unit cells determines that the at least one first clock signal is received from the clock supply device, each of the unit cells selects the at least one first The clock signal is used as the working clock signal of each of the unit cells, and each of the unit cells uses the at least one first clock signal as at least one second clock signal and transmits to all adjacent unit cells. The clock supply system of claim 8, wherein when the unit cell determines that the at least one first clock signal is not received from the clock supply device, each of the unit cells is selected from a partial phase The at least one second clock signal of one of the adjacent unit cells is used as the working clock signal of each of the unit cells, and each of the unit cells transmits the selected at least one second clock signal To the remaining adjacent unit cells. The clock supply system of claim 2, wherein the frequency or phase of the at least one first clock signal received by the at least one interface cell from the clock supply device is not completely the same. The clock supply system of claim 2, wherein the at least one first clock signal received by the at least one interface cell from the clock supply device is a differential pair signal.