TW201631706A - Memory device and method of fabricating the same - Google Patents

Abstract

Provided is a memory device including a plurality of word line sets in the substrate, a plurality of bit lines, a plurality of capacitors, and a plurality of contact plugs. Each word line set has two buried word lines. The bit lines are located on the substrate across the word line sets. The capacitors are located on the substrate between the bit lines, and located on the substrate of both side of the word line sets. The contact plugs are located between the capacitors and the substrate. A material of the contact plugs includes metal.

Description

Memory element and method of manufacturing same

The present invention relates to a memory element and a method of fabricating the same, and more particularly to a memory element having a shallow junction and a method of fabricating the same.

In the case where the accumulation of memory elements is increased and the size of the components is reduced, the line width in the components is gradually reduced, resulting in contact resistance between the storage node contact and the source/drain regions in the device. The increase, resulting in a slower resistance-capacitance delay (RC Delay), which in turn affects the operating speed of the component.

In order to solve this problem, metal telluride is usually used to reduce the resistance between the storage node contact window and the source/drain region. However, in the process of forming a metal telluride, the germanium in the substrate is depleted, causing a problem of junction leakage (Junction Leakage) in the source/drain region of the memory element, thereby affecting the device performance. Therefore, how to reduce the resistance value between the storage node contact window and the source/drain region, and at the same time avoid the problem of junction leakage will become a very important issue.

The present invention provides a memory element having a shallow junction and a method of fabricating the same that reduces the resistance value of the storage node contact window.

A memory element of the present invention includes a plurality of word line sets, a plurality of bit lines, a plurality of capacitors, and a plurality of contact plugs in the substrate. Each word line group has two buried word lines. The bit lines are on the substrate and traverse the group of word lines. Capacitors are located on the substrate between the bit lines and on the substrate on either side of the word line set. The contact plug is located between the capacitor and the substrate. The material of the contact plug includes metal.

The present invention provides a method of manufacturing a memory element, the steps of which are as follows. A substrate is provided. The substrate has a first zone and a second zone. A plurality of gate structures are formed on the substrate of the first region. A plurality of bit lines are formed on the substrate of the second region. A selective epitaxial growth process is performed to form a plurality of epitaxial layers on the substrate between the gate structures and on the substrate between the bit lines. A metal layer is formed on the substrate to cover the epitaxial layer. A tempering process is performed to form a plurality of metal telluride layers on the substrate between the gate structures and on the substrate between the bit lines. A plurality of first contact plugs are formed on the metal telluride layer between the gate structures, and a plurality of second contact plugs are simultaneously formed on the metal germanide layer between the bit lines. A plurality of capacitors are formed on the second contact plug of the second region.

Another method of fabricating a memory element of the present invention comprises: providing a substrate. The substrate has a first zone and a second zone. A plurality of gate structures are formed on the substrate of the first region. A plurality of bit lines are formed on the substrate of the second region. A liner is conformally formed on the substrates of the first zone and the second zone. A metal layer is formed on the substrate to cover the liner. A tempering process is performed to convert the liner into a metal halide layer. Formed on the metal telluride layer Conductor layer. The conductor layer and the metallization layer are patterned to form a plurality of first contact plugs between the gate structures, and at the same time a plurality of second contact plugs are formed between the bit lines. A plurality of capacitors are formed on the second contact plug of the second region.

A memory element of the present invention includes a plurality of word lines, a plurality of bit lines, a plurality of capacitors, a plurality of contact plugs, and a plurality of metal germanide layers in the substrate. The bit line is on the substrate and traverses the word line. Capacitors are located on the substrate between the bit lines and on the substrate on either side of the word line. The contact plug is located between the capacitor and the substrate. The material of the contact plug includes metal. A metal telluride layer is between the contact plug and the substrate.

Accordingly, the present invention can reduce the resistance value between the storage node contact window and the source/drain region, and can also avoid consuming defects in the substrate. The above described features and advantages of the present invention will be more apparent from the following description.

10, 20, 30, 40, 70‧‧‧ openings

50, 60‧‧‧ doped area

100‧‧‧Base

101‧‧‧Isolation structure

102‧‧‧ gate structure

104, 204‧‧‧ gate dielectric layer

106, 110, 206, 210‧‧‧ conductor layers

108, 208‧‧‧ barrier layer

112, 212‧‧‧ top cover

114, 214‧‧ ‧ spacer

116, 118, 118a, 118b, 118c, 136, 136a‧‧‧ dielectric layer

120‧‧‧hard mask layer

122‧‧‧ patterned mask layer

124, 224‧‧ ‧ epitaxial layer

126, 226, 126a, 226a‧‧‧ metal layers

128, 228, 328, 328a, 328b‧‧‧ metal telluride layers

130‧‧‧First contact plug

132‧‧‧Wire layer

134, 134a‧‧ ‧ protective layer

202‧‧‧ bit line

203‧‧‧ character line group

203a, 203b‧‧‧ Buried word line

230‧‧‧second contact plug

234‧‧‧ capacitor

234a‧‧‧ lower electrode

234b‧‧‧ dielectric layer

234c‧‧‧Upper electrode

240‧‧‧ bit line contact window

324‧‧‧ lining

330‧‧‧Conductor layer

232‧‧‧Conductor pad

AA‧‧‧Active Area

D1‧‧‧ first direction

D2‧‧‧ second direction

L1‧‧‧ long side

L2‧‧‧ Short side

Θ‧‧‧ angle

R1‧‧‧ first district

R2‧‧‧Second District

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a top plan view of a memory device in accordance with one embodiment of the present invention.

2A to 2G are schematic cross-sectional views showing a manufacturing flow of the memory element of the embodiment taken along line A-A and line B-B of Fig. 1.

3A to 3F are schematic cross-sectional views showing a manufacturing flow of a memory element along another embodiment of the A-A line and the B-B line of Fig. 1.

Referring to FIG. 1, the present invention provides a memory device including: a substrate 100, a plurality of gate structures 102, a plurality of first contact plugs 130, a plurality of word line groups 203, a plurality of bit lines 202, and a plurality of active devices. AA, a plurality of capacitors 234, and a plurality of second contact plugs 230. The substrate 100 has a first region R1 and a second region R2. In this embodiment, the first region R1 is, for example, a peripheral circuit region, and the second region R2 is, for example, a memory cell array region.

The gate structure 102 is located on the substrate 100 of the first region R1. The gate structures 102 extend in the first direction D1 and are arranged in the second direction D2. The first contact plug 130 is located on the substrate 100 between the gate structures 102. Therefore, the first contact plug 130 can electrically connect the doped region 50 between the wire layer 132 and the gate structure 102. The word line group 203 is located in the substrate 100 of the second region R2. The word line group 203 extends along the second direction D2 and is arranged to each other along the first direction D1. Each word line group 203 has two buried word lines 203a, 203b. However, the present invention does not limit the number of word lines; for example, each word line group can also have only one word line. To avoid confusion, this structure is not called a word line group, but only Is the word line. The bit line 202 is located on the substrate 100 of the second region R2 and traverses the word line group 203 (or word line, not shown). The bit lines 202 extend along the first direction D1 and are arranged along the second direction D2. The above-described word line group 203 (or word line) and the above-described bit line 202 are substantially perpendicular to each other.

The active area AA is located on the substrate 100 of the second area R2. Each active area AA has a long side L1 and a short side L2, and the long side L1 traverses the corresponding word line group 203. A bit line contact window 240 is present at the overlap of each active area AA and the corresponding bit line 202. Therefore, each bit line 202 is traversable when traversing the corresponding word line group 203 A corresponding doped region (not shown) is electrically connected by a bit line contact window 240, and the doped region is located between the two buried word lines 203a, 203b.

In addition, the memory element of the embodiment further includes a plurality of isolation structures 101 (eg, shallow trench isolation structures) located in the substrate 100 of the second region R2 outside the active region AA to electrically isolate the active regions AA. The longitudinal direction of the active area AA is at an angle θ to the direction in which the bit line 202 extends, for example, between 10 and 40 degrees.

Capacitor 234 is located on substrate 100 between bit lines 202. The capacitors 234 are arranged in a plurality of columns and a plurality of rows. The capacitor 234 is disposed on the substrate 100 on both sides of the word line group 203, in other words, the capacitor 234 every two rows and the word line group 203 having the two buried word lines 203a, 203b along the first direction D1 Alternate. The second contact plug 230 is located between the capacitor 234 and the substrate 100. The material of the contact plug 230 includes a metal. The metal of this embodiment includes tungsten, titanium nitride (TiN), cobalt, nickel, aluminum, or a combination thereof. Referring to FIG. 2A, the present invention provides a method of fabricating a memory device. First, a substrate 100 is provided. The substrate 100 has a first region R1 (such as a peripheral circuit region) and a second region R2 (such as a memory cell array region). Next, a plurality of gate structures 102 are formed on the substrate 100 of the first region R1. The gate structure 102 is sequentially stacked by the gate dielectric layer 104, the conductor layer 106, the barrier layer 108, the conductor layer 110, and the cap layer 112. The material of the gate dielectric layer 104 of this embodiment is, for example, hafnium oxide. The material of the conductor layer 106 is, for example, doped polysilicon, undoped polysilicon or a combination thereof. The material of the barrier layer 108 is, for example, titanium, titanium nitride, or a combination thereof. The material of the conductor layer 110 is, for example, tungsten. The material of the cap layer 112 is, for example, tantalum nitride. The gate structure 102 has spacers 114 on both sides. The material of the spacers 114 is, for example, ruthenium oxide, tantalum nitride or a combination thereof. The formation of each of the above layers is well known to those of ordinary skill in the art and will not be described in detail herein. A dielectric layer 116 is then formed over the substrate 100 between adjacent gate structures 102. The material of the dielectric layer of this embodiment is, for example, hafnium oxide, tantalum nitride, borophosphonium glass or the like. Thereafter, a chemical mechanical polishing process is performed to expose the top surface of the gate structure 102. On the other hand, a plurality of bit lines 202 are formed on the substrate 100 of the second region R2. The bit line 202 is sequentially stacked by the gate dielectric layer 204, the conductor layer 206, the barrier layer 208, the conductor layer 210, and the cap layer 212. The gate dielectric layer 204, the conductor layer 206, the barrier layer 208, the conductor layer 210, and the cap layer 212 of the bit line 202 in this embodiment are respectively connected to the gate dielectric layer 104, the conductor layer 106, and the gate of the gate structure 102. The material and formation method of the barrier layer 108, the conductor layer 110 and the cap layer 112 are the same, and will not be described herein. The bit line 202 differs from the gate structure 102 in its thickness, critical dimensions, and line spacing, as is well known to those of ordinary skill in the art and will not be described in detail herein. The bit line 202 has spacers 214 on both sides. The material of the spacer 214 is, for example, tantalum nitride. Dielectric layer 216 is then formed over substrate 100 between adjacent bit lines 202. The material of the dielectric layer of this embodiment is, for example, the same as described above. Thereafter, a chemical mechanical polishing process is performed to expose the top surface of the bit line 202. Since the dielectric layer 116 and the dielectric layer 216 are formed separately, the thickness of the two may be different. Next, a dielectric layer 118, a hard mask layer 120, and a patterned mask layer 122 are sequentially formed on the substrate 100 of the first region R1 and the second region R2. Specifically, the patterned mask layer 122 has an opening 10 and a plurality of openings 20. The opening 10 is disposed on the substrate 100 between adjacent gate structures 102 in the first region R1. The opening 20 is disposed on the substrate 100 between adjacent bit lines 202 in the second region R2. In this embodiment, the material of the dielectric layer 118 is, for example, ruthenium oxide. The material of the hard mask layer 120 is, for example, a tantalum material, a metal material, or a carbon material. The material of the patterned mask layer 122 is, for example, a photoresist. In addition, the embodiment further includes forming an isolation structure 101 (such as a shallow trench isolation structure) in the substrate 100 below the bit line 202 of the second region R2. The material of the isolation structure 101 is, for example, doped or undoped cerium oxide, high density plasma oxide, cerium oxynitride, spin-on silicon oxide, low dielectric constant dielectric material or combination. Referring to FIGS. 2A and 2B, an etching process is performed by patterning the mask layer 122 as a mask to expose a portion of the surface of the substrate 100. In detail, the patterned mask layer 122 is used as a mask to remove the hard mask layer 120 and the dielectric layer 118 under the opening 10 and the opening 20. Then, using the patterned hard mask layer 120 and the patterned dielectric layer 118 (not shown) as a mask, the dielectric layer 116 under the opening 10 and the dielectric layer 216 under the opening 20 are removed. Openings 30 are formed between adjacent gate structures 102, and a plurality of openings 40 are formed between adjacent bit lines 202. The opening 30 exposes a surface of a portion of the substrate 100 in the first region R1; the opening 40 exposes a portion of the surface of the substrate 100 in the second region R2. In addition, after performing the etching process, the substrate 100 of the first region R1 further has a portion of the dielectric layer 118a, wherein the dielectric layer 118a covers the gate structure 102. Next, doped regions 50 are formed in the substrate 100 between adjacent gate structures 102, respectively, and a plurality of doped regions 60 are formed in the substrate 100 between adjacent bit lines 202. Specifically, an ion implantation process is performed to form doped regions 50, 60 in the substrate 100 exposed by the openings 30, 40. The substrate 100 of the present embodiment has a first conductivity type; the doping region 50 and the doping region 60 have a second conductivity type. The first conductivity type is, for example, a P type; the second conductivity type is, for example, an N type, and vice versa. In this embodiment, the doping implanted in the doping region 50 is, for example, phosphorus or arsenic, and the doping concentration is, for example, 1×10 ¹⁵ /cm ³ to 1×10 ¹⁶ /cm ³ ; the doping of the doped region 60 is implanted. The substance is, for example, phosphorus or arsenic, and the doping concentration is, for example, 1 x 10 ¹⁵ /cm ³ to 1 × 10 ¹⁶ /cm ³ . In this embodiment, the doping region 50 is, for example, the source/drain region of the peripheral circuit region; the doping region 60 is, for example, the source/drain region of the memory cell array region. Referring to FIG. 2C, a Selective Epitaxial Growth (SEG) process is performed to form an epitaxial layer 124 in the opening 30 and a plurality of epitaxial layers 224 in the plurality of openings 40. In detail, since the selective epitaxial growth process is only performed on the surface of the exposed substrate 100, the epitaxial layer 124 is only located on the substrate 100 between the gate structures 102, and the epitaxial layer 224 is only in position. On the substrate 100 between the lines 202. The material of the epitaxial layer 124 and the epitaxial layer 224 of the present embodiment is, for example, single crystal germanium, germanium telluride or a combination thereof. The thickness of the epitaxial layer 124 may be between 5 nm and 50 nm; the thickness of the epitaxial layer 224 may be between 5 nm and 50 nm. The epitaxial layer 224 of the present embodiment can increase the height of the junction region between the doped region 60 (eg, the source/drain region) and the subsequent second contact plug 230 (as shown in FIG. 2D below), which can be reduced The resistance value between the second contact plug 230 and the doping region 60 is subsequently avoided, and the defect in the substrate 100 can be avoided to solve the problem of junction leakage of the source/drain region of the memory device. Similarly, epitaxial layer 124 can also reduce the resistance between subsequent first contact plugs 130 and doped regions 50 (eg, source/drain regions). Referring to FIG. 2C and FIG. 2D, a metal layer 126 is conformally formed in the opening 30, and a metal layer 226 is formed conformally in the opening 40. The metal layer 126 covers the surface of the epitaxial layer 124, and the metal layer 226 covers the epitaxial layer. The surface of 224. In this embodiment, the material of the metal layers 126, 226 may be, for example, titanium, cobalt, nickel, tungsten or a combination thereof, and may have a thickness of between 10 nm and 80 nm. Referring to FIGS. 2D and 2E, a tempering process is performed to form a metal telluride layer 128 on the substrate 100 between the gate structures 102, and simultaneously form a plurality of metal tellurides on the substrate 100 between the bit lines 202. Layer 228. In detail, the surface of the metal layer 126 in contact with the epitaxial layer 124 and the surface of the metal layer 226 in contact with the epitaxial layer 224 undergo a metal deuteration reaction, which causes the epitaxial layer 124 in the opening 30 to be transformed into a metal telluride layer 128, opening The epitaxial layer 224 in 40 is converted to a metal telluride layer 228. Since the epitaxial layers 124, 224 have sufficient thickness, they can react with the metal layer 126 above them to form the metal germanide layers 128, 228, respectively, thereby not only reducing the subsequent first contact plugs 130 and doped regions 50 (eg, source) The resistance value between the /pole region) and the resistance value between the subsequent second contact plug 230 and the doped region 60 (eg, the source/drain region), and loss of germanium in the substrate 100 can be avoided. In this way, the problem of leakage of the source/drain region of the memory element can be solved. Further, the unreacted metal layer 126a and the metal layer 226a remain on the sidewalls of the opening 30 and the opening 40, respectively. The metal layer 126a and the metal layer 226a of the present embodiment can be used as a barrier layer of the first contact plug 130 and the second contact plug 230. The material of the metal telluride layers 128, 228 is, for example, titanium telluride, cobalt telluride, nickel telluride or combinations thereof, and may have a thickness between 2 nm and 80 nm. Next, a first contact plug 130 is formed in the opening 30, and a plurality of second contact plugs 230 are formed in the plurality of openings 40. In detail, a conductive material layer (not shown) is formed on the substrate 100 of the first region R1 and the second region R2, and the conductive material layer is filled in the opening 30 and the opening 40, and the material thereof may include a metal, for example, tungsten. Titanium nitride, cobalt, nickel, aluminum or a combination thereof. Thereafter, the gate structure 102 is removed from the conductor material layer on the surface of the bit line 202 to form a first contact plug 130 in the opening 30, respectively, and a plurality of second contact plugs 230 are formed in the plurality of openings 40. . Since the first contact plug 130 and the second contact plug 230 can be formed at the same time in this embodiment, the embodiment can reduce the process steps, thereby reducing the process cost. In addition, the second contact plug 230 and the metal layer 226a in each opening 40 in this embodiment can be regarded as a storage node contact window, which can be used to electrically connect the doping region 60 with the subsequently formed capacitor 234. The metal telluride layer 128 is located between the doped region 50 and the first contact plug 130, such that the metal telluride layer 128 can reduce between the first contact plug 130 and the doped region 50 (eg, the source/drain region) The resistance value. Similarly, the metal telluride layer 228 is located between the doped region 60 and the second contact plug 230, so the metal telluride layer 228 can lower the second contact plug 230 and the doped region 60 (eg, source/drain regions) The resistance value between). The removal method described in this embodiment can utilize a chemical mechanical polishing method. Referring to FIG. 2F, a wire layer 132 is formed on the first contact plug 130 of the first region R1, so that the wire layer 132 can be separated from the gate structure 102 by the first contact plug 130 and the metal telluride layer 128. The doped regions 50 are electrically connected. The material of the wire layer 132 of this embodiment is, for example, tungsten, titanium nitride, cobalt, nickel, aluminum or a combination thereof, and the formation method thereof may be physical vapor deposition. Next, a protective layer 134 is formed conformally on the wire layer 132 to cover the surface of the dielectric layer 118a and the wire layer 132 of the first region R1, and covers the bit line 202 and the second contact plug of the second region R2. The surface of 230. The material of the protective layer 134 of this embodiment is, for example, hafnium oxide, tantalum nitride or a combination thereof, and the thickness thereof may be between 3 nm and 80 nm. Thereafter, a dielectric layer 136 is formed over the protective layer 134, such as the same dielectric layer 116. In addition, in this embodiment, a landing pad (not shown) is formed on the second contact plug 230 of the second region R2 to electrically connect the subsequently formed capacitor 234.

Referring to FIG. 2G, a plurality of capacitors 234 are formed on the second contact plugs 230 of the second region R2. Specifically, each capacitor 234 includes a lower electrode 234a, an upper electrode 234c, and a dielectric layer 234b. Each dielectric layer 234b is located between the lower electrode 234a and the upper electrode 234c. Each lower electrode 234a is electrically connected to the corresponding second contact plug 230. In an embodiment, the dielectric layer 234b may include a high dielectric constant material layer, such as an oxide of the following elements, such as: yttrium, zirconium, aluminum, titanium, tantalum, niobium, tantalum or niobium, or It is aluminum nitride or any combination of the above. The material of the lower electrode 234a and the upper electrode 234c is, for example, titanium nitride, tantalum nitride, tungsten, titanium tungsten, aluminum, copper or metal halide. Referring to FIG. 3A and FIG. 3B, the present invention provides another method of manufacturing a memory element, the steps of which are as follows. The structure and manufacturing process of FIG. 3A are the same as those of the structure and manufacturing process of FIG. 2A, and thus will not be described again. Thereafter, as shown in FIG. 3B, an etching process is performed with the patterned mask layer 122 as a mask to expose a portion of the surface of the substrate 100. Next, doped regions 50 are formed in the substrate 100 between adjacent gate structures 102, respectively, and a plurality of doped regions 60 are formed in the substrate 100 between adjacent bit lines 202. It is worth mentioning that the manufacturing process of FIG. 3B is substantially similar to that of FIG. 2B, but the difference is that after performing the etching process, the substrate 100 of the second region R2 of FIG. 3B further has a partial dielectric layer. 118a, wherein dielectric layer 118a covers bit line 202. Next, referring to FIG. 3C, a liner layer 324 is conformally formed on the substrate 100 of the first region R1 and the second region R2. The liner layer 324 covers the dielectric layer 118a of the first region R1 and the surface of the opening 30, and covers the dielectric layer 118a of the second region R2 and the surface of the opening 40. The material of the liner layer 324 in this embodiment is, for example, polycrystalline germanium, amorphous germanium or a combination thereof, and the thickness thereof may be between 2 nm and 15 nm.

Referring to FIG. 3C and FIG. 3D, a metal layer (not shown) is formed conformally on the liner layer 324. The material of the metal layer in this embodiment is, for example, titanium, cobalt, nickel, tungsten or a combination thereof, and the thickness thereof may be between 10 nm and 80 nm. Thereafter, a tempering process is performed to cause the liner layer 324 to be converted into a metal telluride layer 328. In detail, the surface of the metal layer (not shown) that is in contact with the liner layer 324 undergoes a metal deuteration reaction that causes the liner layer 324 to be converted into a metal telluride layer 328. The material of the metal telluride layer 328 of the present embodiment is, for example, titanium telluride, cobalt telluride, nickel telluride or a combination thereof, and the thickness thereof may be between 2 nm and 80 nm. As with the above embodiment, since the liner layer 324 has a sufficient thickness, it can react with the metal layer above it to form the metal telluride layer 328, so that it can not only lower the subsequent first contact plug 130 and the doping region 50 (eg, source) The resistance value between the /pole region) and the resistance value between the subsequent second contact plug 230 and the doped region 60 (eg, the source/drain region), and loss of germanium in the substrate 100 can be avoided. This solves the problem of junction leakage of the source/drain regions of the memory device. Next, a conductor layer 330 is formed on the metal telluride layer 328. Conductor layer 330 fills opening 30 and opening 40 and overlying metal halide layer 328. The material of the conductor layer 330 of this embodiment is, for example, titanium nitride, cobalt, nickel, aluminum or a combination thereof, and the thickness thereof may be between 10 nm and 80 nm.

Referring to FIGS. 3D and 3E, the patterned conductor layer 330 and the metallization layer 328 are formed to form a plurality of first contact plugs 130 between the gate structures 102, and at the same time form a plurality of first lines between the bit lines 202. Two contact plugs 230. In detail, a wire layer 132 is also formed at the same time as the first contact plug 130 is formed. The wire layer 132 is located on the first contact plug 130, which can be formed by the first contact plug 130 and the metal telluride layer 328a. The doped region 50 between the gate structure 102 is electrically connected. The metal telluride layer 328a is located between the first contact plug 130 and the doped region 50 to reduce the resistance between the first contact plug 130 and the doped region 50. Similarly, a conductor pad 232 is formed at the same time as the second contact plug 230 is formed. The conductor pad 232 is located on the first contact plug 130, which can be connected to the bit by the second contact plug 230, the metal telluride layer 328b. The doped regions 60 between the lines 202 are electrically connected. The conductor pad 232 of this embodiment can be regarded as a landing pad. The metal telluride layer 328b is located between the second contact plug 230 and the doped region 60 to reduce the resistance between the second contact plug 230 and the doped region 60. In addition, during the patterning process, a portion of the dielectric layer 118a is also removed to form a dielectric layer 118b on the gate structure 102 of the first region R1, and formed on the bit line 202 of the second region R2. Dielectric layer 118c. A portion of the metal telluride layer 328a is between the dielectric layer 118b and the wire layer 132; and a portion of the metal halide layer 328b is also between the dielectric layer 118c and the conductor pad 232.

Referring to FIGS. 3E and 3F, a plurality of capacitors 234 are formed on the second contact plug 230 of the second region R2. Specifically, a dielectric layer 136 is formed on the substrate 100. The dielectric layer 136 covers the surface of the dielectric layer 118b and the wiring layer 132 of the first region R1, and fills the opening 70 of the second region R2, and covers the dielectric layer 118c of the second region R2 and the surface of the conductor pad 232. . Thereafter, a capacitor 234 is formed in the dielectric layer 136 of the second region R2. Each capacitor 234 is electrically connected to a corresponding conductor pad 232.

In summary, an embodiment of the present invention utilizes a selective epitaxial growth process to form a plurality of epitaxial layers on a doped region between gate structures and a doped region between bit lines. In another aspect, another embodiment of the invention is to form a liner on a substrate Cover the doped area. The epitaxial layer and the underlayer may be used to participate in the metal deuteration reaction to form a metal telluride layer during the subsequent tempering process. Thus, the present invention can not only reduce the resistance between the storage node contact window and the source/drain region of the memory cell array region, but also avoid the loss of germanium in the germanium substrate and solve the source/drain region of the memory device. The problem of leakage at the junction. In addition, the present invention can simultaneously form contact plugs on the first zone and the second zone, which can reduce the process steps and reduce the process cost.

50, 60‧‧‧ doped area

100‧‧‧Base

101‧‧‧Isolation structure

102‧‧‧ gate structure

104, 204‧‧‧ gate dielectric layer

106, 110, 206, 210‧‧‧ conductor layers

108, 208‧‧‧ barrier layer

112, 212‧‧‧ top cover

114, 214‧‧ ‧ spacer

116, 118a, 136a‧‧‧ dielectric layer

126a, 226a‧‧‧ metal layer

128, 228‧‧‧metal telluride layer

130‧‧‧First contact plug

132‧‧‧Wire layer

134a‧‧ ‧ protective layer

202‧‧‧ bit line

230‧‧‧second contact plug

234‧‧‧ capacitor

234a‧‧‧ lower electrode

234b‧‧‧ dielectric layer

234c‧‧‧Upper electrode

R1‧‧‧ first district

R2‧‧‧Second District

Claims (9)

A memory element comprising: a plurality of word line groups, located in a substrate, each word line group having two buried word lines; a plurality of bit lines on the substrate and traversing the lines a word line group; a plurality of capacitors on the substrate between the bit lines and on the substrate on both sides of the word line groups; and a plurality of contact plugs located in the capacitors Between the substrates, the materials of the contact plugs comprise a metal. The memory element of claim 1, further comprising a plurality of metal telluride layers between the contact plugs and the substrate. The memory component of claim 1, further comprising a plurality of landing pads located between the contact plugs and the capacitors. The memory component of claim 1, further comprising a plurality of active regions, the long side of each active region traversing the corresponding character line group, and each active region and the corresponding bit line The overlap has a one-line contact window. A method of fabricating a memory device, comprising: providing a substrate having a first region and a second region; forming a plurality of gate structures on the substrate of the first region; and the substrate in the second region Forming a plurality of bit lines thereon; performing a selective epitaxial growth process to form a plurality of epitaxial layers on the substrate between the gate structures and the substrate between the bit lines; Forming a metal layer on the substrate to cover the epitaxial layers; performing a tempering process to form a plurality of regions on the substrate between the gate structures and between the bit lines a metal telluride layer; forming a plurality of first contact plugs on the metal telluride layers between the gate structures and simultaneously forming on the metal germanide layers between the bit lines a plurality of second contact plugs; and forming a plurality of capacitors on the second contact plugs of the second region. A method of fabricating a memory device, comprising: providing a substrate having a first region and a second region; forming a plurality of gate structures on the substrate of the first region; and the substrate in the second region Forming a plurality of bit lines thereon; forming a liner on the substrate of the first region and the second region; forming a metal layer on the substrate to cover the liner; performing a tempering process, Transforming the liner into a metal telluride layer; forming a conductor layer on the metal telluride layer; patterning the conductor layer and the metal telluride layer to form a plurality of first contacts between the gate structures a plug, and simultaneously forming a plurality of second contact plugs between the bit lines; and forming a plurality of capacitors on the second contact plugs of the second area. The method of manufacturing the memory device of claim 5, further comprising forming a plurality of landing pads between the second contact plugs and the capacitors. A method of manufacturing a memory element according to claim 5 or 6, wherein The first area is a peripheral circuit area, and the second area is a memory cell array area. A memory element comprising: a plurality of word lines in a substrate; a plurality of bit lines on the substrate and traversing the word lines; a plurality of capacitors located between the bit lines On the substrate, on the substrate on both sides of the word lines; a plurality of contact plugs between the capacitors and the substrate, wherein the materials of the contact plugs comprise a metal; A metal telluride layer is located between the contact plugs and the substrate.