TW201635260A - Shift register circuit - Google Patents

Abstract

A shift register, having a plurality of shift register circuit. Every stage of shift register circuit has a first transistor, a second transistor, a third transistor, and a fourth transistor. a first end of the first transistor for receiving input signal, a second end of the first transistor electrically connected to a node, a gate end of the first transistor for receiving a first clock signal. a gate end of the second transistor electrically connected to a node, a first end of the second transistor for receiving a second clock signal, a second end of the first transistor for outputting an output signal. a first end of the third transistor electrically connected to the node, a gate end of the third transistor for receiving a start pulse. a first end of the fourth transistor electrically connected to the second end of the second transistor, a gate end of the fourth transistor for receiving a fourth clock signal. A capacitance electrically connected between the gate end and the second end of the second transistor, the start pulse is a synchronization signal of a frame time, an initial enable time of the clock signals are late to the start pulse, and the second clock signal has inverted phase with the fourth clock signal.

Description

Shift register circuit

The invention relates to a shift temporary storage circuit, in particular to a shift temporary storage circuit with less layout area and signal routing.

The display panel includes a plurality of pixels, a gate driving circuit, and a source driving circuit. The gate drive circuit includes a plurality of shift register registers for providing a plurality of gate drive signals to control the turning on and off of the pixels. The source driver circuit is used to write the data signal to the pixel that is turned on. In addition, current display panels often use gate driver on array (GOA) to provide the gate drive signals required for pixels. Different from the conventional gate driver, the circuit using GOA can reduce the production cost of the panel because the process can be incorporated into the process of the TFT array of the display panel.

However, in the currently known shift register circuit, a DC voltage source is used as a reference voltage to maintain the signal at a certain level, so that the layout area cannot be reduced. In addition, when the transistor continues to be actuated by the DC voltage source, a threshold voltage offset is generated, causing the shift register circuit to malfunction.

Therefore, how to reduce the layout area and avoid shifting the temporary circuit malfunction is a goal of continuous efforts by those skilled in the art.

According to an embodiment of the invention, a shift register includes a multi-stage shift register circuit, each shift register circuit includes: a first transistor having a first end, a second end, and a gate terminal The first end of the first transistor is configured to receive an input signal, the first transistor is electrically connected to the node, the gate end of the first transistor is configured to receive the first clock signal, and the second transistor has a first end a second end, and a gate terminal, wherein the gate of the second transistor is electrically connected to the second end of the first transistor, and the second end of the second transistor is used for outputting an output signal, and the first end of the second transistor The third transistor has a first end, a second end, and a gate terminal, wherein the first end of the third transistor is electrically connected to the second end of the first transistor, and the third The gate of the transistor is configured to receive a start signal; the fourth transistor has a first end, a second end, and a gate terminal, wherein the first end of the fourth transistor is electrically connected to the second end of the second transistor, The gate of the fourth transistor is used to receive the fourth clock signal; and the capacitor, the coupling Between the node and the second end of the second transistor, wherein the start signal is a synchronization signal during the startup screen, the initial activation time of the clock signal is later than the start signal, the fourth clock signal and the second signal The clock signals are mutually inverted and the initial phase of the fourth clock signal is delayed by 180 degrees from the second clock signal, and the initial phase of the first clock signal is delayed by 270 degrees from the second clock signal.

According to another embodiment of the present invention, a shift register circuit includes a pull-up unit electrically connected to a node, and the pull-up unit is turned on according to the first clock signal and the node voltage is pulled up; the charging unit is electrically connected to the node. The output unit is electrically connected to the node, and the output unit is electrically connected to the node, and includes a second input end for receiving the second clock signal, and outputting the signal to the output end according to the node voltage; and a voltage stabilizing unit electrically connecting the output end, including the fourth input The terminal is configured to receive the fourth clock signal, wherein the start signal is a synchronization signal during the startup screen, the initial activation time of the clock signal is later than the start signal, and the fourth clock signal and the second clock signal are mutually Inverted and the initial of the fourth clock signal The phase is delayed by 180 degrees from the second clock signal, and the initial phase of the first clock signal is delayed by 270 degrees from the second clock signal.

In summary, through the embodiments of the technical solution of the present invention, the shift register circuit is driven by the clock signals CK1, CK2, CK3, and CK4 to reduce the effect of the signal trace to reduce the layout area. It can increase the aperture ratio of the display or reduce the area of the peripheral area. In addition, it can suppress the bias effect caused by the transistor being continuously coupled to the DC voltage source.

100, 200, 300‧‧‧ shift register circuit

110‧‧‧Upper pull unit

120‧‧‧Output unit

130, 230, 330‧‧‧Charging unit

140, 240‧‧‧ voltage regulator unit

M1, M2, M3, M4‧‧‧ transistors

C‧‧‧ capacitor

IN1, IN2, IN3, IN4‧‧‧ inputs

OUT‧‧‧ output

ING‧‧‧ signal end

VST‧‧‧Charging end

CK1, CK2, CK3, CK4‧‧‧ clock signal

G _N , G _N-1 ‧‧‧ output signal

Q _N ‧‧‧ nodes

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 2 is a circuit diagram of a shift register circuit according to an embodiment of the invention; FIG. 3 is a circuit diagram of a shift register circuit according to another embodiment of the present invention; and FIG. 4 is a diagram according to another embodiment of the present invention; An embodiment of the present invention is a driving waveform diagram of a shift temporary storage circuit;

The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the invention, and the description of structural operations is not intended to limit the order of execution thereof The structure, the device having the equal effect, is the invention The scope of the cover. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. For ease of understanding, the same elements in the following description will be denoted by the same reference numerals.

The terms "first", "second", etc., used herein are not intended to refer to the order or order, nor are they intended to limit the invention, only to distinguish between elements or operations described in the same technical terms. Only.

Please refer to FIG. 1. FIG. 1 is a circuit diagram of a shift register circuit 100 according to an embodiment of the present invention. The shift register circuit 100 includes a pull-up unit 110, an output unit 120, a charging unit 130 and a voltage stabilizing unit 140, a charging terminal VST, a signal terminal ING, an input terminal IN1, an input terminal IN2, an input terminal IN4, and an output terminal OUT. The charging terminal VST is used for receiving the start signal; the input terminal IN1, the input terminal IN2 and the input terminal IN4 respectively receive different clock signals CK1, CK2 and CK4, and the signal terminal ING is used for receiving the output of the pre-stage shift register circuit. The output signal G _N-1 output by the terminal.

The pull-up circuit 110 is coupled to the signal terminal ING, the node Q _N and the input terminal IN1. The input terminal IN1 is configured to receive the clock signal CK1 and control the power between the signal terminal ING and the node Q _N according to the potential of the clock signal CK1. Sexual connection.

The output unit 120 is coupled to the input terminal IN2, the node Q _N and the output terminal OUT. The input terminal IN2 is configured to receive the clock signal CK2 and control the electrical connection between the input terminal IN2 and the output terminal OUT according to the potential of the node Q _N . connection.

The charging unit 130 is coupled to the node Q _N and the charging terminal VST for controlling the voltage level of the node Q _N according to the potential of the charging terminal VST.

The voltage stabilizing unit 140 is coupled to the output terminal OUT and the input terminal IN4, and the input terminal IN4 is configured to receive the clock signal CK4 and is used for controlling the lightning pressure of the output terminal OUT according to the clock signal CK4. Level.

In one embodiment, the charging unit 130 and the voltage stabilizing unit 140 can be coupled to a voltage source VGL, such that the charging unit 130 can charge and discharge the node Q _N according to the potential of the charging terminal VST. The voltage stabilizing unit 140 can delay the potential of the output terminal OUT at a low voltage level according to the potential of the input terminal IN4 to prevent the potential of the output terminal OUT from floating.

Please refer to FIG. 2, which is another embodiment of the present invention. Another embodiment shown in FIG. 2 is a shift register unit 200. The structures are substantially similar and labeled with the same reference numerals. It should be noted that the charging unit 230 may include an input terminal IN3 for receiving the clock signal CK3. Since the start signal of the charging terminal VST and the enabling period of the clock signal CK3 do not overlap each other, the coupling may also be adopted. The way of the clock signal CK3 is to charge the node Q _N . Compared with the shift register circuit 100, the shift register circuit 200 can save traces to achieve the effect of reducing the layout area.

Referring to FIG. 2, the voltage stabilizing unit 240 of the shift register unit 200 can electrically connect the clock signal CK2 and maintain the potential of the output terminal OUT at a low voltage level according to the clock signal CK4 received by the input terminal IN4. The clock signal CK2 is inverted in the clock signal CK4, so when the voltage regulator unit is turned on, the potential of the output terminal OUT can be pulled down to a low voltage level to avoid the potential level floating of the output terminal OUT (floating ).

In addition, the pull-up unit 110, the output unit 120, the charging unit 130, and the voltage stabilizing unit 140 in the shift register unit 100 and the charging unit 230 and the voltage stabilizing unit 240 in the shift register unit 200 can also use switches or electricity. For the implementation of the crystal, the present specification is only an example of an N-type transistor. However, the present invention is not limited thereto, and the shift register circuit can also be implemented using a P-type transistor.

The pull-up unit 110 includes a transistor M1, the output unit 120 includes a transistor M2, the charging unit 130 includes a transistor M3, and the voltage stabilizing unit 140 includes a transistor M4, each of which has a first end, a second end, and The gate is extreme. When the gate terminal of transistor M1 is electrically connected to the input terminal IN1, for receiving; end of a first transistor M1 is electrically connected to the signal terminal ING, for receiving from the preceding-stage shift register cell output signal G _N-1 The pulse signal CK1, the second end of the transistor M1 is electrically connected to the node Q _N . The first end of the transistor M2 is electrically connected to the input terminal IN2 for receiving the clock signal CK2, the gate terminal of the transistor M2 is electrically connected to the node Q _N , and the second end of the transistor M2 is electrically connected to the output terminal OUT. To output the output signal G _N . The first end of the transistor M3 is electrically connected to the node Q _N , the gate terminal of the transistor M3 is electrically connected to the charging terminal VST for receiving the start signal, and the second end of the transistor M3 is electrically connected to the low voltage source VGL. The first end of the transistor M4 is electrically connected to the output terminal OUT, the gate terminal of the transistor M4 is electrically connected to the input terminal IN4 for receiving the clock signal CK4, and the second end of the transistor M4 is electrically connected to the low voltage source VGL. In an embodiment, the output unit 120 may further include a capacitor C electrically connected between the gate terminal and the second terminal of the transistor M2. The capacitor is coupled between the transistors by using a capacitor, and the voltage of the node Q _N can be stored in the capacitor. Capacitor, when the output signal G _{N of the} output terminal OUT must be maintained at a high voltage level, it will not leak too fast, and it can store the charge.

In another embodiment, the charging unit 230 includes a transistor M3 and the voltage stabilizing unit 240 includes a transistor M4, and the second end of the transistor M3 is electrically connected to the clock signal CK3 because the transistor M3 is turned on. In the state, the voltage of the node Q _N can be pulled down by the clock signal CK3 at the low voltage level. The second end of the transistor M4 is electrically connected to the clock signal CK2. When the transistor M4 is turned on, the voltage of the output signal G _N of the output terminal OUT can be maintained by the clock signal CK2 at the low voltage level. The level does not cause the output signal G _{N to} float.

Please refer to FIG. 3, which is a circuit diagram of the shift register circuit 300. The structures are substantially similar and labeled with the same reference numerals, and will not be further described. It is worth mentioning that the second end of the transistor M3 of the charging unit 330 is not mentioned. Is connected to the gate terminal of the transistor M3, because the clock signal has not been enabled at the beginning of the picture period, at this time, the transistor M3 in the shift register unit 300 of the first or second stage It can be connected by a diode connection to achieve the function of charging the node Q _N .

In order to clearly illustrate the features and advantages of the shift register of the present invention, please refer to FIG. 4 for the circuit diagram of the shift register circuit, and FIG. 4 is the signal of the shift register circuits 100, 200 and 300. Waveform diagram. The initial signal is the synchronization signal Vsync of each frame period, and the initial activation time of the clock signal CK1, the clock signal CK2, the clock signal CK3, and the clock signal CK4 is later than the start signal. The clock signal CK4 and the clock signal CK2 are mutually inverted, and the initial phase of the clock signal CK4 is delayed by 180 degrees from the clock signal CK2, and the clock signal CK1 and the clock signal CK3 are mutually inverted and the clock signal CK1 is The initial phase is delayed by 180 degrees from the clock signal CK3, and the initial phase of the clock signal CK1 is delayed by 270 degrees from the clock signal CK2. The initial phase refers to the phase time at which the clock signal is first enabled at the beginning of the picture period.

Taking the shift register circuit 300 of the first stage as an example, in the time interval T1, the transistor M3 receives the start signal from the charging terminal VST to be turned on, and the remaining transistors M1, M2, and M4 are in the off state at this time. crystal M3 starts charging node Q _N; in the time interval T2, transistors M3 continued charging node Q _N, Q _N nodes located at the first end for receiving a high voltage level and the transistor M2 is such that the clock signal CK2 transistor M2 Turning on and outputting the output signal G _N , the transistors M1 and M4 are in the off state; in the time interval T3, the transistors M1, M3, and M4 are in the off state, and the transistor M2 is continuously turned on and outputting the output signal G _N in the time interval. In T4, the clock signal CK2 is disabled and the clock signal CK4 is enabled to turn on the transistor M4, and the remaining transistors M1, M2, and M3 are in an off state. At this time, the function of the transistor M4 is to maintain the voltage of the output signal G _N . Located at a low voltage level to avoid signal floating.

Taking the shift register circuit 200 of the Nth stage as an example, in the time interval T1, the transistor M1 receives the G _N-1 signal from the signal terminal ING of the previous stage to be turned on, and the remaining transistors M2, M3, and M4 are at this time. In the off state, the transistor M1 starts to charge the node Q _N ; in the time interval T2, the transistor M1 continues to charge the node Q _N , the node Q _N is at the high voltage level and the first end of the transistor M2 receives the clock signal CK2 turns on the transistor M2 and outputs the output signal G _N , and the transistor M4 is in the off state; in the time interval T3 , the transistors M1 , M3 , M4 are in the off state , the transistor M2 is continuously turned on and outputs the output signal G _N ; During the time interval T4, the clock signal CK2 is disabled and the clock signal CK4 is enabled to turn on the transistor M4, and the remaining transistors M1, M2, and M3 are in an off state. At this time, the function of the transistor M4 is to maintain the output signal G. The voltage of _N is at a low voltage level to avoid signal floating.

In summary, the shift temporary storage circuit of the embodiment of the present invention drives the shift temporary storage circuit through the clock signals CK1, CK2, CK3, and CK4 to reduce the effect of the signal trace to reduce the layout area. It can increase the aperture ratio of the display or reduce the area of the peripheral area, and can also suppress the threshold voltage offset caused by the continuous coupling of the transistor to the DC voltage source.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100‧‧‧Shift register circuit

110‧‧‧Upper pull unit

120‧‧‧Output unit

130‧‧‧Charging unit

140‧‧‧Stabilizer

M1, M2, M3, M4‧‧‧ transistors

C‧‧‧ capacitor

IN1, IN2, IN4‧‧‧ input

OUT‧‧‧ output

ING‧‧‧ signal end

VST‧‧‧Charging end

CK1, CK2, CK4‧‧‧ clock signal

G _N , G _N-1 ‧‧‧ output signal

VGL‧‧‧ voltage source

Q _N ‧‧‧ nodes

Claims (11)

a shift register, comprising a multi-stage shift register circuit, wherein each of the shift register circuits comprises: a first transistor having a first end, a second end, and a gate terminal, The first end of the first transistor is configured to receive an input signal, the first transistor is electrically connected to a node, and the gate end of the first transistor is configured to receive a first clock signal; a second transistor having a first end, a second end, and a gate terminal, wherein the gate terminal of the second transistor is electrically connected to the second end of the first transistor, and the second transistor The second end is configured to output an output signal, the first end of the second transistor is configured to receive a second clock signal, and the third transistor has a first end, a second end, and a gate Extremely, wherein the first end of the third transistor is electrically connected to the second end of the first transistor, the gate end of the third transistor is configured to receive a start signal; and a fourth transistor has a first end, a second end, and a gate terminal, wherein the first end of the fourth transistor is electrically connected to the first The second end of the transistor, the gate of the fourth transistor is configured to receive a fourth clock signal; and a capacitor is coupled between the node and the second end of the second transistor, The start signal is a synchronization signal during a screen, and the initial activation time of the clock signals is later than the start signal, and the fourth clock signal and the second clock signal are mutually Inverted and the initial phase of the fourth clock signal is delayed by 180 degrees from the second clock signal, and the initial phase of the first clock signal is delayed by 270 degrees from the second clock signal. The shift register of claim 1 further comprising: the second end of the third transistor and the second end of the fourth transistor being electrically coupled to a voltage source. The shift register of claim 1 , further comprising: the second end of the third transistor is configured to receive a third clock signal, the third clock signal and the first clock signal are mutually Inverted, and the initial phase of the first clock signal is delayed by 180 degrees from the third clock signal. The shift register of claim 1 further comprising: the second end of the third transistor being electrically coupled to the gate terminal of the third transistor. The shift register of claim 1 further comprising: the second end of the fourth transistor being electrically coupled to the second clock signal. The shift register according to claim 1, wherein in a first period, the third transistor is turned on, and the node voltage is pulled up; and in a second period, the second transistor is turned on, To output the output signal; During a third period, the third transistor is turned off to pull down the node voltage; and in a fourth period, the fourth transistor is turned on to pull down the output signal and stabilize the potential of the output signal. The shift register according to claim 1, wherein in a first period, the first transistor is turned on, and the node voltage is pulled up; and in a second period, the second transistor is turned on, Outputting the output signal; during a third period, the first transistor is turned off to pull down the node voltage; and during a fourth period, the fourth transistor is turned on to pull down the output signal and stabilize The potential of the output signal. a shifting temporary storage circuit includes: a pull-up unit electrically connected to a node, comprising a first input end and a signal end, wherein the pull-up unit is turned on according to a first clock signal and the node voltage is pulled up; a charging unit electrically connected to the node for receiving a start signal; an output unit electrically connected to the node, including a second input end for receiving a second clock signal, and outputting an output signal according to the node voltage And a voltage stabilizing unit electrically connected to the output end, comprising a fourth input end for receiving a fourth clock signal, wherein the start signal is a synchronization signal during a start of a picture, Time The initial activation time of the pulse signal is later than the start signal, the fourth clock signal and the second clock signal are mutually inverted, and the initial phase of the fourth clock signal is delayed from the second clock signal. At 180 degrees, the initial phase of the first clock signal is delayed by 270 degrees from the second clock signal. The shift register circuit of claim 8 , wherein the charging unit further comprises a third input terminal for receiving a third clock signal, wherein the third clock signal and the first clock signal are mutually Inverted, and the initial phase of the first clock signal is delayed by 180 degrees from the third clock signal. The shift register according to claim 8, wherein the voltage stabilizing unit is electrically connected to the second clock signal for stabilizing the potential of the output terminal when the voltage stabilizing unit is turned on. The shift register circuit of claim 8, wherein the charging unit and the voltage stabilizing unit are electrically connected to a voltage source.