TW201628010A - Anti-fuse memory and semiconductor storage device - Google Patents

Abstract

Provided is anti-fuse memory in which destructive memory voltage that causes the breakdown of a memory gate insulating film (8) becomes reverse bias voltage between a memory gate electrode (NG) and a switch gate electrode (PG), thus making it possible to make the film thickness of a switch gate insulating film (7) thinner without being constrained by the destructive memory voltage and to achieve correspondingly high-speed operation of on/off operation in a channel region at the switch gate electrode (PG) during data reading. In addition, as a result of it being possible to form the memory gate insulating film (8) and the switch gate insulating film (7) in a similar manner so as to be unlikely to break during data reading without the need to perform special processing on the anti-fuse memory (2a) such as the ion implantation of impurities into a memory gate insulating film in order to facilitate the breakage thereof as in the prior art, it is possible to decrease the likelihood that the memory gate insulating film (8) will suffer from breakdown even if, for example, reading selection memory voltage is repeatedly applied to the memory gate electrode (NG), and to thereby increase the reliability with respect to read information during data reading.

Description

Anti-fuse memory and semiconductor memory device

The present invention relates to anti-fuse memory and semiconductor memory devices.

In the past, an anti-fuse memory as shown in the specification of Patent No. 7,402,855 (Patent Document 1) is known as an anti-fuse memory which can be used to write data only once by damaging the insulating film. The anti-fuse memory of the patent document 1 is described in detail in the "Background Art" of the patent application No. 2014-015352, for example, a component separation layer and impurity diffusion are formed at a specific interval on the surface of the well. A gate electrode is formed on the well between the element isolation layer and the impurity diffusion region by interposing the switch gate insulating film and the memory gate insulating film. Further, in the anti-fuse memory, a step portion is formed on the gate electrode, and the thickness of the switch gate insulating film is formed to be thicker than the thickness of the memory gate insulating film.

Thereby, in the anti-fuse memory, when the data is written, the film thickness is thinner by the voltage difference between the breakdown word voltage applied to the impurity diffusion region and the breakdown bit voltage applied to the gate electrode. One of the memory gate insulating films is broken by insulation and is in a state in which data is written, but the insulating state of the switching gate insulating film of the other of the thick film thickness can be maintained. Moreover, the anti-fuse memory system determines the electrical connection between the gate electrode of the memory gate insulating film and the well of the thin film thickness based on the voltage change of the bit line connected to the impurity diffusion region during data reading. The status can be judged whether or not the data is written.

Further, as another anti-fuse memory, an anti-fuse memory such as the specification of Patent Document No. 6,940,751 (Patent Document 2) can be also considered (see FIGURE 27 of Patent Document 2). Here, the anti-fuse memory system shown in FIG. 27 of Patent Document 2 is formed in such a manner that the switching gate insulating film and the memory gate insulating film formed between the gate electrode and the well are formed in the same manner. The film thickness is thick, but in the manufacturing process, one of the memory gate insulating films is ion-implanted with impurities, so that the memory gate insulating film is more easily destroyed by the insulation than the switch gate insulating film, that is, by ion implantation. The lifetime of the gate insulating film which can be maintained without any treatment is deteriorated, and the memory gate insulating film is actively destroyed.

Therefore, in the anti-fuse memory, when the data is written, the memory gate insulating film of one of the ion-implanted impurities is broken by the insulation and becomes a state in which the data is written, but the ion implantation can be maintained. The insulation state of the switch gate insulating film of the other of the impurities.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] US Patent No. 7,402,855

[Patent Document 2] US Patent No. 6,940,751

However, in the anti-fuse memory of Patent Document 1 of the former, in order to write data, even if the word voltage is broken and a voltage difference is generated from the broken bit voltage, the switching gate insulating film is not damaged by the insulation. The film thickness of the switch gate insulating film must be sufficiently thick. Therefore, as the film thickness of the switch gate insulating film increases, there is a high-speed action that makes it difficult to realize the on/off operation of data reading. The problem.

In this regard, in the anti-fuse of Patent Document 2 of the latter, since the film thickness of the switching gate insulating film and the film thickness of the memory gate insulating film are formed to have the same film thickness, it is different from Patent Document 1 described above. The anti-fuse can realize the high-speed operation of the on/off operation when reading data.

However, in the anti-fuse of Patent Document 2, the memory gate insulating film is easily broken. Bad, if the read gate voltage is repeatedly applied to the gate electrode for reading data, there is also a burden on the memory gate insulating film, which eventually causes the memory gate insulating film to be read during data reading. The breakdown of insulation. Therefore, in the anti-fuse of Patent Document 2, although the memory gate insulating film is not destroyed at the time of data writing, the memory gate insulating film is destroyed during data reading, so there is data. The reliability of reading data during reading is reduced.

Therefore, the present invention has been made in view of the above points, and an object thereof is to provide an anti-fuse memory and a semiconductor memory device which can improve the reliability of reading information and realize high-speed operation.

In order to solve the above problems, the anti-fuse memory of the present invention is characterized by comprising: a well having an impurity diffusion region to which a bit line is connected; a memory gate insulating film formed on the well; a memory type memory gate electrode formed on the memory gate insulating film and applying a damaged memory voltage for insulating and destroying the memory gate insulating film; a switch gate insulating film formed on the impurity a well between the diffusion region and the memory gate insulating film, and integrally formed with the memory gate insulating film; and a switching gate electrode which is opposite to the memory gate electrode Forming a second conductivity type on the switching gate insulating film and bonding to the memory gate electrode; and applying the damaged memory voltage to the memory gate electrode to the memory gate electrode and The voltage between the switching gate electrodes becomes a reverse bias voltage.

Furthermore, the semiconductor memory device of the present invention is characterized in that an anti-fuse memory is disposed at each of the intersections of the plurality of bit lines with respect to the plurality of switching word lines and the plurality of memory word lines; Anti-fuse memory system The above anti-fuse memory.

According to the present invention, by destroying the memory of the memory gate insulating film The body voltage becomes a reverse bias voltage between the gate electrode of the memory and the gate electrode of the switch, and the film thickness of the switch gate insulating film can be reduced without being limited by destroying the voltage of the memory. Therefore, data reading can be realized. The high-speed action of the on/off operation of the channel region in the gate electrode of the switch is taken.

Further, in the anti-fuse memory and the semiconductor memory device, it is possible to perform the special processing such as easy destruction of the memory gate insulating film by ion implantation as in the prior art, and the same as the switching gate insulating film. The memory gate insulating film is formed by the film which is not easily broken when the data is read. Therefore, even if the read memory voltage is repeatedly applied to the memory gate electrode, the memory gate insulating film is not easily Insulation damage, which improves the reliability of reading information when reading data.

1‧‧‧Semiconductor memory device

2a‧‧‧Anti-fuse memory

2b‧‧‧Anti-fuse memory

2c‧‧‧Anti-fuse memory

2d‧‧‧Anti-fuse memory

2N‧‧‧Write to non-selective memory

2R‧‧‧Read selection memory

2NR‧‧‧Read non-selective memory

2W‧‧‧Write selection memory

4‧‧‧ Component separation layer

5‧‧‧ impurity diffusion area

7‧‧‧Switch gate insulating film

8‧‧‧Memory gate insulating film

9‧‧‧ side wall

21‧‧‧Semiconductor memory device

22‧‧‧Anti-fuse memory

BL1‧‧‧ bit line

BL2‧‧‧ bit line

C1‧‧‧Depletion layer capacitance

C2‧‧‧ gate insulating film capacitor

CH‧‧‧ channel layer

CN‧‧‧Substrate voltage

CV‧‧‧ substrate voltage

D‧‧‧depletion layer

DW‧‧‧Semiconductor substrate

M‧‧‧ memory capacitor

M1‧‧‧ memory capacitor

MG‧‧‧gate electrode

MG1‧‧‧ gate electrode

MV‧‧‧ memory voltage

NG‧‧‧ memory gate electrode

NG1‧‧‧ memory gate electrode

NWL1‧‧‧ memory word line

NWL2‧‧‧ memory word line

PG‧‧‧Switch Gate Electrode

PWL1‧‧‧ switch word line

PWL2‧‧‧ switch word line

S‧‧‧Switching transistor

S1‧‧‧Switching transistor

V‧‧‧ channel potential

W‧‧‧ Well

Fig. 1 is a schematic view showing the circuit configuration of a semiconductor memory device including the anti-fuse memory of the present invention and voltages at respective portions during a data writing operation.

Fig. 2 is a schematic view showing a cross-sectional structure of an anti-fuse memory of the present invention.

Fig. 3 is a schematic view showing voltages of respective parts at the time of data reading operation.

4 is a schematic view showing voltages of respective portions in a circuit configuration and a data writing operation of the semiconductor memory device according to another embodiment.

Fig. 5 is a schematic view showing the explanation for preventing dielectric breakdown in the anti-fuse memory shown in Fig. 4.

Fig. 6 is a schematic view showing a cross-sectional structure of an anti-fuse memory according to another embodiment.

Hereinafter, embodiments for carrying out the invention will be described. In addition, the description is set to the order shown below.

1. Composition of semiconductor memory device and anti-fuse memory

2. Data writing action

3. Data reading action

4. Function and effect

5. Other embodiments

5-1. Semiconductor memory device of other embodiments

5-2. Detailed composition of anti-fuse memory of other embodiments

5-3. Others

(1) Composition of semiconductor memory device and anti-fuse memory

In Fig. 1, reference numeral 1 denotes a semiconductor memory device having a configuration in which the anti-fuse memory devices 2a, 2b, 2c, and 2d of the present invention are arranged in a matrix, for example, a plurality of switching word lines PWL1, PWL2, and The pair of memory word lines NWL1 and NWL2 in the pair of switching word lines PWL1 and PWL2 are arranged in one direction (in the column direction in FIG. 1). Further, the semiconductor memory device 1 is provided with a plurality of bit lines BL1 and BL2 so as to be orthogonal to the switching word lines PWL1 and PWL2 and the memory word lines NWL1 and NWL2. The semiconductor memory device 1 is provided with anti-fuse memories 2a, 2b, 2c, and 2d at intersections of the switching word lines PWL1 and PWL2 and the memory word lines NWL1 and NWL2 and the bit lines BL1 and BL2. The anti-fuse memory 2a, 2b, 2c, 2d are connected to the switching word lines PWL1, PWL2, the memory word lines NWL1, NWL2, and the bit lines BL1, BL2.

In this case, the semiconductor memory device 1 can uniformly apply a plurality of anti-fuse memories 2a, 2c (2b, 2d) disposed along the bit line BL1 (BL2) from the bit line BL1 (BL2). The bit voltage. Further, the plurality of anti-fuse memories 2a and 2b (2c, 2d) arranged along the switching word line PWL1 (PWL2) and the memory word line NWL1 (NWL2) are self-switching word lines PWL1 (PWL2). A specific switching voltage is applied uniformly, and a specific memory voltage is uniformly applied from the memory word line NWL1 (NWL2).

Thereby, the semiconductor memory device 1 can be applied to the respective memory word lines NWL1, NWL2 by selecting the voltage values applied to the bit lines BL1, BL2, the voltage values applied to the respective switching word lines PWL1, PWL2, and the voltage values applied to the respective memory word lines NWL1, NWL2. Voltage value, but only for a plurality of anti-fuse memories Among the 2a, 2b, 2c, and 2d, for example, the anti-fuse memory 2a of the 1st row of the 1st column is written, or only the data of the anti-fuse memory 2a of the 1st row of the 1st column is read.

Here, since the anti-fuse memory bodies 2a, 2b, 2c, and 2d have the same configuration as a whole, the following description will be focused on the anti-fuse memory 2a of the first row and the first row. The anti-fuse memory 2a includes a switching transistor S and a memory capacitor M, and a switching word line PWL1 is connected to the switching gate electrode PG provided in the switching transistor S, and is stored in the memory of the memory capacitor M. The gate electrode NG is connected to the memory word line NWL1.

In addition to the above configuration, the anti-fuse memory 2a of the present invention forms the memory gate electrode NG of the memory capacitor M by the N-type first conductivity type, and forms the switch of the P-type second conductivity type. The switching gate electrode PG of the transistor S is coupled to the P-type switching gate electrode PG and the N-type memory gate electrode NG to form a PN by switching the gate electrode PG and the memory gate electrode NG. Join the diodes.

Actually, the switching transistor S has a switching gate insulating film 7 formed of an insulating member and a switching gate electrode PG disposed on the well, and the voltage difference between the switching gate electrode PG and the bit line BL1 is formed. The channel region of the well opposite to the switching gate electrode PG is switched to the on state (on state), and the bit voltage of the bit line BL1 can be applied to the channel region of the memory capacitor M.

On the other hand, the memory capacitor M has a configuration in which a memory gate insulating film 8 which is formed integrally with the switching gate insulating film 7 on the well and which is disposed in the same layer as the switching gate insulating film 7 is provided. A memory gate electrode NG is disposed on the memory gate insulating film 8. In this case, the memory capacitor M is formed by insulatingly destroying the memory gate insulating film 8 by a voltage difference generated between the memory gate electrode NG and the channel region of the well, by The memory gate insulating film 8 is insulated and destroyed, and can be in a state of writing data.

In fact, as shown in FIG. 2, the anti-fuse memory 2a of the present invention includes, for example, a The P-type well W on the semiconductor substrate DW is formed with the impurity diffusion region 5 and the element isolation layer 4 at a predetermined interval on the surface of the well W. The impurity diffusion region 5 is a P-type having a conductivity type opposite to that of the well W, and has a configuration in which a bit line BL1 is connected to the surface. For the impurity diffusion region 5, a breakdown bit voltage, a non-destruction bit voltage, a read selection bit voltage, and the like can be applied from the bit line BL1.

Further, in the well W, a channel region exists on the surface between the impurity diffusion region 5 and the element isolation layer 4, and a switching gate insulating film 7 and a memory gate insulating film 8 are formed along the channel region. A gate electrode MG is formed on the switch gate insulating film 7 and the memory gate insulating film 8.

Further, sidewalls 9 including SiO ₂ or the like are formed on both side portions of the gate electrode MG, and one portion of the impurity diffusion region 5 is formed in a region below the sidewall 9. Incidentally, in the case of this embodiment, the impurity diffusion region 5 is formed just below the side surface of the gate electrode MG in the region below the side wall 9.

Here, the gate electrode MG is formed such that the switch gate electrode PG is disposed on the side of the impurity diffusion region 5 to which the bit line BL1 is connected, and the memory gate electrode is disposed on the element isolation layer 4 side of the other. NG, one of the other side faces of the memory gate electrode NG may be disposed opposite to the element isolation layer 4.

Further, in the case of this embodiment, one side surface of the gate electrode PG of the P-type switch gate electrode PG is bonded to one side surface of the N-type memory gate electrode NG to form a PN junction diode, if applied When the memory voltage to the memory gate electrode NG is higher than the switching voltage applied to the switch gate electrode PG, the voltage from the memory gate electrode NG to the switching gate electrode PG is reverse biased, thereby The voltage application from the memory gate electrode NG to the switching gate electrode PG can be blocked.

Further, in the case of the embodiment, the anti-fuse memory 2a is configured such that the work function of the switch gate electrode PG is different from the work function of the memory gate electrode NG, and the switch gate electrode PG is applied to the switch gate. The effective switching voltage (effective voltage) of the pole insulating film 7 The difference produces a change that can be reduced.

For example, in the case where the well W is formed by the P-type, the work function of the switching gate electrode PG disposed on the side of the impurity diffusion region 5 to which the bit line BL1 is connected is larger than the work function of the memory gate electrode NG. Selected. Here, the relationship between the work functions of the switching gate electrode PG and the memory gate electrode NG can also be considered as follows. The anti-fuse memory 2a is selected such that the difference between the work function of the memory gate electrode NG and the well W is larger than the difference between the work functions of the switch gate electrode PG and the well W, thereby writing the data described later. At this time, the voltage applied to the switching gate insulating film 7 can be alleviated, and a larger effective voltage can be applied to the memory gate insulating film 8.

In addition, the gate electrode MG is formed into the same film thickness as the gate electrode PG and the memory gate electrode NG, and is formed in the bottom of the switch gate electrode PG and the memory gate electrode NG without a step. bottom. Thereby, the gate electrode MG is in the channel region, and the film thickness of the switching gate insulating film 7 formed between the well W and the switching gate electrode PG is formed between the well W and the memory gate electrode NG. The film thickness of the memory gate insulating film 8 is selected to be substantially the same film thickness.

Incidentally, the semiconductor memory device 1 including the anti-fuse memory 2a, 2b, 2c, and 2d can be formed by using photolithography technology in addition to a general semiconductor manufacturing process, and when forming the gate electrode MG. In the ion implantation method, an N-type impurity or a P-type impurity is ion-implanted into the polysilicon gate region, and a P-type switch gate electrode PG is uniformly formed in a region of the gate electrode MG, and another region of the gate electrode MG is The shape success function and the N-type memory gate electrode NG different in conductivity type from the switch gate electrode PG.

(2) Data writing action

Next, a case where only data is written to the anti-fuse memory 2a of the first row and the first row in the semiconductor memory device 1 shown in FIG. 1 will be described below. Here, the anti-fuse memory 2a for writing data is also referred to as write selection memory 2W, and on the other hand, anti-fuse memory 2b, 2c, 2d which is not written data is also referred to as writing. Non-selective memory 2N. In this case, a broken bit voltage of 0 [V] can be applied to the bit line BL1 to which the write selection memory 2W is connected, and 3 can be applied to the switch word line PWL1 to which the write selection memory 2W is also connected. Write the selection switch voltage for V]. Further, a corrupted memory voltage of 5 [V] can be applied to the memory word line NWL1 which is also connected to the write selection memory 2W.

On the other hand, a non-destructive bit voltage of 3 [V] can be applied to the other bit lines BL2 to which only the anti-fuse memories 2b, 2d (written to the non-selective memory 2N) to which data is not written are connected. Further, a write non-selection switching voltage of 0 [V] can be applied to the switching word line PWL2 to which only the anti-fuse memory 2c, 2d (written to the non-selective memory 2N) to which data is not written is connected, and A non-destructive memory voltage of 0 [V] is applied to the memory word line NWL2 to which only the write non-select memory 2N is connected. Further, in this case, a substrate voltage of 0 [V] can be applied to the well in which the anti-fuse memory 2a, 2b, 2c, 2d is formed.

In the write selection memory 2W, the write selection switch voltage applied to the gate [3] of the switch gate electrode PG from the switch word line PWL1, and the channel region of the well W opposite to the switch gate electrode PG It is turned on. Further, the write selection memory 2W is caused by the destruction of the memory voltage of 5 [V] applied from the memory word line NWL1 to the memory gate electrode NG, and the well W facing the memory gate electrode NG. The channel area is also turned on.

At this time, in the write selection memory 2W, since the destruction bit voltage of 0 [V] is applied to the impurity diffusion region 5 from the bit line BL1, the pair of the switching gate electrode PG and the memory gate electrode NG are The channel region in which the channel state is turned on becomes a breakdown bit voltage of 0 [V], and as a result, between the memory gate electrode NG and the channel region facing the memory gate electrode NG, A voltage difference of 5 [V] formed by destroying the word voltage and destroying the bit voltage can be generated.

At this time, the write selection memory 2W is formed by bonding the N-type memory gate electrode NG and the P-type switch gate electrode PG to form the PN junction diode, so that the memory gate insulating film 8 is insulated and destroyed. The high voltage that is applied to the memory gate electrode NG destroys the memory The voltage which is reverse biased between the memory gate electrode NG and the switch gate electrode PG is not applied from the memory gate electrode NG to the switch gate electrode PG.

Thereby, the write selection memory 2W generates a voltage difference formed by the broken bit voltage and the broken word voltage only in the arrangement region of the memory gate electrode NG, and only the memory of the lower portion of the memory gate electrode NG. The gate insulating film 8 is broken in insulation, and the memory gate electrode NG and the impurity diffusion region 5 are turned on with a low resistance, and can be in a state of writing data.

Thus, since the write selection memory 2W is not limited to the high voltage of the memory gate electrode NG, the write selection switch is required to make the channel region the minimum voltage necessary for the ON state. Since the voltage is applied to the switching gate electrode PG, even if the film thickness of the switching gate insulating film 7 is formed thin, the switching gate insulating film 7 is not broken by the dielectric voltage of the memory, but can be maintained. Insulation state.

Further, in the case of this embodiment, the write selection memory 2W is different in the work function of the switching gate electrode PG and the memory gate electrode NG, and the application of the self-switching gate electrode PG to the switching gate can be further reduced. The effective voltage of the insulating film 7 can suppress the accumulation of the load caused by the voltage of the switching gate insulating film 7.

For example, in the case of this embodiment, in the write selection memory 2W, the voltage of the damaged memory applied to the memory gate electrode NG is selected to be 5 [V], which is applied to the switching gate electrode PG. The write selection switch voltage is selected to be 3 [V], so that the voltage value applied to the switch gate electrode PG can be lowered by 2 [V] from the voltage value of the memory gate electrode NG, and further, according to the work function. The effective voltage value applied from the memory gate electrode NG to the memory gate insulating film 8 is reduced by about 1 [V]. As described above, in the write selection transistor 2W, the voltage value applied to the switch gate insulating film 7 can be set to be lower than the voltage difference of 5 [V] generated in the memory gate insulating film 8. 2 [V] of 2 [V]. Thus, in the write selection memory 2W, the memory gate insulating film 8 can be insulated and destroyed during the data writing operation, and the voltage applied to the switching gate insulating film 7 can be alleviated, whereby the switch can be turned on. The film thickness of the gate insulating film 7 is thinned.

Incidentally, in the anti-fuse memory 2b in which the shared write selection memory 2W, the switch word line PWL1, and the memory word line NWL1 are not written, the voltage value is applied from the bit line BL2. High non-destructive bit voltage of 3 [V], so even if a 5 [V] destructive word voltage is applied to the memory gate electrode NG, the voltage difference between the memory gate electrode NG and the bit line BL2 becomes small. Therefore, the memory gate insulating film 8 at the lower portion of the memory gate electrode NG is not broken by the insulation, but is still in an insulated state, so that the state in which the data is not written can be maintained.

On the other hand, in the other anti-fuse memories 2c, 2d to which the non-destructive memory voltage of 0 [V] is applied, since 0 [V] is applied to the memory word line NWL2, no memory gate is generated. The voltage difference between the electrode NG and the well to which the substrate voltage of 0 [V] is applied, and the memory gate insulating film 8 of the lower portion of the memory gate electrode NG are not insulated and remain insulated, and can be maintained without being written. The status of the data. As described above, in the semiconductor memory device 1, data can be written only to the anti-fuse memory 2a required for the anti-fuse memory 2a, 2b, 2c, and 2d arranged in a matrix.

(3) Data reading action

In the semiconductor memory device 1, for example, as shown in FIG. 3, which is denoted by the same reference numeral as that of FIG. 1, the data of the anti-fuse memory 2a disposed in the first row and the first row is read. The case where the data of the other anti-fuse memory 2b, 2c, and 2d is not read will be described. In the following, the anti-fuse memory 2a for reading data is referred to as the read selection memory 2R, and the anti-fuse memory 2b, 2c, 2d for which data is not read is referred to as the read non-selective memory 2NR.

In the case of this embodiment, the semiconductor memory device 1 can apply 0 [V] to the bit line BL1 connected to the read selection memory 2R after initially charging all the bit lines to 1.2 [V]. The selected bit voltage is read, and on the other hand, a read non-selected bit voltage of 1.2 [V] is applied to the other bit lines BL2 to which only the non-selected memory 2NR is read.

Further, at this time, in the semiconductor memory device 1, a read selection switch voltage of 1.2 [V] can be applied to the switch word line PWL1 to which the read selection memory 2R is connected, and a read selection memory 2R can be connected to the same. The memory word line NWL1 applies a read selection memory voltage of 1.2 [V]. Thereby, since the read selection memory 2R is applied with a read selection switch voltage of 1.2 [V] to the switch gate electrode PG from the switch word line PWL1, the channel region facing the switch gate electrode PG can be It is turned on.

At this time, for example, when the memory gate insulating film 8 of the selection memory 2R is damaged by insulation (data has been written), the channel region facing the memory gate electrode NG becomes the memory gate. The electrode NG has the same potential (in this case, the read memory voltage is 1.2 [V]), and the selected memory voltage can be read via the channel region in which the switch gate electrode PG is turned on. Applied to the bit line BL1. Thus, in the bit line BL1, the read selection bit voltage can be changed from Low to High (for example, from 0 [V] to 0.7 [V]).

On the other hand, when the memory gate insulating film 8 of the selected memory 2R is not damaged by insulation (data is not written), the memory gate electrode NG and the channel region become non-conductive, so even The channel region opposite to the switch gate electrode PG is turned on, and the read selection memory voltage from the memory word line NWL1 is not applied to the bit line BL1, and the read selection of the bit line BL1 is not performed. The bit voltage is still 0 [V] without a change. As described above, in the semiconductor memory device 1, it is possible to determine whether or not the data has been written to the read selection memory 2R based on the change in the voltage value of the bit line BL1.

In addition, at this time, in the anti-fuse memory 2c which shares the unread data of the read selection memory 2R and the bit line BL1, the read non-selection of 0 [V] has been applied to the switch word line PWL2. Since the switching voltage is applied, the channel region opposed to the switching gate electrode PG is turned off (non-conducting state). Thereby, the anti-fuse memory 2c blocks the electrical connection between the memory capacitor M and the bit line BL1 by switching the transistor S, and does not block the bit line BL1 shared with the read selection memory 2R. Reading the selected bit voltage has an effect.

On the other hand, it is connected to a read non-selection bit voltage to which 1.2 [V] is applied (although it is set to 1.2 [V] here, but the voltage value can be arbitrarily selected within the range of 0 to 1.2 [V]. In the anti-fuse memory 2b, 2d of the un-read data of the bit line BL2, any one of them is applied to and read from the memory gate electrode NG from the memory word lines NWL1 and NWL2. The selected non-selected memory voltage is the same as the bit voltage of 1.2 [V], so even if the memory gate insulating film 8 is broken by the insulation, the read non-selected bit voltage of the bit line BL2 does not change, and It is impossible to judge whether or not there is data to be written. Thus, in the semiconductor memory device 1, only the data of the desired anti-fuse memory 2a can be read.

Further, in the case of the embodiment, when the memory gate insulating film 8 of the anti-fuse memory 2b is broken by insulation during the data reading operation, a conduction path is formed between the memory gate electrode NG and the channel region. When 0 [V] is applied to the bit line BL2 (non-selected line) of the anti-fuse memory 2b, 2d to which only unread data is connected, 1.2 [V] of the memory word line NWL1 is caused. The voltage charges the bit line BL2 via the anti-fuse memory 2b, thereby generating a residual current irrespective of reading.

Therefore, in the present invention, after the bit lines BL1, BL2 are both initially charged to 1.2 [V], the bit line to which only the read non-select memory 2NR is connected is still set to 1.2 [V]. Only the bit line BL1 connected to the read selection memory 2R is discharged to 0 [V], and the data of the read selection memory 2R can be read. Thereby, the case where the voltage of 1.2 [V] of the memory word line NWL1 is charged to the bit line BL2 via the anti-fuse memory 2b does not occur, and the generation of the residual current as described above can be prevented.

(4) Function and effect

In the above configuration, for example, the N-type memory gate electrode NG formed on the memory gate insulating film 8 and the P-type formed on the switching gate insulating film 7 are formed in the anti-fuse memory 2a. The switching gate electrode PG is joined to form a PN junction diode. When the data is written, the damaged memory voltage applied to the memory gate electrode NG becomes between the memory gate electrode NG and the switching gate electrode PG. Reverse bias voltage.

Thus, in the anti-fuse memory 2a, the voltage of the memory voltage is reverse-biased between the memory gate electrode NG and the switching gate electrode PG by breaking the memory voltage of the memory gate insulating film 8 The film thickness of the switching gate insulating film 7 can be formed thinly without being limited by the high voltage to destroy the memory voltage, thereby realizing the channel region in the switching gate electrode PG during data reading. High-speed action of on/off action.

Further, in the anti-fuse memory 2a, it is possible to perform special processing such as easy destruction of impurities into the memory gate insulating film by ion implantation as in the prior art, and similarly to the switch gate insulating film 7, The memory gate insulating film 8 is formed by the film quality which is not easily broken when the data is read. Therefore, even if the read selection memory voltage is repeatedly applied to the memory gate electrode NG, the memory gate insulating film 8 is not easily Insulation damage, which improves the reliability of reading information when reading data.

Further, in the anti-fuse memory 2a, by using the memory gate electrode NG and the switching gate electrode PG as different work functions, the switching gate electrode PG can be made during the data writing operation. The voltage after the write selection switch voltage decrease number [V] is applied to the switch gate insulating film 7, so that the voltage value of the switch gate insulating film 7 can be lowered, so that the film thickness of the switch gate insulating film 7 can be formed. It is thinner.

Further, when the comparison is made with the same material, the work functions of the switching gate electrode PG and the memory gate electrode NG are fixed irrespective of the miniaturization (scale). Therefore, the thinner the film thickness of the switching gate insulating film 7 and the memory gate insulating film 8 between the gate electrode MG and the well W, the memory gate insulating film 8 which causes dielectric breakdown during the data writing operation. The difference in applied electric field between the switching gate insulating film 7 which maintains the insulating state (the dielectric breakdown is not generated) may become more remarkable. At this time, in the anti-fuse memory 2a, the thickness of the switching gate insulating film 7 and the memory gate insulating film 8 between the gate electrode MG and the well W can be reduced and the size can be reduced.

Further, in the anti-fuse memory 2a, since the switching gate electrode PG and the memory gate electrode NG are integrally formed adjacent to each other, the switching gate electrode PG and the memory gate electrode NG are not formed. There is a slit, so as a whole, it is possible to achieve a small width direction Modeling.

Further, in the anti-fuse memory 2a, since the respective thicknesses of the switching gate insulating film 7 and the memory gate insulating film 8 are formed to have the same film thickness, it is necessary to form a film thickness differently as before. Compared with the anti-fuse memory of the switch gate insulating film and the memory gate insulating film (Patent Document 1), the manufacturing process can be simplified.

Incidentally, for example, when the gate insulating film of the transistor provided in the control circuit for controlling the anti-fuse memory 2a is set to 4 [nm] or less, in the anti-fuse memory 2a, The film thickness of the switch gate insulating film 7 and the memory gate insulating film 8 is formed to be as thin as the gate insulating film of the control circuit (4 [nm] or less), and thus can be, for example, 5 [V] or less. Low voltage enables data writing.

In this case, in the semiconductor memory device 1 in which the anti-fuse memory devices 2a, 2b, 2c, and 2d are mounted, writing can be realized if a transistor having an input/output voltage of, for example, 2.5 [V] is present, and no higher is required. High pressure component. Further, when the thickness of the memory gate insulating film 8 and the switching gate insulating film 7 is 2.5 [nm] or less, writing of data can be realized at a low voltage of, for example, 3.5 [V] or less, and only The writing of data can be realized by a transistor having an input/output element of, for example, 1.5 [V] to 1.8 [V].

Further, in the anti-fuse memory bodies 2a, 2b, 2c, and 2d, the gate insulating film of the transistor provided in the control circuit for controlling the anti-fuse memory bodies 2a, 2b, 2c, and 2d can be used as described above. The thicknesses of the switch gate insulating film 7 and the memory gate insulating film 8 are all the same, so that it is not necessary to provide a special process for manufacturing the anti-fuse memory 2a, 2b, 2c, 2d, and the manufacturing process can be The semiconductor manufacturing process of the control circuit is simultaneously fabricated, so that the semiconductor memory device in which the control circuit and the anti-fuse memory 2a, 2b, 2c, and 2d are mounted can be easily manufactured.

(5) Other embodiments (5-1) Semiconductor memory device of other embodiments

Figure 4 showing the same reference numerals as the corresponding parts of Figure 1 shows other implementations. The semiconductor memory device 21 of the embodiment is different from the semiconductor memory device 1 of the above-described embodiment in that one memory word line NWL1 is shared by all the anti-fuse memory bodies 2a, 2b, 2c, and 2d. In such a semiconductor memory device 21, when only data is written to the anti-fuse memory 2a of the first row and the first row, and no data is written to other anti-fuse memory, all anti-melting can be performed. The memory word line NWL1 shared by the silk memories 2a, 2b, 2c, and 2d applies a corrupted memory voltage of 5 [V].

In this case, the data is written to the write selection memory 2W in the semiconductor memory device 21, or the anti-fuse memory 2b sharing the write selection memory 2W and the switch word line PWL1 is not written. The principle of the data is the same as that of the above embodiment, and the effect obtained by writing to the selected memory 2W is also the same, and therefore the description thereof is omitted here. Here, the following description focuses on the anti-fuse memories 2c and 2d which are not written with data by the principle different from the above embodiment.

In this case, the destruction bit voltage of 0 [V] can be applied to the bit line BL1 to which the write selection memory 2W is connected, and the anti-fuse memory 2b, 2d to which only unwritten data is connected can be written. The other bit line BL2 of the non-selected memory 2N) is applied with a non-destructive bit voltage of 3 [V]. Further, a write non-selection switching voltage of 0 [V] can be applied to the switching word line PWL1 to which only the anti-fuse memory 2c, 2d (written to the non-selected memory 2N) to which data is not written is connected.

Thereby, the anti-fuse memory 2c, 2d which is not written with data is written to the non-selection switch voltage by 0[V] applied from the switch word line PWL2 to the switch gate electrode PG, and the switch is made The channel region of the gate electrode of the gate electrode PG is turned off, and the memory capacitor M is electrically connected to the bit lines BL1 and BL2.

Therefore, as shown in FIG. 5, which is denoted by the same reference numeral as that of FIG. 2, for example, in the anti-fuse memory 2c, 5 has been applied to the memory gate electrode NG from the memory word line NWL1. V] destroys the memory voltage, so that the damaged memory voltage is transmitted to the well W, and can be formed along the periphery of the well surface facing the memory gate electrode NG. The channel layer CH of a particular channel potential.

Further, at this time, in the anti-fuse memory 2c in which data is not written, since the electrical connection between the memory capacitor M and the bit line BL1 is blocked, it is formed around the channel layer CH on the surface of the well W. The depletion layer D is formed such that the channel layer CH can be insulated from the switching transistor S or the bit line BL1.

Here, it is assumed that the capacitance (hereinafter referred to as a gate insulating film capacitance) C2 obtained by the memory gate electrode NG and the memory gate insulating film 8 is formed in the well W and surrounds the channel layer CH. When the capacitance of the layer D (hereinafter referred to as the depletion layer capacitance) C1 is 3 times (that is, C2 = 3 × C1), the channel potential V of the channel layer CH can be obtained by the channel potential V = (memory gate electrode The memory voltage MV-substrate voltage CN)×(the gate insulating film capacitor C2/(depletion layer capacitor C1+gate insulating film capacitor C2) is calculated by the equation.

Therefore, in the case of this embodiment, since the substrate voltage CV is 0 [V] and the memory voltage MV of the memory gate electrode NG is 5 [V], the channel potential V rises to about 3.5 to 4 [ V] around. Thereby, in the anti-fuse memory 2c in which data is not written, even if the memory voltage of 5 [V] is applied to the memory gate electrode NG, the channel surrounded by the depletion layer D is formed on the surface of the well W. Since the channel potential V of the layer CH becomes a high potential, the voltage difference between the memory gate electrode NG and the channel layer CH becomes small, so that the dielectric breakdown of the memory gate insulating film 8 can be prevented. Further, the anti-fuse memory 2d to which data is not written can also prevent dielectric breakdown of the memory gate insulating film 8 in accordance with the same principle as the above-described anti-fuse memory 2c.

However, in the case where the data is not written against the fuse memory 2c, 2d, the channel potential formed in the channel layer CH of the anti-fuse memory 2c, 2d is formed at the start of the data writing operation. Since it is not fixed, the actual voltage writing operation causes the voltage applied to the memory gate insulating film 8 to vary due to the voltage of the bit lines BL1 and BL2.

Therefore, as shown in FIG. 4, it is desirable to first apply an anti-fuse memory after applying a reset voltage of, for example, 3 [V] to each of the bit lines BL1, BL2 and each of the switch word lines PWL1, PWL2. The switching transistor S of 2c and 2d is set to the ON state, and the channel potential of the memory capacitor M is raised to about 2.5 [V]. Thereafter, the switching word line PWL2 is turned off, and the bit line BL1 is turned off. Set to 0 [V]. Thereby, in the anti-fuse memory 2c, 2d in which the data is not written, the channel layer CH of the memory capacitor M is blocked from the outside by voltage application from the switch word line PWL2, and the channel potential is fixed at 3 [ V] around. Here, since the memory voltage of 5 [V] is applied to the memory word line NWL1, the channel potential can be further increased by capacitive coupling from the state where the channel potential is fixed.

(5-2) Detailed composition of anti-fuse memory of other embodiments

Here, FIG. 6 showing the same reference numerals as those in FIG. 2 is a schematic view showing a cross-sectional configuration of the anti-fuse memory 22 of another embodiment. The anti-fuse memory 22 is different from the anti-fuse memory 2a, 2b, 2c, 2d shown in FIG. 2 described above in that the memory gate electrode NG has a shape across the switching gate electrode PG.

Similarly to the above-described embodiment, the anti-fuse memory 22 has a switching gate insulating film 7 and a memory gate insulating film 8 formed on the surface of the well W, and is insulated on the switching gate insulating film 7 and the memory gate. On the film 8, a gate electrode MG1 is formed. The gate electrode MG1 has a configuration in which the memory gate electrode NG1 forming the memory capacitor M1 is formed on the memory gate insulating film 8, and has a switching gate electrode PG forming the switching transistor S1 formed on the switching gate The structure on the insulating film 7.

Further, in the case of the embodiment, the gate electrode MG1 is formed with an N-type memory gate electrode NG so that one side of the P-type switch gate electrode PG straddles the upper surface, and the memory gate is formed. The electrode PG is joined to the switching gate electrode NG1 to form a PN junction diode. Therefore, the gate electrode MG1 is also connected to the gate electrode PG1 from the memory gate electrode NG1 if the memory voltage applied to the memory gate electrode NG1 is higher than the switching voltage applied to the switch gate electrode PG. The voltage is applied as a voltage of the reverse bias voltage, so that the voltage application from the memory gate electrode NG1 to the switching gate electrode PG can be blocked.

Moreover, in the case of this embodiment, the anti-fuse memory 22 is also in the same manner as described above. Similarly, the work function of the switch gate electrode PG is different from the work function of the memory gate electrode NG1, and the voltage value of the switching voltage applied from the switch gate electrode PG to the switch gate insulating film 7 can be reduced.

In the above configuration, in the anti-fuse memory 22 shown in FIG. 6, the memory voltage is also broken between the memory gate electrode NG1 and the switching gate electrode PG due to insulation breakdown of the memory gate insulating film 8. Since the voltage is reverse biased, the film thickness of the switch gate insulating film 7 can be reduced without being limited by the high voltage to destroy the memory voltage, thereby enabling the switching gate electrode PG during data reading. The high-speed action of the on/off action of the channel area in the middle.

Further, in the anti-fuse memory 22, it is possible to perform the special processing such as easy destruction of the memory gate insulating film by ion implantation as in the prior art, and the same as the switching gate insulating film 7 The memory gate insulating film 8 is formed by the film quality which is not easily broken when the data is read, so even if the read selection memory voltage is repeatedly applied to the memory gate electrode NG1, the memory gate insulating film 8 is not It is easily damaged by insulation, which improves the reliability of reading information when reading data.

Further, in the anti-fuse memory 22, the memory gate electrode NG1 and the switching gate electrode PG can be set to different work functions, and the gate electrode PG can be switched during the data writing operation. The voltage after the write selection switch voltage reduction number [V] is applied to the switch gate insulating film 7 can reduce the voltage value of the switch gate insulating film 7, so that the film thickness of the switch gate insulating film 7 can be formed. It is thinner.

(5-3) Others

In addition, the present invention is not limited to the embodiment, and various modifications can be made within the scope of the gist of the invention. For example, the voltage values shown in FIG. 1 or FIGS. 3 and 4 can be applied to various other voltages. value.

Further, in the above embodiment, the plurality of anti-fuse memories provided in the semiconductor memory devices 1 and 21 are all set to the memory gate electrodes NG, NG1, and the switches. The case where the gate electrode PG forms the PN junction diode of the anti-fuse memory 2a, 2b, 2c, 2d, 22 of the present invention is described, but the present invention is not limited thereto, and may be provided in the semiconductor memory. At least one or more of the anti-fuse memories of the plurality of anti-fuse memories of the device 1 are used as the semiconductor memory devices of the anti-fuse memories 2a, 2b, 2c, 2d, and 22 of the present invention.

Further, in the above-described embodiment, the case where the thickness of the switching gate insulating film 7 is formed to be the same as the thickness of the memory gate insulating film 8 is described. However, the present invention is not limited thereto; The film thickness of the pole insulating film is not less than the film thickness of the memory gate insulating film, and the thickness of the switching gate insulating film and the memory gate insulating film may be set to various film thicknesses. However, the film thickness of the switching gate insulating film and the memory gate insulating film is preferably 4 [nm] or less, and more preferably 2.5 [nm] or less.

Further, in the above-described embodiment, the N-type impurity diffusion region 5 is provided for the P-type well W, and the memory gate electrode NG (NG1) which is the N-type first conductivity type is further provided, and The anti-fuse memory 2a, 2b, 2c, and 2d (22) in which the second conductivity type is the P-type switch gate electrode PG will be described, but the present invention is not limited thereto, and the N-type can also be applied. The well is provided with a P-type impurity diffusion region, and further includes an anti-fuse memory as a memory gate electrode in which the first conductivity type is a P-type and a switching gate electrode in which a second conductivity type is an N-type.

Further, in this case, when the well W is formed in the N-type, the work function of the N-type switch gate electrode PG disposed on the side of the impurity diffusion region 5 to which the bit line BL1 is connected is smaller than that of the P-type memory. The manner of the work function of the gate electrode NG is selected. Therefore, in the anti-fuse memory, the effective switching voltage (effective voltage) applied from the switching gate electrode to the switch gate insulating film changes the work function difference, thereby reducing the insulation of the switch gate. The effective voltage of the membrane.

1‧‧‧Semiconductor memory device

2a‧‧‧Anti-fuse memory

2b‧‧‧Anti-fuse memory

2c‧‧‧Anti-fuse memory

2d‧‧‧Anti-fuse memory

2N‧‧‧Write to non-selective memory

2W‧‧‧Write selection memory

7‧‧‧Switch gate insulating film

8‧‧‧Memory gate insulating film

BL1‧‧‧ bit line

BL2‧‧‧ bit line

M‧‧‧ memory capacitor

NG‧‧‧ memory gate electrode

NWL1‧‧‧ memory word line

NWL2‧‧‧ memory word line

PG‧‧‧Switch Gate Electrode

PWL1‧‧‧ switch word line

PWL2‧‧‧ switch word line

S‧‧‧Switching transistor

Claims (6)

An anti-fuse memory characterized by: a well having a surface formed with an impurity diffusion region to which a bit line is connected; a memory gate insulating film formed on the well; and a first conductivity type memory gate a pole electrode formed on the memory gate insulating film, applying a damaged memory voltage for insulating and destroying the memory gate insulating film; and a switch gate insulating film formed on the impurity diffusion region and the memory gate The well between the pole insulating films is formed integrally with the memory gate insulating film; and the switch gate electrode is formed of a second conductivity type that is opposite to the memory gate electrode, and Formed on the switch gate insulating film and bonded to the memory gate electrode; and the damaged memory voltage applied to the memory gate electrode is between the memory gate electrode and the switch gate electrode Become the voltage of the reverse bias. The anti-fuse memory of claim 1, wherein a channel region of the well opposite to the switch gate electrode is switched to an on state, and a breakdown bit voltage from the bit line is applied to the memory gate The channel region of the well opposite to the electrode is insulated from the memory gate insulating film by a voltage difference between the breakdown bit voltage of the channel region and the memory voltage of the memory gate electrode. The anti-fuse memory of claim 1, wherein the film thickness of the switching gate insulating film is formed to be equal to or less than a film thickness of the memory gate insulating film. Such as claim 1 of the anti-fuse memory, wherein By making the work function of the memory gate electrode different from the work function of the switch gate electrode, the work function difference and the effective voltage applied from the switch gate electrode to the switch gate insulating film are reduced. A semiconductor memory device, characterized in that: an anti-fuse memory is disposed on each of the intersections of the plurality of bit lines with respect to the plurality of switch word lines and the plurality of memory word lines; and the anti-melting A silk memory system is the anti-fuse memory of any one of claims 1 to 4. The semiconductor memory device of claim 5, wherein the memory is shared by a plurality of the anti-fuse memories sharing a plurality of the switching word lines and a plurality of the other anti-fuse memories sharing the other switching word lines. Body word line.