TW201626389A - Resistive memory device - Google Patents

Abstract

A resistive memory device is provided. A first cell is coupled to a word line, a first bit line and a source line. A second cell is coupled to the word line, a second bit line and the source line. A control circuit controls the levels of the word line, the first bit line and the source line to execute a set operation for the first cell and execute a reset operation for the second cell. After the set and the reset operations, the resistance of the first cell is less than the resistance of the second cell. During the execution of the set operation, the control circuit asserts the level of the source line at a pre-determined level. During the execution of the reset operation, the control circuit asserts the level of the source line at the pre-determined level.

Description

Resistive memory device

The present invention relates to a memory device, and more particularly to a resistive memory device.

In general, computer memory is divided into volatile memory and non-volatile memory. Non-volatile memory includes read only memory (ROM), programmable read only memory (PROM), erasable orchestratable read only memory (EPROM), and flash memory. Volatile memory includes Dynamic Random Access Memory (DRAME) and Static Random Access Memory (SRAM).

Current novel volatile memories include ferroelectric memory, phase-change memory, magnetic memory (MRAM), and resistive memory (RRAM). Resistive memory is widely used because of its simple structure, low cost, fast speed and low power consumption.

The invention provides a resistive memory device comprising a first memory cell, a second memory cell and a control circuit. The first memory cell is coupled to a word line, a first bit line, and a source line. The second memory cell is coupled to the word line, a second bit line, and a source line. The control circuit controls the level of the word line, the first bit line, and the source line to perform a setting action on the first memory cell. After the setting action is performed, the first memory cell has a first impedance. Control circuit control word The levels of the first line, the second bit line, and the source line are used to perform a reset action on the second memory cell. After the reset action, the second memory cell has a second impedance. The second impedance is greater than the first impedance. When the setting action is performed, the control circuit causes the level of the source line to be a predetermined level. When the reset action is performed, the control circuit sets the level of the source line to a preset level.

The invention further provides a control method suitable for a resistive recording Memories. The resistive memory device has a first memory cell and a second memory cell. The first memory cell is coupled to a word line, a first bit line, and a source line. The second memory cell is coupled to the word line, a second bit line, and a source line. The control method of the present invention includes performing a setting operation for causing the first memory cell to have a first impedance and performing a resetting operation for causing the second memory cell to have a second impedance. The second impedance is greater than the first impedance. Both the setting and resetting actions include providing a preset level to the source line.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

100‧‧‧Resistive memory device

110‧‧‧ memory array

120‧‧‧Control circuit

WL<0>~WL<M>‧‧‧ character line

BL<0>~BL<N>‧‧‧ bit line

SL<0>~SL<M>‧‧‧Source line

M ₀₀ ~M _MN ‧‧‧ memory cell

121‧‧‧ column decoder

122‧‧‧ line decoder

123‧‧‧Write buffer

124‧‧‧ position controller

125‧‧‧Sensing amplification unit

AW‧‧‧ input address

AB‧‧‧Input address

DA‧‧‧ Input data

V _ON1 , V _ON1 ‧‧‧Open level

V _OFF1 , V _OFF2 ‧‧‧Closed

V _SET1 , V _SET2 ‧‧‧Set level

V _SL ‧‧‧Preset level

V _VRF1 , V _VRF2 ‧‧‧ reading level

V _RESET1 , V _{RESET2 ‧‧‧Reset} level

310, 320, 330, 340, 350, 360, 410, 420, 430, 440, 450, 460‧‧‧ current paths

S510, S520, S530‧‧‧ steps

Figure 1 is a schematic view of a resistive memory device of the present invention.

FIG. 2 is a schematic diagram showing the internal structure of the memory array 110 of the present invention.

3A, 3B, 4A, and 4B are schematic diagrams of the level of the word line, the bit line, and the source line.

Figure 5 is a flow chart of the control method of the present invention.

Figure 1 is a schematic view of a resistive memory device of the present invention. As shown, the resistive memory device 100 includes a memory array 110, a control circuit 120, word lines WL<0>~WL<M>, bit lines BL<0>~BL<N>, and source lines. SL<0>~SL<M>. Memory array 110 includes memory cells M ₀₀ ~M _MN . Each memory cell is coupled to a corresponding word line, bit line, and source line. Taking the memory cells M ₀₀ and M ₀₁ as an example, the memory cell M _{00 is} coupled to the word line WL<0>, the bit line BL<0>, and the source line SL<0>; the memory cell M _{01 is} coupled to the word line. WL<0>, bit line BL<1>, and source line SL<0>.

The control circuit 120 controls the levels of the word lines WL<0>~WL<M>, the bit lines BL<0>~BL<N>, and the source lines SL<0>~SL<M> for accessing Memory cell M ₀₀ ~M _MN . For example, in a write mode, the control circuit 120 performs a set action or a reset action on the memory cells M ₀₀ to M _MN for writing data to the memory cell M ₀₀ ~ M _MN . In a read mode, the control circuit 120 performs a verify operation for reading data stored by the memory cells M ₀₀ to M _MN .

For example, after the control circuit 120 performs a setting operation on a first specific memory cell, the first specific memory cell has a low impedance to indicate that the data stored in the first specific memory cell is zero. After the resetting operation, a second specific memory cell has a high impedance to indicate that the data stored in the second specific memory cell is one. Thus, control circuit 120 in accordance with the impedance of the memory cell M ₀₀ ~ M _MN, and can be ₀₀ ~ M _MN information that is stored in the memory cell M.

In the present embodiment, the control circuit 120 maintains the levels of the source lines SL<0>~SL<M> at a preset level during the setting, resetting, and verifying operations. Since the level of the source lines SL<0>~SL<M> is maintained at a preset level, the control circuit 120 does not need to change the level of the source lines SL<0>~SL<M>, and thus can be shortened. The control circuit 120 writes the data to the write time of the memory cells M ₀₀ to M _MN .

In another embodiment, the control circuit 120 performs the set and reset actions simultaneously. For example, while the control circuit 120 performs a setting operation on the memory cell M ₀₀ , the control circuit 120 performs a reset operation on the memory cell M ₀₁ . In other embodiments, the control circuit 120 of the first memory cell M ₀₀ ~ M _MN setting operation is performed, and then the memory cell M ₀₀ ~ M _MN performs the reset operation.

In this embodiment, the control circuit 120 includes a column decoder 121, A row of decoders 122, a write buffer 123, a one-bit controller 124, and a sense amplification unit 125 are not intended to limit the invention. Any circuit structure that can control the level of the word line WL<0>~WL<M>, the bit line BL<0>~BL<N>, and the source line SL<0>~SL<M> As the control circuit 120.

The column decoder 121 is coupled to the word line WL<0>~WL<M>, and is connected to the input. The address AW is decoded, and at least one word line is turned on according to the decoding result. The row decoder 122 is coupled to the bit lines BL<0>~BL<N>, decodes the input address AB, and turns on at least one bit line according to the decoding result. The write buffer 123 writes the input data DA into at least one memory cell.

The level controller 124 is coupled to the source lines SL<0>~SL<M> for controlling The level of the source line SL<0>~SL<M>. In this embodiment, each of the source lines SL<0>~SL<M> is coupled to the same level controller 124. The present invention does not limit the connection relationship between the source lines SL<0>~SL<M> and the level controller. In another possible embodiment, the source lines SL<0>~SL<M> are first coupled together and then coupled to the one-bit controller. In other embodiments, the source lines SL<0>~SL<M> are divided into a number of groups. Each group is coupled to a corresponding level controller.

The sensing amplifying unit 125 verifies the data stored by the memory cells M ₀₀ to M _MN and outputs the data in a parallel out or serial out manner. The present invention does not limit how the sense amplification unit 125 verifies the memory cells. In a possible embodiment, the sensing amplification unit 125 uses a complementary sensing method to verify the data stored by the memory cells. In the complementary detection method, each memory cell includes a first memory cell and a second memory cell. The impedances of the first and second memory cells have a complementary relationship. In a possible embodiment, when the first and second memory cells have low impedance and high impedance respectively, it means that the data stored in the memory cell is 0; if the first and second memory cells have high impedance respectively At low impedance, it means that the data stored in this memory cell is 1. Therefore, based on the impedance of the first and second memory cells, the data stored in the memory cells can be known.

In another possible embodiment, the sensing amplification unit 125 uses a reference sensing method to verify the data stored by the memory cells. In the reference detection method, the sensing amplification unit 125 compares the impedance of each memory cell with a reference impedance, and according to the comparison result, the data stored by the memory cell is known.

FIG. 2 is a schematic diagram showing the internal structure of the memory array 110 of the present invention. For convenience of description, FIG. 2 only shows the word line WL<0>~WL<3>, the bit line BL<0>~BL<3>, the source line SL<0>~SL<2>, and the memory cell. M ₀₀ ~ M ₃₃ . In this embodiment, the source lines SL<0>~SL<2> are coupled together.

As shown, each memory cell has a transistor and a variable resistor. Taking the memory cell M ₀₀ as an example, the gate of the transistor T ₀₀ is coupled to the word line WL<0>. One end of the transistor T ₀₀ is coupled to the source line SL<0>. The variable resistor R _{00 is} coupled between the other end of the transistor T ₀₀ and the bit line BL<0>. In the present embodiment, when the control circuit 120 performs a setting operation on the memory cell M ₀₀ , the variable resistor R ₀₀ has a low impedance. When the control circuit 120 performs a reset operation on the memory cell M ₀₀ , the variable resistor R ₀₀ has a high impedance.

3A, 3B, 4A, and 4B are schematic diagrams of the level of the word line, the bit line, and the source line. For convenience of description, the 3A, 3B, 4A, and 4B diagrams only show the memory cells M ₀₀ ~ M ₁₃ , the word line WL<0>~WL<1>, the bit line BL<0>~BL<3>, and the source. The polar line SL<0>~SL<1>.

When the word line WL<0> is an on level V _ON1 , the transistors T ₀₀ to T _{03 of the} memory cells M ₀₀ to M ₀₃ can be turned on. Since the word line WL<1> is a turn-off level V _OFF1 , the transistors T ₁₀ to T _{13 of the} memory cells M ₁₀ to M ₁₃ are not turned on. In a possible embodiment, the off level V _OFF1 is a ground level.

In this embodiment, the level of the source lines SL<0>~SL<1> is a preset level V _SL . The bit line BL<0> is a set level V _SET1 , and the set level V _{SET1 is} greater than the preset level V _SL . Therefore, a current path 310 is formed in the memory cell M ₀₀ . Since the current of the current path 310 flows from the variable resistor R ₀₀ to the transistor T ₀₀ , a setting operation is performed on the memory cell M ₀₀ . After setting the action, the memory cell M ₀₀ has a low impedance. In a possible embodiment, the data stored in the memory cell M ₀₀ is zero.

In this embodiment, the level of the bit line BL<1> is equal to the preset level V _SL . Since the bit line BL<1> has the same level as the source line SL<0>, a current path is not formed in the memory cell M ₀₁ . Therefore, the memory cell M _{01 is} not set or reset. In other embodiments, if a specific memory cell is not required to be written or reset, the level of the bit line to which the specific memory cell is coupled may be equal to the level of the source line.

The bit line BL<2>~BL<3> is a reset level V _RESET1 . In the present embodiment, since the reset level V _{RESET1 is} smaller than the preset level V _SL , current paths 320 and 330 are formed in the memory cells M ₀₂ and M ₀₃ , respectively. Since the current of the current path 320 flows from the transistor T ₀₂ to the variable resistor R ₀₂ , a reset action is performed on the memory cell M ₀₂ . Similarly, the memory cell M ₀₃ will also perform a reset action. After the reset action, the variable resistors R ₀₂ and R ₀₃ are both high impedance. In the present embodiment, the data stored in the memory cells M ₀₂ and M ₀₃ are both 1.

The invention does not limit the size of the preset level V _SL . In this embodiment, the preset level V _SL is between the set level V _SET1 and the reset level V _RESET1 , and the set level V _{SET1 is} greater than the reset level V _RESET 1 _. In a possible embodiment, the reset level V _RESET1 is a ground level. In this case, the complexity of the resistive memory device can be reduced since no negative level is required.

In the present embodiment, when the setting and resetting operations are performed, the level of the source line SL<0> is maintained at the preset level _VSL . Further, since the setting operation and the resetting operation are simultaneously performed, the writing time of the array 110 can be largely memorized.

Figure 3B is a schematic diagram of the verify operation of the present invention. The word line WL<0> is an open level V _ON1 for verifying the data stored in the memory cells M ₀₀ ~ M ₀₃ . In this embodiment, when the verifying operation is performed, the level of the source line SL<0> is still maintained at the preset level _VSL . At this time, the level of the bit line BL<0>~BL<3> is a read level V _VRF1 . In this embodiment, the read level V _{VRF1 is} greater than the preset level V _SL . Therefore, current paths 340, 350, and 360 are formed in memory cells M ₀₀ , M _{02 ,} and M ₀₃ , respectively. The current of the current path 340 flows from the variable resistor R ₀₀ to the transistor T ₀₀ . The current of the current path 350 flows from the variable resistor R ₀₂ to the transistor T ₀₂ . The current of the current path 360 flows from the variable resistor R ₀₃ to the transistor T ₀₃ . In one possible embodiment, the current of current path 340 is greater than the current of current paths 350 and 360. The current of current path 340 may be 10 uA, and the current of current paths 350 and 360 may be 1 uA. In this embodiment, the impedance of the memory cells M ₀₀ to M ₀₃ can be known from the currents of the current paths 340, 350, and 360, and the memory cells can be known by the impedance of the memory cells M ₀₀ to M ₀₃ . Information stored in M ₀₀ ~ M ₀₃ .

Fig. 4A is a schematic view showing the setting and resetting operation of the present invention. Fig. 4A is similar to Fig. 3A except that the level of the source line SL<0> of Fig. 4A is a ground level GND. Since the level of the source line SL<0> is between the set level V _SET2 and the reset level V _RESET2 , it can be known that the set level V _SET2 is a positive level, and the reset level V is reset. _RESET2 is a negative level. In a possible embodiment, the level difference between the set level V _SET2 and the ground level GND is equal to the level difference between the reset level V _RESET2 and the ground level GND.

Since the level of the word line WL<1> is a closed level V _OFF2 , the transistors T ₁₀ to T ₁₃ in the memory cells M ₁₀ to M ₁₃ are not turned on. In a possible embodiment, the off level V _OFF2 is equal to the reset level V _RESET2 . In another embodiment, the off level _{VOFF2 is} less than the off level _VOFF1 . In other embodiments, the ON level V _ON2 , the set level V _SET2 , and the reset level V _{RESET2 of} FIG. _4A are respectively smaller than the ON level V _{ON1 of} the 3A diagram, the set level V _SET1 , and the reset level. V _RESET1 . Therefore, it is not necessary to use a large-sized high-voltage element as the transistors T ₀₀ to T ₁₃ , and the usable space of the memory device is increased and the component cost of the memory device is reduced. In the present embodiment, the current of the current path 410 flows from the variable resistor R ₀₀ to the transistor T ₀₀ ; the current of the current path 420 flows from the transistor T ₀₂ to the variable resistor R ₀₂ ; the current of the current path 430 is electrically The crystal T ₀₃ flows to the variable resistor R ₀₃ .

Figure 4B is a schematic diagram of the verification action of the present invention. The word line WL<0> is an open level V _ON2 for verifying the data stored in the memory cells M ₀₀ ~ M ₀₃ . In this embodiment, when the verifying operation is performed, the source line SL<0> is still the ground level GND. At this time, the bit lines BL<0>~BL<3> are all a read level V _VRF2 . In the present embodiment, the read level V _{VRF2 is} smaller than the read level V _VRF1 . In addition, the currents of the current paths 440, 450, and 460 are all flown into the transistor by the variable resistor.

Figure 5 is a flow chart of the control method of the present invention. Control of the invention The method is suitable for a resistive memory device. In a possible embodiment, the resistive memory device has a first memory cell and a second memory cell. The first memory cell is coupled to a word line, a first bit line, and a source line. The second memory cell is coupled to the word line, a second bit line, and the source line.

Step S510 performs a setting action. Assume that step S510 is The setting action is performed on the first memory cell. In a possible embodiment, an enable bit is provided to the word line, a set bit is provided to the first bit line, and a preset bit is provided to the source line. After performing the setting action, the first memory cell has a first impedance, such as a low impedance.

Step S520 performs a reset action. Assume that step S520 is correct The second memory cell performs a reset action. In a possible embodiment, an enable bit is provided to the word line, a reset bit is provided to the second bit line, and a preset bit is provided to the source line. In this example, after the reset action is performed, the second memory cell has a second impedance, such as a high impedance. The same level is supplied to the source line during setup and reset operations. Therefore, it is not necessary to adjust the level of the source line and reduce the writing time of the resistive memory device.

In a possible embodiment, steps S510 and S520 are performed simultaneously. In another embodiment, the reset level is less than the set level. In this embodiment, the pre The set level is between the set level and the reset level. In a possible embodiment, the reset level is a ground level.

In another possible embodiment, the preset level is a ground level. In this example, the reset level is a negative level. In other embodiments, if a specific memory cell is not required to be set or reset, a preset bit can be provided to the bit line to which the specific memory cell is coupled. In a possible embodiment, the specific memory cell is disposed between the first and second memory cells.

In other embodiments, step S530 is further included. Step S530 Perform a verification action. In a possible embodiment, step S530 detects the impedance of the first memory cell and compares the detection result with a reference impedance. In another possible embodiment, the first and second memory cells each have a first memory cell and a second memory cell. Taking the first memory cell as an example, step S530 reads the impedances of the first and second memory cells of the first memory cell, and learns the data value stored in the first memory cell according to the reading result.

In other embodiments, the opening is provided when the verification action is performed. The bit is given to the word line, a read bit is provided to the first and second bit lines, and a preset bit is provided to the source line for detecting the impedance of the memory cell. In a possible embodiment, the reading level is greater than the preset level, but is not intended to limit the invention. Since the same level is supplied to the source line when the verification operation is performed, the level of the source line is not required to be adjusted, so that the reading time of the resistive memory device can be shortened.

Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning In addition, unless explicitly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related technical field, and should not be interpreted as an ideal state or In the official voice.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

WL<0>, WL<1>‧‧‧ character line

BL<0>~BL<3>‧‧‧ bit line

SL<0>~SL<1>‧‧‧Source line

M ₀₀ ~M ₁₃ ‧‧‧ memory cells

R ₀₀ ~R ₁₃ ‧‧‧Variable resistor

T ₀₀ ~T ₁₃ ‧‧‧Optoelectronics

V _ON1 ‧‧‧Open level

V _OFF1 ‧‧‧Closed

V _SET1 ‧‧‧Set level

V _SL ‧‧‧Preset level

V _{RESET1 ‧‧‧Reset} level

310, 320, 330‧‧‧ current path

Claims (10)

A resistive memory device includes: a first memory cell coupled to a word line, a first bit line, and a source line; a second memory cell coupled to the word line and a second bit a source line and the source line; and a control circuit for controlling the level of the word line, the first bit line, and the source line for performing a setting action on the first memory cell After the setting operation, the first memory cell has a first impedance, and the control circuit controls the word line, the second bit line, and the level of the source line to perform a second memory cell. a resetting operation, after the resetting operation, the second memory cell has a second impedance, the second impedance being greater than the first impedance; wherein, when the setting action is performed, the control circuit causes the source line to The level is a preset level, and when the resetting operation is performed, the control circuit sets the level of the source line to the preset level. The resistive memory device of claim 1, wherein the control circuit performs the setting operation and the resetting operation simultaneously. The resistive memory device of claim 2, wherein the control circuit sets the first bit line to a set level and causes the second bit when performing the setting action and the resetting action The line is a reset level, and the reset level is less than the set level. The resistive memory device of claim 3, wherein the preset level is between the set level and the reset level. The resistive memory device of claim 4, wherein the preset level is a ground level. The resistive memory device of claim 1, wherein the control circuit controls the first and second memories by controlling a level of the word line, the first bit line, and the source line. The cell performs a verification operation for reading the data stored by the first and second memory cells. When the verification operation is performed, the level of the source line is equal to the preset level. The resistive memory device of claim 6, wherein the first and second bit lines have the same level when the verifying operation is performed. The resistive memory device of claim 7, wherein the control circuit has a sensing amplifying unit, and the sensing amplifying unit compares the impedance of the first memory cell with a reference impedance when performing the verifying action A comparison is made to verify the data stored by the first memory cell. The resistive memory device of claim 7, wherein the first memory cell has a first memory cell and a second memory cell, and the control circuit has a sensing amplification unit for performing the verification. During operation, the sensing amplification unit reads the impedances of the first and second memory cells to verify the data stored by the first memory cell. The resistive memory device of claim 1, further comprising: a third memory cell coupled to the word line, a third bit line, and the source line, wherein the third bit line Located between the first and second bit lines, when the control circuit performs the setting or resetting operation, the control circuit causes the third bit line to be the preset level; in the third memory cell The third memory cell does not provide a current path when performing the setting or resetting action.