TW201626356A - Liquid crystal display - Google Patents

Abstract

Provided is a liquid crystal display including: a liquid crystal panel assembly including a plurality of pixels; a data driver applying data voltages to a plurality of data lines connected to the plurality of pixels; and a signal controller generating image data signals to provide the generated image data signals to the data driver, in which the plurality of pixels includes a reactive mesogen (RM) alignment layer formed on a display panel, and the signal controller generates the image data signals by adjusting the data voltage with the maximum gray applied to the blue pixel to be decreased by a predetermined level.

Description

LCD Monitor

Embodiments of the present invention relate to a liquid crystal display and a driving method, and more particularly to a liquid crystal display using an RM alignment layer and a driving method thereof.

A liquid crystal display (LCD), one of the most commonly used types of flat panel displays, currently includes two display panels having electrodes and a liquid crystal layer disposed therebetween. The liquid crystal display generates an electric field by applying a voltage to the electrodes to readjust the liquid crystal molecules of the liquid crystal layer, and thereby controlling the transmittance of the light, thereby displaying an image.

The liquid crystal display has the advantage of facilitating the reduction of the thickness, but also has the disadvantage that the side visibility is deteriorated compared to the front side. Therefore, in order to solve this disadvantage, different kinds of liquid crystal alignment and driving methods have been developed. A liquid crystal display in which a pixel electrode and a common electrode are formed on a substrate is attracting attention as a method of realizing a wide viewing angle.

Recently, liquid crystal displays using a reactive mesogen (RM) alignment layer have been developed. Based on the low anchoring energy of the RM alignment layer, the liquid crystal display using the RM alignment layer has an effect of increasing transmittance compared to the existing liquid crystal display. However, in the liquid crystal display using the RM alignment layer, there is a problem that yellowish side light emission is observed at a high gray level.

The above information disclosed in this prior art section is only used to enhance the understanding of the background of the invention, and thus it may contain information that does not form the prior art known to those of ordinary skill in the art.

The present invention has been made in an effort to provide a liquid crystal display and a driving method thereof which have an advantage of avoiding light yellow side light emission in a liquid crystal display using an RM alignment layer.

An exemplary embodiment of the present invention provides a liquid crystal display including a liquid crystal panel assembly including a plurality of pixels, a data driver that applies a data voltage to a plurality of data lines connecting a plurality of pixels, and generates image data signals to provide a Generating the image data signal to the data controller of the data driver, wherein the plurality of pixels comprise at least one of a reactive liquid crystal (RM) alignment layer formed on the display panel, and the signal controller is adjusted by applying a predetermined level The data voltage with the largest gray level to the blue pixel is dropped to generate an image data signal.

The signal controller can generate image data signals, so when the ratio of the blue luminance to the y coordinate of the blue color coordinate is changed, the data voltage of the maximum gray scale applied to the blue pixel is adjusted to be high in the variable interval. Voltage.

The signal controller can generate image data signals, so the data voltage applied to the red and green pixels with the largest gray level maintains the original data voltage.

The signal controller can generate image data signals, so the data voltage with the largest gray level applied to the red pixels is adjusted to a high voltage in the variable interval.

The signal controller can generate image data signals, so the data voltage applied to the green pixel with the largest gray level is adjusted to a high voltage in the variable interval.

The maximum gray level can be 256 gray levels, and the variable interval can be 250 gray levels or less.

The signal controller can generate image data signals, so the data voltage applied to the blue pixel with the largest gray level is adjusted to a high voltage of 250 gray scale.

Each of the plurality of pixels may include a pixel electrode to which a data voltage is applied, and a common electrode to which a common voltage is applied to form an electric field with the pixel electrode, and the pixel electrode may include a cross main body including a horizontal stem and a vertical stem, and a horizontal stem Or a tiny branch of the vertical trunk that extends obliquely.

The pixel electrode may include a first sub-pixel electrode and a second sub-pixel electrode.

When the data voltage is applied to one pixel, the magnitude of the voltage applied to the first sub-pixel electrode and the magnitude of the voltage applied to the second sub-pixel electrode may be different from each other.

Another exemplary embodiment of the present invention provides a driving method of a liquid crystal display, the liquid crystal display including a plurality of pixels including an RM alignment layer formed on the display panel, and a plurality of gate lines and a plurality of data connected to the plurality of pixels a method comprising: continuously applying a gate signal of a gate turn-on voltage to a plurality of gate lines; and applying a data voltage to the plurality of data lines in response to a gate signal of the gate turn-on voltage, wherein the plurality of pixels comprise red The pixel, the green pixel, and the blue pixel, and the data voltage applied to the blue pixel having the largest gray level is adjusted by dropping the predetermined level.

When the ratio of the blue luminance to the y coordinate of the blue color coordinate is changed, the data voltage of the maximum gray scale applied to the blue pixel can be adjusted to a high voltage in the variable interval.

The data voltage applied to the red and green pixels with the largest gray level can be maintained at the original data voltage.

The data voltage applied to the red pixel with the largest gray scale can be adjusted to a high voltage in the variable interval.

The data voltage applied to the green pixel with the largest gray scale can be adjusted to a high voltage in the variable interval.

The maximum gray level can be 256 gray levels, and the variable interval can be 250 gray levels or less.

The data voltage applied to the blue pixel with the largest gray scale can be adjusted to a high voltage of 250 gray scale.

Each of the plurality of pixels may include a pixel electrode to which a data voltage is applied, and a common electrode to which a common voltage is applied to form an electric field with the pixel electrode, and the pixel electrode may include a cross main body including a horizontal stem and a vertical stem, and a horizontal stem or a vertical stem A tiny branch of the trunk that extends diagonally.

The pixel electrode may include a first sub-pixel electrode and a second sub-pixel electrode.

When the data voltage is applied to one pixel, the magnitude of the voltage applied to the first sub-pixel electrode and the magnitude of the voltage applied to the second sub-pixel electrode may be different from each other.

According to an exemplary embodiment of the present invention, it is possible to avoid yellowish side illumination in a liquid crystal display using an RM alignment layer.

The invention will be described more fully hereinafter with reference to the accompanying drawings, in which, FIG. The described embodiments may be modified in various different ways, all without departing from the spirit or scope of the invention.

Further, in the exemplary embodiments, since the same reference numerals indicate the same elements having the same structure, the first exemplary embodiment is representatively illustrated, and in other exemplary embodiments, only the first and the first Different configurations of the illustrative embodiments.

Accordingly, the drawings and description are to be regarded as Throughout the specification, the same reference symbols refer to the same elements.

Throughout the specification and the following claims, when an element is described as being "coupled" to another element, the element can be "directly coupled" to the other element or through the third element. Other components are "electrically coupled." In addition, the words "comprise" and variations thereof "comprises" and "comprising" are to be understood to include the recited elements, but do not exclude any Other components.

In the drawings, the thickness of layers, films, panels, regions, and the like are exaggerated for clarity. Throughout the specification, the same reference symbols refer to the same elements. It will be understood that when an element such as a layer, a film, a region or a substrate is referred to as being "on" another element, it may be directly on the other element or the intervening element. In contrast, when an element is referred to as being "directly on" another element, there is no intervening element.

Hereinafter, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram depicting a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display includes a signal controller 1100, a gate driver 1200, a data driver 1300, a gray scale voltage generator 1400, a liquid crystal panel assembly 1500, and a common voltage generator 1600.

The liquid crystal panel assembly 1500 includes a plurality of gate lines S1-Sn, a plurality of data lines D1-Dm, and a plurality of pixels PX. The plurality of pixels PX are coupled to the plurality of gate lines S1-Sn and the plurality of data lines D1-Dm, and are substantially arranged in a matrix form. The plurality of gate lines S1-Sn are substantially extended in the column direction to be substantially parallel to each other. The plurality of data lines D1-Dm are substantially extended in the row direction to be substantially parallel to each other. Here, it is depicted that only a plurality of gate lines S1-Sn and a plurality of data lines D1-Dm are connected to a plurality of pixels PX, but different signal lines such as a power line and a segment reference voltage line RL (see FIG. 2) It may be additionally connected to a plurality of pixels PX according to the structure or driving method of the pixel PX.

Meanwhile, on the rear surface of the liquid crystal panel assembly 1500, a backlight (not shown) that controls the brightness of the image displayed on the liquid crystal panel assembly 1500 can be provided. The backlight emits light to the liquid crystal panel assembly 1500.

The signal controller 1100 receives the image signals R, G, and B and inputs control signals. The image signals R, G, and B store brightness information of a plurality of pixels. The brightness has a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) gray scale. The input control signal includes a data enable signal DE, a horizontal sync signal Hsync, a vertical sync signal Vsync, and a main clock signal MCLK.

The signal controller 1100 generates a gate control signal CONT1, a data control signal CONT2, and image data signals DAT, data enable signals DE, horizontal synchronization signals Hsync, vertical synchronization signals Vsync and main clocks according to image signals R, G, and B. Signal MCLK. The signal controller 1100 can divide the image signals R, G, and B according to the frame unit according to the vertical synchronization signal Vsync, and divide the image signals R, G, and B according to the gate line unit according to the horizontal synchronization signal Hsync to generate the image data signal DAT.

When the signal controller 1100 generates the image data signal DAT, the signal controller 1100 can adjust the data voltage of the maximum gray level applied to the blue pixel by a predetermined level to generate the image data signal DAT. In this case, the data voltage having the largest gray scale applied to the red pixel and the green pixel is maintained locally, or the data voltage having the maximum gray level applied to the red pixel and the green pixel can be reduced by the predetermined level. The level of decrease of the data voltage with the largest gray level in response to the blue pixel. This will be described in the sixth to ninth drawings below.

The signal controller 1100 provides the image data signal DAT and the data control signal CONT2 to the data driver 1300. The data control signal CONT2, which is a signal for controlling the operation of the data driver 1300, includes a horizontal synchronization start signal for informing the transmission start of the image data signal DAT, a load signal for indicating the output of the data signal to the data lines D1-Dm, and a data clock signal. The data control signal CONT2 can further include a reverse signal for the common voltage Vcom to reverse the voltage polarity of the image data signal DAT.

The signal controller 1100 provides a gate control signal CONT1 to the gate driver 1200. The gate control signal CONT1 includes at least one clock signal to control the output of the scan start signal and the gate turn-on voltage from the gate driver 1200. The gate control signal CONT1 may further include an output enable signal to limit the duration of the gate turn-on voltage.

The gate driver 1200 applies a gate signal to a plurality of gate lines S1-Sn, respectively, and the gate signal is configured to open and close the gate connected to the liquid crystal panel assembly 1500 by combining the gate conduction voltage and the gate turn-off voltage. The first switching element Qa, the second switching element Qb, and the third switching element Qc of the line S1-Sn (see Fig. 2).

The data driver 1300 connects the data lines D1-Dm of the liquid crystal panel assembly 1500 and selects the gray scale voltage from the gray scale voltage generator 1400. The data driver 1300 applies the selected gray scale voltage to the data lines D1-Dm as the data voltage. The gray scale voltage generator 1400 may provide only a predetermined number of reference gray scale voltages without providing voltages for all gray scales. In the present case, the data driver 1300 can divide the reference gray scale voltage to generate gray scale voltages for all gray scales and select data voltages in the generated gray scale voltages.

The difference between the data voltage applied to the pixel PX and the common voltage Vcom is expressed as the charging voltage of the first liquid crystal capacitor Clca and the second liquid crystal capacitor Clcb (see FIG. 2), that is, the pixel voltage. The alignment of the liquid crystal molecules changes according to the amplitude of the pixel voltage, and as a result, the polarity of light passing through the liquid crystal layer 3 is changed (see Fig. 4). The change in polarity is expressed as a change in the transmittance of light by the polarizer, and as a result, the pixel PX displays the brightness represented by the gray scales of the image signals R, G, and B.

The gate signal of the gate turn-on voltage is sequentially applied to the plurality of gate lines S1-Sn by setting a horizontal interval of one unit, and the gate signal of the data voltage corresponding to the gate turn-on voltage is applied to the plurality of gate signals. Data line D1-Dm. As a result, a data voltage is applied to all of the pixels PX to display an image in one frame. The 1 horizontal interval is referred to as "1H" and is the same as the interval of the horizontal synchronization signal Hsync and the data enable signal DE.

When one frame ends, the state of the reverse signal (RVS) applied to the next frame and applied to the data driver 1300 is controlled such that the polarity of the data voltage applied to each pixel PX is relative to the polarity in the previous frame (" Frame reverse"). In this case, even in one frame, according to the characteristics of the reverse signal (RVS), the polarity of the data voltage applied to one data line is periodically changed (column inversion and dot inversion), or applied to one pixel. The polarity of the data voltages of the columns can be different from each other (row reverse and dot reverse).

The data voltage can be divided into a positive data voltage and a negative data voltage according to the polarity. The positive data voltage for the same gray level is greater than the negative data voltage.

The common voltage generator 1600 generates a common voltage Vcom to be supplied to the liquid crystal panel assembly 1500.

The foregoing signal controller 1100, the gate driver 1200, the data driver 1300, the gray scale voltage generator 1400, and the common voltage generator 1600 can be directly mounted on the liquid crystal panel assembly 1500 in the form of at least one IC wafer, and are mounted on The flexible printed circuit film (not shown) is attached to the liquid crystal panel assembly 1500 in the form of a tape wound wafer carrier package (TCP) or mounted on a separate printed circuit board (not shown). Optionally, the signal controller 1100, the gate driver 1200, the data driver 1300, the grayscale voltage generator 1400, and the common voltage generator 1600 can be integrated with the signal lines S1-Sn and the signal lines D1-Dm in the liquid crystal panel assembly. 1500.

FIG. 2 is a circuit diagram depicting one pixel in a liquid crystal display according to an exemplary embodiment of the present invention. A circuit structure of a pixel of a liquid crystal display according to an exemplary embodiment of the present invention and a driving method thereof will be described with reference to FIG.

One pixel PX included in the liquid crystal display includes a first sub-pixel PEa and a second sub-pixel PEb. The first sub-pixel PEa includes a first switching element Qa and a first liquid crystal capacitor Clca. The second sub-pixel PEb includes a second switching element Qb, a third switching element Qc, and a second liquid crystal capacitor Clcb.

The first switching element Qa and the second switching element Qb are both connected to the gate line Si and the data line Dj. The third switching element Qc is coupled to the gate line Si, the output terminal of the second switching element Qb, and the segment reference voltage line RL. The first switching element Qa and the second switching element Qb are thin film transistors, such as three-terminal elements, whose control terminals are connected to the gate line Si and the input terminals are connected to the data line Dj. The output terminal of the first switching element Qa is coupled to the first liquid crystal capacitor Clca. The output terminal of the second switching element Qb is coupled to the input terminals of the second liquid crystal capacitor Clcb and the third switching element Qc. The third switching element Qc is also a three-terminal element such as a thin film transistor, the control terminal is connected to the gate line Si, the input terminal is connected to the second liquid crystal capacitor Clcb, and the output terminal is connected to the segment reference voltage line. RL.

When the gate conduction signal is applied to the gate line Si, the first switching element Qa, the second switching element Qb, and the third switching element Qc connected to the gate line Si are turned on. In the present case, the data voltage is applied to the data line Dj, and the data voltage applied to the data line Dj is applied to the first sub-pixel electrode of the first sub-pixel PEa through the turned-on first switching element Qa, and is turned on The second switching element Qb is applied to the first sub-pixel electrode of the second sub-pixel PEb. Since the data voltages applied to the first sub-pixel electrode and the second sub-pixel electrode are identical to each other, the first liquid crystal capacitor Clca and the second liquid crystal capacitor Clcb are charged at the same value as the difference between the common voltage and the data voltage, but at the same time The voltage charged in the second liquid crystal capacitor Clcb is divided by the turned-on third switching element Qc. Therefore, the voltage charged in the second liquid crystal capacitor Clcb is reduced by the difference between the common voltage and the segment reference voltage.

The pixel voltage of the second sub-pixel PEb is smaller than the pixel voltage of the first sub-pixel PEa. The first sub-pixel PEa including the first sub-pixel electrode may be referred to as a high pixel, and the second sub-pixel PEb including the second sub-pixel electrode may be referred to as a low pixel.

Since the voltage charged in the first liquid crystal capacitor Clca and the voltage charged in the second liquid crystal capacitor Clcb are different from each other, the tilt angles of the liquid crystal molecules in the first sub-pixel and the second sub-pixel are different from each other, and as a result, The luminances of the two sub-pixels are different from each other. When the voltage of the first liquid crystal capacitor Clca and the voltage of the second liquid crystal capacitor Clcb are appropriately controlled, the image seen from the side can maximize the image seen from the front side, thereby improving the side visibility.

Here, the circuit of the pixel as depicted in FIG. 2 is described, but the pixels of the display device according to the exemplary embodiment of the present invention are not limited thereto, and may be of various different configurations.

Hereinafter, the structure of the liquid crystal panel assembly 1500 of the liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3 to 5.

FIG. 3 is a plan view depicting one pixel in a liquid crystal display according to an exemplary embodiment of the present invention. Fig. 4 is a cross-sectional view taken along line IV-IV of Fig. 3. Fig. 5 is a plan view showing a basic area of a pixel electrode in a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIGS. 3 to 5, the liquid crystal display includes the panel 100 and the upper panel 200 opposed to each other, and the liquid crystal layer 3 including the liquid crystal molecules 31 interposed between the lower panel 100 and the upper panel 200. A pair of polarizers, a first polarizer POL1 and a second polarizer POL2, are attached to the outer surfaces of the two panels of the lower panel 100 and the upper panel 200.

First, the lower panel 100 will be described.

A gate conductor including the gate line 121 and the segment reference voltage line 131 is formed on the first insulating substrate 110. The gate line 121 includes a first gate electrode 124a, a second gate electrode 124b, a third gate electrode 124c, and a wide end portion (not shown) to be coupled to other layers or an external driving circuit. The segmented reference voltage line 131 includes first storage electrodes 135 and 136 and a reference electrode 137. The second storage electrodes 138 and 139 that are not connected to the segment reference voltage line 131 but overlap the second sub-pixel electrode 191b are provided.

The gate insulating layer 140 is disposed on the gate line 121 and the segment reference voltage 131, and the first semiconductor layer 154a, the second semiconductor layer 154b, and the third semiconductor layer 154c are disposed on the gate insulating layer 140. A plurality of ohmic junctions 163a, 165a, 163b, 165b, 163c, and 165c may be disposed on the first semiconductor layer 154a, the second semiconductor layer 154b, and the third semiconductor layer 154c.

A plurality of data lines 171 including a first source electrode 173a and a second source electrode 173b, a first drain electrode 175a, a second drain electrode 175b, a third source electrode 173c, and a third drain electrode 175c are included. The data conductors are disposed on the ohmic junctions 163a, 165a, 163b, 165b, 163c, and 165c and the gate insulating layer 140. The data conductor, the semiconductor disposed under the data conductor, and the ohmic junction can be simultaneously formed by using a mask. The data line 171 includes a wide end portion to be coupled to other layers or an external driving circuit, and may include a first semiconductor layer 154a, a second semiconductor layer 154b and a third semiconductor layer 154c, and ohmic junctions 163a, 165a having the same planar shape. 163b, 165b, 163c, and 165c.

The first gate electrode 124a, the first source electrode 173a, and the first drain electrode 175a form a first thin film transistor, a first switching element Qa, together with the first semiconductor layer 154a. A channel of the first thin film transistor is formed on the first semiconductor layer 154a between the first source electrode 173a and the first drain electrode 175a.

Similarly, the second gate electrode 124b, the second source electrode 173b, and the second drain electrode 175b together with the second semiconductor layer 154b form a second thin film transistor, and a second switching element Qb. A channel of the second thin film transistor is formed on the second semiconductor layer 154b and between the second source electrode 173b and the second drain electrode 175b.

The third gate electrode 124c, the third source electrode 173c, and the third drain electrode 175c form a third thin film transistor and a third switching element Qc together with the third semiconductor layer 154c. A channel of the third thin film transistor is formed on the third semiconductor layer 154c and between the third source electrode 173c and the third drain electrode 175c. The second drain electrode 175b is coupled to the third source electrode 173c and includes a widely extending extension portion 177.

The first passivation layer 180p is disposed on the data line 171, the third source electrode 173c, the first drain electrode 175a, the second drain electrode 175b, and the third drain electrode 175c of the data conductor, and the first semiconductor layer 154a On the exposed portions of the second semiconductor layer 154b and the third semiconductor layer 154c. The first passivation layer 180p may include an inorganic insulating layer such as tantalum nitride or hafnium oxide. The first passivation layer 180p prevents the pigment of the color filter 230 from flowing into the exposed portions of the first semiconductor layer 154a, the second semiconductor layer 154b, and the third semiconductor layer 154c.

The vertical light blocking member 220a and the color filter 230 are disposed on the first passivation layer 180p. Any of the vertical shading elements 220a and the color filters 230 may also be provided first. The vertical light blocking member 220a may have the same or similar planar shape as the data line 171 and is formed to cover the data line 171.

Here, the vertically extending vertical light blocking element 220a is described, but the present invention is not limited thereto, and a shield electrode formed simultaneously with the pixel electrode and receiving a common voltage may also be applied.

The color filter 230 extends along two adjacent data lines 171 in the vertical direction. The two color filters 230 adjacent to each other may be separated from each other based on the data line 171 or overlap each other in a region adjacent to the data line 171.

The color filter 230 may specifically display one primary color, and examples of the primary colors may include three primary colors of red, green, and blue or three primary colors of yellow, cyan, and magenta. Although not depicted, the color filter 230 may further include a color filter that displays a mixed color of primary colors or white other than the primary colors.

The second passivation layer 180q is disposed on the vertical light blocking element 220a and the color filter 230. The second passivation layer 180q may include an inorganic insulating layer such as tantalum nitride or hafnium oxide. The passivation layer 180q can prevent the color filter 230 from being lifted and suppress the contamination of the liquid crystal layer 3 due to the organic material such as the solvent flowing from the color filter 230, thereby avoiding the defect of the afterimage which may be caused when the screen is driven.

In the first passivation layer 180p, the color filter 230, and the second passivation layer 180q, a first contact hole 185a exposing the first drain electrode 175a and a second contact hole 185b exposing the second drain electrode 175b are disposed. In the first passivation layer 180p, the second passivation layer 180q, and the gate insulating layer 140, a third contact hole 185c exposing a portion of the reference electrode 137 and a portion of the third drain electrode 175c is formed. The third contact hole 185c is covered by the joint member 195. The connecting member 195 electrically connects the reference electrode 137 and the third drain electrode 175c exposed by the third contact hole 185c.

A plurality of pixel electrodes 191 are disposed on the second passivation layer 180q. Each of the pixel electrodes 191 includes a first sub-pixel electrode 191a and a second sub-pixel electrode 191b which are separated from each other with the gate line 121 therebetween, and are adjacent to each other in the row direction based on the gate line 121. The pixel electrode 191 may be made of a transparent conductive material such as ITO or IZO, or may be composed of a reflective metal such as aluminum, silver, chromium or an alloy thereof.

Each of the first sub-pixel electrode 191a and the second sub-pixel electrode 191b includes a basic region of the pixel electrode 191 depicted in FIG. 5 or one or more modifications thereof. The first sub-pixel electrode 191a is physically and electrically coupled to the first drain electrode 175a through the first contact hole 185a, and receives a data voltage from the first drain electrode 175a. The second sub-pixel electrode 191b is physically and electrically coupled to the second drain electrode 175b through the second contact hole 185b, and receives a data voltage from the second drain electrode 175b. The data voltage applied to a portion of the second drain electrode 175b is separated by the third source electrode 173c, and as a result, the magnitude of the voltage applied to the first subpixel electrode 191a is higher than the voltage applied to the second subpixel electrode 191b. The magnitude is still large.

The first sub-pixel electrode 191a and the second sub-pixel electrode 191b to which the data voltage is applied generate an electric field together with the common electrode 270 of the upper panel 200 to determine the liquid crystal layer 3 between the pixel electrode 191 and the two electrodes of the common electrode 270. The direction of the liquid crystal molecules. The brightness of the light passing through the liquid crystal layer 3 changes in accordance with the direction of the liquid crystal molecules determined as described above.

The lower alignment layer 11 is formed on the pixel electrode 191.

Next, the upper panel 200 will be described.

The horizontal light blocking member 220b is disposed on the second insulating substrate 210. The horizontal shading element 220b is referred to as a black matrix (BM) and blocks light leakage. The horizontal shading element 220b may be disposed in a region corresponding to the gate line 121. That is, the horizontal shading member 220b extending in the column direction can be provided.

The second polarizer POL2 is disposed under the second insulating substrate 210, that is, on the opposite side of the horizontal light blocking member 220b.

An overcoat 250 is formed on the horizontal shading element 220b. The cover layer 250 may be made of an organic insulating material and provide a flat surface. According to an exemplary embodiment, the cover layer 250 may be omitted.

The common electrode 270 is formed on the cover layer 250. The common electrode 270 can be made of a transparent conductor such as ITO and IZO.

The upper alignment layer 21 is formed on the common electrode 270.

The lower alignment layer 11 and the upper alignment layer 21 are reactive liquid crystal (RM) alignment layers. The lower alignment layer 11 and the upper alignment layer 21 may be vertical alignment layers. However, in the present invention, the lower alignment layer 11 and the upper alignment layer 21 may be defined as RM alignment layers. Since the RM alignment layer has low anchoring energy, the transmittance of the RM alignment layer can be increased by about 5% compared to the vertical alignment layer.

The liquid crystal layer 3 includes a plurality of liquid crystal molecules 31, and when a voltage is not applied to the pixel electrode 191 and the common electrode 270 of the two field generating electrodes, the liquid crystal molecules 31 may be arranged to have the same longitudinal direction as the slit pattern of the pixel electrode 191. The pretilt angle of the direction is inclined.

As depicted in FIG. 5, the overall shape of the pixel electrode 191 is quadrangular and includes a cross trunk disposed with a horizontal stem 193 and a vertical stem 192 perpendicular to the horizontal stem 193. The pixel electrode 191 is divided into a first region Da, a second region Db, a third region Dc, and a fourth region Dd by the horizontal stem 193 and the vertical stem 192. The first area Da, the second area Db, the third area Dc, and the fourth area Dd respectively include a plurality of first minute branches 194a, a plurality of second minute branches 194b, a plurality of third minute branches 194c, and a plurality of fourth tiny Branch 194d.

The first minute branch 194a extends obliquely from the horizontal stem 193 or the vertical stem 192 to the upper left direction, and the second minute branch 194b extends obliquely from the horizontal stem 193 or the vertical stem 192 to the upper right direction. Further, the third minute branch 194c extends obliquely from the horizontal stem 193 or the vertical stem 192 to the lower left direction, and the fourth minute branch 194d extends obliquely from the horizontal stem 193 or the vertical stem 192 to the lower right direction.

The first minute branch 194a, the second minute branch 194b, the third minute branch 194c, and the fourth minute branch 194d may form an angle of about 45 or 135 with the gate line 121 or the horizontal stem 193. Further, the first minute branch 194a, the second minute branch 194b, the third minute branch 194c, and the fourth minute branch 194d of the two adjacent first region Da, second region Db, third region Dc, and fourth region Dd They can be perpendicular to each other.

The width of the first minute branch 194a, the second minute branch 194b, the third minute branch 194c, and the fourth minute branch 194d may be about 2.5 mm to about 5.0 mm, and in a first area Da, a second area Db, and a third The distance between the adjacent first minute branch 194a, the second minute branch 194b, the third minute branch 194c, and the fourth minute branch 194d in the region Dc or the fourth region Dd may be about 2.5 mm to about 5.0 mm.

According to other exemplary embodiments of the present invention, the widths of the first minute branch 194a, the second minute branch 194b, the third minute branch 194c, and the fourth minute branch 194d may increase toward the horizontal trunk 193 or the vertical trunk 192, and the first minute The difference between the maximum width portion and the minimum width portion of one of the branch 194a, the second minute branch 194b, the third minute branch 194c, and the fourth minute branch 194d may be 0.2 mm to 1.5 mm.

Hereinafter, the process of tuning the color coordinates of the liquid crystal display using the RM alignment layer according to the present invention will be described with reference to FIGS. 6 and 7.

FIG. 6 is a flow chart depicting a process of tuning color coordinates in a liquid crystal display, in accordance with an illustrative embodiment of the present invention. Figure 7 is a graph depicting the Y/y value versus data voltage in a liquid crystal display using the RM alignment layer.

An example of configuring a plurality of pixels included in the liquid crystal panel assembly 1500 by red pixels, green pixels, and blue pixels will be described with reference to FIGS. 6 and 7.

The invariant interval of Yb/yb of the blue pixel is confirmed (T110) before the color coordinates of the liquid crystal display are tuned.

In general, the y coordinate of the color coordinates can be expressed as Equation 1.

(Equation 1)

Here, X, Y, and Z represent triple excitation values, Yr represents red luminance, Yg represents green luminance, Yb represents blue luminance, yr represents red y coordinates, yg represents green y coordinates, and yb represents blue Colored y coordinates. Yr/yr represents the ratio of the luminance Yr of red to the y coordinate of red, Yg/yg represents the ratio of the luminance Yg of green to the y coordinate of green, and Yb/yb represents the ratio of the luminance Yb of blue to the y coordinate of blue. . Since a plurality of pixels included in the liquid crystal panel assembly 1500 are arranged by red pixels, green pixels, and blue pixels, Yr/yr, Yg/yg, and Yb/yb correspond to red pixels, green pixels, and blue pixels, respectively.

Changes in Yr/yr, Yg/yg, and Yb/yb relative to the data voltage applied to the plurality of pixels can be measured. Fig. 7 is a graph showing changes in Yr/yr, Yg/yg, and Yb/yb when the data voltage is changed from the data voltage V235 of 235 gray scale to the data voltage V256 of 256 gray scale in the liquid crystal display of 256 gray scale.

Referring to Fig. 7, it can be seen that the Yr/yr value of the red pixel and the Yg/yg value of the green pixel change almost uniformly when the data voltage is changed. At the same time, it can be seen that when the data voltage is changed between the data voltage V250 of 250 gray scale and the data voltage V256 of 256 gray scale, the Yb/yb value of the blue pixel hardly changes. The section in which the Yb/yb value of the blue pixel does not change is referred to as the Yb/yb constant interval NC of the blue pixel. It can be seen that the Yb/yb value of the blue pixel is changed in the interval when the data voltage is lower than the data voltage V250 of the 250th gray scale. The section in which the Yb/yb value of the blue pixel is changed is referred to as the Yb/yb variable section AC of the blue pixel.

The Yb/yb constant interval NC of the blue pixel means an interval in which the luminance of the blue color hardly changes even if the blue y coordinate is adjusted. When the color coordinates are tuned under the negligence of the Yb/yb constant interval NC of the blue pixel, the data voltage and the y coordinate of the maximum gray scale applied to the blue pixel are adjusted during the tuning of the color coordinates. In the Yb/yb constant interval NC of the blue pixel, the luminance of blue hardly changes, and therefore, the y coordinate may be excessively adjusted. In this case, after tuning the color coordinates, the amount of change in the y-coordinate of the side color coordinates is generated in the interval when the color change is rapidly changed. As an example, Figure 8 is illustrated.

Fig. 8 depicts a graph according to the amount of change in the side color coordinates of the gray scale when the data voltage of the blue pixel having the largest gray scale is not adjusted.

Referring to Fig. 8, the amount of change Δx (SVA) and Δy (SVA) of the side color coordinates of the liquid crystal display using the vertical alignment layer are all lower than 0.015 depending on the gray scale and are not changed rapidly. In other words, the amount of change Δy (RM alignment layer) of the side color coordinates of the liquid crystal display using the RM alignment layer is generated according to the interval when the gray scale approaches 0.02 and changes rapidly. Therefore, the change amount Δy of the y coordinate of the side color coordinate is changed by the rapidly changing section so that the yellowish side light is seen. The yellowish side luminescence occurs at approximately 250 gray levels or more.

When the color coordinates are tuned under the negligence of the Yb/yb constant interval NC of the blue pixel, the gamma curves (RM alignment layers) of red, green, and blue are measured and depicted in FIG.

Fig. 9 is a graph depicting a gamma curve when the data voltage of the blue pixel having the largest gray scale is not adjusted. Referring to Fig. 9, the interval in which the luminance B of the blue color rapidly decreases can be verified as compared with the luminance R of the red color and the luminance G of the green color. When the luminance B of blue is rapidly decreased, the yellowish side luminescence can be expressed.

Referring back to FIGS. 6 and 7, the interval in which the yellowish side light is seen corresponds to the Yb/yb constant interval NC of the blue pixel. In order to avoid the yellowish side light emission, the data voltage V256 having the largest gray scale (256 gray scale) is adjusted to the high voltage of the Yb/yb variable section AC of the blue pixel (S120). That is, the data voltage V256 having a gray scale of 256 for the blue pixel is adjusted to the data voltage V250 of 250 gray scale.

Therefore, the data voltage with the largest gray level can be adjusted by reducing the predetermined level. Preferably, the data voltage with the largest gray level is adjusted to the high voltage of the Yb/yb variable interval AC of the blue pixel, but the difference is that the data voltage with the largest gray level can also be obtained by the blue pixel. The high voltage of the Yb/yb variable interval AC is further reduced or increased by a predetermined level to be adjusted.

Meanwhile, by adjusting the data voltage V256 having the maximum gray scale (256 gray scale) to the high voltage of the Yb/yb variable interval AC of the blue pixel, only the data voltage having the largest gray scale for the blue pixel can be Adjusted to the high voltage of the Yb/yb variable interval AC of the blue pixel. Further, in addition to the blue pixels, the data voltage having the largest gray scale for the red pixel and the green pixel may be adjusted to the high voltage of the Yb/yb variable interval AC of the blue pixel.

The color coordinate tuning is performed by applying the adjusted data voltage V250 to the blue pixel and adjusting the y coordinate (S130). In the Yb/yb variable interval AC of the blue pixel, since the brightness of the blue color is changed by adjusting the y coordinate of the blue color, the interval in which the brightness of the blue color is rapidly decreased does not occur, and the yellowish side light emission can be Was avoided.

Table 1 illustrates an example in which the data voltage of the maximum gray scale applied to the blue pixel is not changed in the liquid crystal display using the RM alignment layer (Example A), and the maximum gray scale applied to the blue pixel therein The data voltage is changed to the high voltage of the Yb/yb variable section AC as described above (example B), and in the example of the liquid crystal display using the vertical alignment layer (example C), by measuring the color coordinates before The result of the x value and the y value and the amount of change in the side coordinates.

(Table 1)

It can be seen that compared to the example in which the data voltage of the maximum gray scale applied to the blue pixel is not changed (example A), the amount of change of the side color coordinate is applied to the data of the blue pixel having the largest gray scale. The example in which the voltage is changed to the high voltage of the Yb/yb variable section AC (example B) is reduced. This is similar to the example of a liquid crystal display using a vertical alignment layer in which the yellowish side illumination is not seen (example C). Therefore, the side color coordinates of the liquid crystal display using the vertical alignment layer can have an effect of increasing the transmittance of the RM alignment layer while maintaining the side color coordinates similar to those of the liquid crystal display using the vertical alignment layer.

Although the present invention has been described in connection with what is presently considered as an exemplary embodiment, it is understood that the invention is not limited to the disclosed embodiments, but rather, Various modifications and equivalent arrangements within the scope and spirit of the patent scope.

11‧‧‧Under the alignment layer
100‧‧‧lower panel
110‧‧‧First insulating substrate
1100‧‧‧Signal Controller
124a‧‧‧first gate electrode
124b‧‧‧second gate electrode
124c‧‧‧third gate electrode
1200‧‧ ‧ gate driver
131‧‧‧Segmented reference voltage line
135, 136‧‧‧ first storage electrode
137‧‧‧ reference electrode
138, 139‧‧‧ second storage electrode
1300‧‧‧Data Drive
140‧‧‧ gate insulation
1400‧‧‧ gray scale voltage generator
154a‧‧‧First semiconductor layer
154b‧‧‧second semiconductor layer
154c‧‧‧ third semiconductor layer
1500‧‧‧LCD panel components
163a, 165a, 163b, 165b, 163c, 165c‧ ‧ ohm junction
1600‧‧‧Common voltage generator
173a‧‧‧first source electrode
173b‧‧‧second source electrode
173c‧‧‧ third source electrode
175a‧‧‧First bungee electrode
175b‧‧‧second pole electrode
175c‧‧‧third electrode
177‧‧‧Extension
180p‧‧‧first passivation layer
180q‧‧‧second passivation layer
185a‧‧‧first contact hole
185b‧‧‧second contact hole
185c‧‧‧ third contact hole
191‧‧‧pixel electrode
191a‧‧‧First sub-pixel electrode
191b‧‧‧Second sub-pixel electrode
192‧‧‧Vertical trunk
193‧‧‧ horizontal backbone
194a‧‧‧The first tiny branch
194b‧‧‧Second tiny branch
194c‧‧‧The third tiny branch
194d‧‧‧The fourth tiny branch
195‧‧‧Connecting components
21‧‧‧Upward alignment layer
200‧‧‧Upper panel
210‧‧‧Second insulating substrate
220a‧‧‧ vertical shading elements
220b‧‧‧ horizontal shading elements
230‧‧‧ color filter
250‧‧‧ Coverage
270‧‧‧Common electrode
3‧‧‧Liquid layer
31‧‧‧ liquid crystal molecules
AC‧‧‧Yb/yb variable interval
R, G, B‧‧‧ video signals
Clca‧‧‧First Liquid Crystal Capacitor
Clcb‧‧‧Second liquid crystal capacitor
CONT1‧‧‧ gate control signal
CONT2‧‧‧ data control signal
D1-Dm, Dj, 171‧‧‧ data lines
Da‧‧‧First Area
Db‧‧‧Second area
Dc‧‧‧ third area
Dd‧‧‧ fourth area
DAT‧‧‧ image data signal
DE‧‧‧Data enable signal
Hsync‧‧‧ horizontal sync signal
MCLK‧‧‧ main clock signal
NC‧‧‧Yb/yb constant interval
PEa‧‧‧ first subpixel
PEb‧‧‧ second sub-pixel
POL1‧‧‧first polarizer
POL2‧‧‧second polarizer
PX‧‧ ‧ pixels
Qa‧‧‧First switching element
Qb‧‧‧Second switching element
Qc‧‧‧third switching element
RL‧‧‧section reference voltage line
S1-Sn, Si, 121‧‧‧ gate line
Vcom‧‧‧share voltage
Vsync‧‧‧ vertical sync signal
S110, S120, S130‧‧‧ steps

A more complete evaluation of the present invention and many of its attendant advantages will become apparent from the Detailed Description of the Drawings ,among them:

FIG. 1 is a block diagram depicting a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram depicting one pixel in a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 3 is a plan view depicting one pixel in a liquid crystal display according to an exemplary embodiment of the present invention.

Fig. 4 is a cross-sectional view taken along line IV-IV of Fig. 3.

Fig. 5 is a plan view showing a basic area of a pixel electrode in a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 6 is a flow chart depicting a process of tuning color coordinates in a liquid crystal display, in accordance with an illustrative embodiment of the present invention.

Figure 7 depicts a plot of Y/y values versus data voltage in a liquid crystal display using the RM alignment layer.

Fig. 8 depicts a graph according to the amount of change in the color coordinates of the gray scale when the data voltage of the blue pixel having the largest gray scale is not adjusted.

Figure 9 depicts a graph of the gamma curve when the data voltage of the blue pixel with the largest gray level is not adjusted.

S110, S120, S130‧‧‧ steps

Claims (10)

A liquid crystal display comprising: a liquid crystal panel assembly comprising a plurality of pixels; a data driver applying a data voltage to a plurality of data lines coupled to the plurality of pixels; and a signal controller for generating an image Data signal to provide the generated image data signal to the data driver, and the plurality of pixels comprise at least one reactive liquid crystal (RM) alignment layer formed on a display panel, the signal controller is configured according to a predetermined The adjustment is such that the data voltage applied to a blue pixel having a maximum gray level is decreased to generate the image data signal. The liquid crystal display of claim 1, wherein the signal controller generates the image data signal such that when the ratio of the blue luminance to the y coordinate of the blue color coordinate is changed, the blue pixel is applied to the blue pixel. The data voltage with the largest gray level is adjusted to a high voltage in a variable interval. The liquid crystal display according to claim 2, wherein the signal controller generates the image data signal, so that the data voltage applied to the red pixel and the green pixel having the maximum gray level is maintained at the original data voltage. . The liquid crystal display of claim 2, wherein the signal controller generates the image data signal such that the data voltage applied to the red pixel with the maximum gray level is adjusted to be high in the variable interval. Voltage. The liquid crystal display of claim 2, wherein the signal controller generates the image data signal such that the data voltage applied to the green pixel having the maximum gray level is adjusted to be high in the variable interval. Voltage. The liquid crystal display of claim 2, wherein the maximum gray scale is 256 gray scales, and the variable interval is 250 gray scales or less. The liquid crystal display of claim 6, wherein the signal controller generates the image data signal, so that the data voltage applied to the blue pixel having the maximum gray level is adjusted to be the height of 250 gray scales. Voltage. The liquid crystal display of claim 1, wherein each of the plurality of pixels comprises a pixel electrode to which the data voltage is applied and a common electrode to which a common voltage is applied to form an electric field with the pixel electrode, And the pixel electrode comprises a cross trunk including a horizontal trunk and a vertical trunk and a micro branch extending obliquely from the horizontal trunk or the vertical trunk. The liquid crystal display of claim 8, wherein the pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode. The liquid crystal display of claim 9, wherein when the data voltage is applied to one pixel, a voltage amplitude applied to the first sub-pixel electrode and a voltage amplitude applied to the second sub-pixel electrode are mutually different.