TW201624701A - HEMT compatible lateral rectifier structure - Google Patents

Abstract

The present disclosure is directed to a high electron mobility transistor compatible power lateral field effect rectifier (L-FER) device, in some embodiments, the rectifier device has an electron supply layer that is tethered over the layer of semiconductor material and Between the anode terminal and the cathode terminal. The doped III-N semiconductor material layer is above the electron supply layer. The passivation layer is tied over the electron supply layer and the doped III-N semiconductor material layer. The gate structure is tied above the doped III-N semiconductor material layer and the passivation layer. The doped III-N semiconductor material layer adjusts the threshold voltage of the rectifier device. Due to the high temperature reverse bias (HTRB) stress, the passivation layer improves the reliability of the L-FER device by mitigating current degradation.

Description

HEMT compatible lateral rectifier structure

This disclosure relates to HEMT compatible lateral rectifier structures.

A power semiconductor device is a semiconductor device that is switched or rectified in a power electronic device (eg, a power converter). Power semiconductor devices (eg, power diodes, thyristors, power MOSFETs, etc.) are used to handle larger currents and support larger reverse bias than low power MOSFET devices.

Conventional power semiconductor devices are formed using germanium. However, in recent years, the semiconductor industry has waged many efforts to develop gallium nitride (GaN)-based power devices. Compared to conventional 矽-based power devices, GaN-based power devices are characterized by, for example, lower on-resistance and the ability to perform high frequency operation.

Some embodiments of the present disclosure provide a high electron mobility transistor (HEMT) compatible power lateral field effect rectifier (L-FER) device including a layer of semiconductor material that is tethered over a substrate; an electron supply layer Relying above the layer of semiconductor material between the anode termination and the cathode termination; a layer of doped III-N (III-nitride) semiconductor material that is above the electron supply layer; a passivation layer Causing the electron supply layer and the doped III-N semiconductor material layer; and a gate structure vertically above the doped III-N semiconductor material layer and the passivation layer.

Some embodiments of the present disclosure provide a lateral field effect rectifier (L- FER) device comprising a layer of semiconductor material over a substrate; an electron supply layer positioned above the layer of semiconductor material and disposed laterally between the anode termination and the cathode termination; doped III-N (III a nitride-based semiconductor material layer that is tethered over the electron supply layer; a nitride-based passivation layer that is tied to the doped III-N semiconductor material layer and the electron supply layer and in direct contact a layer of the doped III-N semiconductor material and the electron supply layer; a gate isolation material layer positioned above the passivation layer and on the III-N semiconductor material layer; and a gate structure Located above the gate isolation material layer.

Some embodiments of the present disclosure provide a method for forming a lateral field effect rectifier (L-FER) device, comprising providing a substrate having an epitaxial heterojunction between a layer of semiconductor material and an electron supply layer; forming An anode termination and a cathode termination comprising an ohmic contact region on opposite ends of the electron supply layer; selectively forming a doped III-N (III-nitride) semiconductor material layer on the electron supply layer; A passivation layer is formed over the electron supply layer and the doped III-N semiconductor material layer; and a gate structure is formed on the doped III-N semiconductor material layer.

100‧‧‧L-FER device

102‧‧‧Substrate

104‧‧‧Semiconductor material layer

105‧‧‧Two-dimensional electronic gas (2-DEG)

106‧‧‧Electronic supply layer

108‧‧‧Anode terminal

110‧‧‧cathode terminal

112‧‧‧Insulation layer

114‧‧‧Doped III-N semiconductor material layer

116‧‧‧ gate isolation material layer

118‧‧‧ gate structure

120‧‧‧Dielectric materials

122‧‧‧Metal interconnect layer

300‧‧‧ wafer

302‧‧‧L-FER

304‧‧‧Normally broken HEMT

306‧‧‧Source terminal

308‧‧‧Bungy terminal

310‧‧‧ gate structure

400‧‧‧HEMT compatible L-FER device

402‧‧‧ Passivation layer

404‧‧‧ gate structure

500‧‧‧HEMT compatible L-FER device

502‧‧‧Doped III-N semiconductor materials

504‧‧‧ Passivation layer

114a‧‧‧First GaN layer

114b‧‧‧Second GaN layer

1002‧‧‧ mask layer

1004‧‧‧ openings

1006‧‧‧ etchant

1 is a cross-sectional view showing some embodiments of a High Electron Mobility Transistor (HEMT) compatible lateral field effect rectifier (LFER) device.

2 is a diagram illustrating the performance parameters of the disclosed HEMT compatible gallium nitride (GaN) rectifier device.

3 is a cross-sectional view showing some embodiments of an integrated wafer including the disclosed L-FER integrated with a normally-off HEMT.

4 is a cross-sectional view showing some embodiments of a HEMT compatible L-FER device having a passivation layer.

Figure 5 is a cross-sectional view showing still another embodiment of a HEMT compatible L-FER device having a passivation layer.

6 is a flow chart illustrating some embodiments of a method of forming a HEMT compatible L-FER device.

7 through 13b are cross-sectional views illustrating some embodiments of an exemplary structure for performing a HEMT compatible lateral field effect rectifier (L-FER).

The description of the present disclosure is to be understood by reference to the claims In the following description, for the purposes of explanation, numerous specific details are illustrated in the description. However, it will be apparent to those skilled in the art that the implementation of one or more aspects described herein requires only a certain degree of detail. In other instances, known structures and devices are shown in block diagram form for ease of understanding.

In recent years, gallium nitride (GaN) transistors have effectively replaced germanium-based transistors for many high power applications (eg, power switching). A GaN transistor having an aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterostructure has many performance advantages over conventional germanium devices. For example, GaN semiconductors can provide lower on-resistance and higher switching frequency than conventional germanium power devices.

Efforts have been made to provide a two-terminal GaN power rectifier with excellent performance (eg, high reverse breakdown voltage, low forward turn-on voltage, and low specific on-resistance) that is compatible with GaN HEMTs (High Electron Mobility Transistors). However, such efforts have mostly failed. For example, a Schottky barrier diode and a pin diode exhibit high breakdown voltage and low on-resistance characteristics on doped bulk GaN, but Schottky barrier diodes and pins The epitaxial structure of the diode cannot be compatible with the epitaxial structure of the GaN HEMT without significant performance loss (eg, higher turn-on voltage and on-resistance). Alternatively, the HEMT compatible power rectifier has a poor turn-off leakage, which is limited by the Schottky contact reverse biasing leakage current.

Accordingly, the present disclosure is directed to a high electron mobility transistor (HEMT) compatible lateral field effect rectifying device that provides high reverse breakdown voltage and low gate leakage. In some embodiments, the fairing includes an electron supply layer positioned above the layer of semiconductor material between the anode termination and the cathode termination. The doped III-N semiconductor material layer is above the electron supply layer. The gate isolation material layer is above the doped III-N semiconductor material layer. The gate structure is positioned above the gate isolation material, thereby separating the gate structure and the electron supply layer by the gate isolation material layer and the doped III-N semiconductor material layer. The doped III-N semiconductor material layer adjusts the threshold voltage of the rectifying device, while the gate isolation material layer provides a barrier that provides low leakage and high reverse breakdown voltage to the rectifying device.

1 is a cross-sectional view showing some embodiments of a High Electron Mobility Transistor (HEMT) compatible lateral field effect rectifier (LFER) device.

The L-FER device 100 includes a layer of semiconductor material 104 positioned over a substrate 102 (eg, a sapphire substrate, a germanium substrate, a tantalum carbide substrate, etc.). In some embodiments, the semiconductor material layer 104 can comprise a III-V semiconductor material or a III-nitride (III-N) semiconductor material. For example, in some embodiments in which the L-FER device 100 includes a gallium nitride rectifier device, the semiconductor material layer 104 can include a gallium nitride (GaN) layer (eg, having unintentional doping with doping from process contamination). GaN layer).

The electron supply layer 106 is positioned over the layer of semiconductor material 104 that extends between the anode and cathode terminations 108 and 110 and includes an ohmic contact region over the layer of semiconductor material 104, respectively. The energy band gap of the material of the electron supply layer 106 is not equal to (e.g., greater than) the energy band gap of the underlying semiconductor material layer 104, and thus the location of the heterojunction of the channel region of the HEMT compatible L-FER device 100 is along The interface of the semiconductor material layer 104 with the electron supply layer 106. During operation, the heterojunction causes the electron supply layer 106 to supply a charge carrier to a two-dimensional electron gas (2-DEG) 105 formed along the interface. The 2-DEG 105 has high mobility electrons that can be at the anode termination 108 The cathode terminals 110 are free to move between them. In some embodiments, the electron supply layer 106 comprises aluminum gallium nitride (AlGaN). in In some embodiments, the AlGaN film can be deliberately doped with doping to provide a carrier to the 2-DEG 105.

The layer of insulating material 112 can be positioned over the anode termination 108, the cathode termination 110, and the electron supply layer 106. For example, in some embodiments, the insulating material layer 112 can include tantalum nitride (Si ₃ N ₄ ). In some embodiments, the insulating material layer 112 can be on the anode termination 108, the cathode termination 110, and a portion of the electron supply layer 106 and directly contacts the anode termination 108, the cathode termination 110, and a portion of the electron supply layer 106.

The doped III-N semiconductor material layer 114 is tied over the electron supply layer 106. The doped III-N semiconductor material layer 114 is laterally spaced from the cathode termination 110 by an offset length L _D . In various embodiments, the doped III-N semiconductor material layer 114 can include p-type doping and/or n-type doping. In some embodiments, the doped III-N semiconductor material layer 114 is laterally located between the insulating material layer 112 and the anode termination 108. The doped III-N semiconductor material layer includes gallium nitride (GaN). In some embodiments, GaN can include a GaN underlayer having a first doped pattern (eg, p-type doping) and a GaN top layer positioned over the GaN underlayer and having a second doping different from the first doped pattern Type (for example, n-type doping).

A gate isolation material layer 116 is positioned over the doped III-N semiconductor material layer 114. For example, in some embodiments, the gate isolation material layer 116 may include hafnium oxide (SiO ₂ ), hafnium nitride (Si ₃ N ₄ ), gallium oxide (Ga ₂ O ₃ ), aluminum oxide (Al ₂ O _{3 )} ), cerium oxide (Sc ₂ O ₃ ), cerium oxide (HfO ₂ ), or aluminum nitride (AlN). In various embodiments, the gate spacer material layer 116 can have a thickness in the range of from about 15 angstroms (Åstroms) to about 30 angstroms. In some embodiments, the gate isolation material layer 116 can also be positioned over the insulating material layer 112. The gate isolation material layer suppresses gate leakage current, thereby improving gate stability, and provides a low turn-on voltage, low on-resistance, and high breakdown reverse voltage to the L-FER device 100.

The gate structure 118 is positioned above the gate isolation material 116 above the doped III-N semiconductor material layer 114, such that the gate isolation material layer 116 isolates the gate structure 118 from the underlying doped III-N Semiconductor material 114. In some embodiments, the gate Structure 118 can include a metal gate structure. For example, the gate structure 118 may include one or more of titanium (Ti), nickel (Ni), aluminum (Al), aluminum nickel (NiAl), or tungsten (W), tungsten nitride (WN), or combination. In various embodiments, the thickness (height) of the gate structure 118 can range from about 1,000 angstroms to about 5,000 angstroms.

The dielectric material 120 is positioned above the substrate and over the gate structure 118. The dielectric material 120 may include a low dielectric constant k interlayer dielectric (ILD) material such as hafnium oxide (SiO ₂ ), doped tantalum carbide oxide (SiCO), or the like. The dielectric material 120 includes one or more metal interconnect layers 122 for providing an anode termination 108, a cathode termination 110, and a gate structure 118 that are electrically coupled to the L-FER device 100. In some embodiments, the one or more metal interconnect layers 122 can include one or more metal vias 122a for providing vertical connections, and one or more metal lines 122b for providing lateral connections.

One or more metal interconnect layers 122 are used to electrically couple the gate structure 118 to the anode termination 108. By connecting the gate structure 118 to the anode termination 108, the three terminal devices (anode termination 108, cathode assembly 110 and gate structure 118) are converted to two terminal lateral rectifiers having a drift length L _D , thus The threshold voltage of the channel (rather than the Schottky barrier of the anode termination 108) determines the forward turn-on voltage of the L-FER device 100. During operation, one or more metal interconnect layers 122 may be operated to bias the L-FER device 100 in a forward bias mode operation or a reverse bias mode operation. For example, applying a forward bias to the gate structure 118 causes the channel to open, while applying a reverse bias to the gate structure 118 causes the channel to close.

2 is a diagram illustrating the performance parameters of the disclosed HEMT compatible gallium nitride (GaN) rectifier device. The first y-axis illustrates the on-resistance (ie, drain-to-source resistance) and the drift length L _D (x-axis). The second y-axis system illustrates the breakdown voltage and the drift length LD (x-axis).

As shown in FIG. 200, the GaN lateral rectifier device has a reverse breakdown voltage of 660 V and an on-resistance R _ON at a drift length L _D of 9 μm, _{and SP} is 3.72 mOhm*cm ² . The resulting indicator (BV ₂ /R _{ON, SP} ) power pattern is 117 MW*cm ^-2 , which is compatible with the most advanced GaN rectifiers, and the state-of-the-art GaN rectifier is not compatible with HEMT.

3 is a cross-sectional view showing some embodiments of an integrated wafer 300 including the disclosed L-FER 302 integrated with a normally-off HEMT 304.

The description of L-FER 302 is shown in Figure 1. The normally-off HEMT 304 series includes a source terminal 306, a drain terminal 308, and a gate structure 310 positioned above a hetero-junction (eg, AlGaN/GaN hetero-junction). As shown, L-FER 302 shares a common semiconductor material epitaxial layer 104 over substrate 102 with normally-off HEMT 304. In some embodiments, the L-FER 302 and the normally-off HEMT 304 can be fabricated as an integrated structure (eg, on the same integrated wafer) using the same process.

4 is a cross-sectional view illustrating some embodiments of a high electron mobility transistor (HEMT) compatible lateral field effect rectifier (LFER) device 400 having a passivation layer 402.

The HEMT compatible L-FER device 400 includes a passivation layer 402 over the electron supply layer 106 and the doped III-N semiconductor material 114. In some embodiments, passivation layer 402 continues to extend from anode termination 108 to cathode termination 110. In some embodiments, the passivation layer 402 abuts the top surface of the electron supply layer 106, the top surface of the doped III-N semiconductor material 114, and the sidewalls of the doped III-N semiconductor material 114. In some embodiments, the passivation layer 402 can also abut the sidewalls of the anode termination 108 and the cathode termination 110.

The passivation layer 402 is used to passivate surface traps and defects in the underlying electron supply layer 106 and the doped III-N semiconductor material 114. Passivation layer 402 can increase device reliability and DC performance by passivating surface traps and defects. For example, surface traps and defects are typically activated during high temperature reverse bias (HTRB) stresses, causing current degradation in the HEMT compatible L-FER device 400. Passivation layer 402 reduces current degradation caused by HTRB stress on HEMT compatible L-FER device 400, Thus, the current system before and after the HTRB stress is substantially the same (ie, the passivation layer 402 mitigates current degradation due to HTRB stress).

In some embodiments, passivation layer 402 includes a nitride-based passivation layer. For example, in some embodiments, passivation layer 402 can include aluminum nitride (AlN) or tantalum nitride (Si ₃ N ₄ ). For example, the thickness t of the passivation layer 402 ranges from about 5 angstroms to about 100 angstroms.

The insulating material layer 112 is tied over the passivation layer 402. The gate isolation material 116 is disposed on the insulating material layer 112 and the passivation layer 402. Gate structure 404 is positioned above gate isolation material 116. In some embodiments, the gate structure 404 is laterally located between the sections of the insulating material layer 112. In some embodiments, the gate structure 404 can have sidewalls that are vertically aligned with the sidewalls of the lower gate isolation material 116 and abut the insulating material layer 112 and the gate isolation material 116. In such embodiments, the passivation layer 402 can extend laterally beyond the gate structure 404. In some embodiments, the gate structure 404 is laterally isolated from the anode termination 108 by the layer of insulating material 112.

FIG. 5 illustrates a cross-sectional view of some embodiments of a high field mobility transistor (HEMT) compatible lateral field effect rectifier (LFER) device 500.

The HEMT compatible L-FER device 500 has a doped III-N semiconductor material 502 having a height h that causes the doped III-N semiconductor material 502 to extend to a position perpendicular to the anode termination 108 to above the cathode termination 110. It is understood that the height of the doped III-N semiconductor material 502 adjusts the threshold voltage of the L-FER device. As shown by the HEMT compatible L-FER device 500, the height of the doped III-N semiconductor material 502 causes the passivation layer 504 to abut the opposing sidewalls of the doped III-N semiconductor material 502.

6 is a flow chart illustrating some embodiments of a method 600 of forming a HEMT compatible lateral field effect rectifier (L-FER) device.

Although the method 600 is described and illustrated in the following as a series of acts or views, it is to be understood that the order of the acts or the description is not intended to limit the disclosure. For example, some actions may be in a different order and/or different from the other The event or event occurs simultaneously. Moreover, not all of the acts described are required to be implemented in one or more aspects of the embodiments described herein. Furthermore, one or more of the acts described herein can be performed in one or more individual acts and/or phases.

At 602, a substrate is provided having an epitaxial heterojunction between the layer of semiconductor material and the electron supply layer. In some embodiments, the substrate includes a layer of semiconductor material (eg, a III-V semiconductor material) and an upper electron supply layer, epitaxial growth grown over the substrate (eg, a sapphire substrate, a germanium substrate, a tantalum carbide substrate, etc.). The semiconductor material layer and the electron supply layer have different energy bands to form a heterojunction.

At 604, an anode termination and a cathode termination are formed at opposite ends of the electron supply layer. The anode and cathode terminals include ohmic contact regions.

At 606, a layer of doped III-N semiconductor material is selectively formed on the electron supply layer. In some embodiments, the doped III-N semiconductor material layer can include a doped gallium nitride (GaN) material having p-type doping and/or n-type doping.

At 608, in some embodiments, a passivation layer can be formed over the doped III-N semiconductor material layer and the electron supply layer. In some embodiments, a passivation layer can be formed over the doped III-N semiconductor material layer and the electron supply layer and in direct contact with the doped III-N semiconductor material layer and the electron supply layer.

At 610, an insulating material layer is selectively formed over the substrate, over the anode termination, cathode termination, doped III-N semiconductor material and/or electron supply layer. In some embodiments, a layer of insulating material can be formed over the passivation layer and in direct contact with the passivation layer.

At 612, a layer of insulating material is selectively etched to expose the doped III-N semiconductor material or passivation layer.

At 614, a layer of gate isolation material is formed over the layer of insulating material and over the layer of doped III-N semiconductor material or passivation layer.

At 616, a gate structure is formed over the gate isolation material layer, Positioned above the layer of doped III-N semiconductor material.

At 618, one or more metal interconnect layers are formed within the interlayer dielectric (ILD) material to electrically couple the anode termination to the gate structure.

7 through 13b are cross-sectional views illustrating some embodiments of a structure for forming a lateral field effect rectifier (L-FER) device and corresponding to the method of method 600. Although the description of FIGS. 7 through 13b pertains to method 600, it will be understood that the structures disclosed in FIGS. 7 through 13b are not limited to this method, but are merely structural examples.

FIG. 7 illustrates a cross-sectional view 700 of some embodiments of a substrate corresponding to acts 602-604.

As shown in cross-sectional view 700, semiconductor material layer 104 and electron supply layer 106 are epitaxially grown over substrate 102 (eg, germanium, tantalum carbide, sapphire, etc.). The semiconductor material layer 104 and the electron supply layer 106 have different energy bands, thus forming an epitaxial heterojunction. In some embodiments, the semiconductor material layer 104 includes a gallium nitride (GaN) layer, and the electron supply layer 106 includes an aluminum gallium nitride (AlGaN) layer.

The anode terminal 108 and the cathode terminal 110 are formed at opposite ends of the electron supply layer 106. In some embodiments, a metal (eg, tungsten, aluminum, etc.) may be deposited on the underlying semiconductor layer by deposition techniques (eg, chemical vapor deposition, physical vapor deposition, etc.) and the deposited metal may be selectively etched, An anode termination 108 and a cathode termination 110 are formed.

FIG. 8a illustrates a cross-sectional view 800a of some embodiments of a substrate corresponding to act 606.

As shown in cross-sectional view 800a, on the electron supply layer 106, a doped III-N semiconductor material layer 114 (e.g., GaN) is selectively formed. In some embodiments, the doped III-N semiconductor material layer 114 can include an n/p gallium nitride (GaN) layer. The n/p gallium nitride layer includes a first GaN layer 114a on the electron supply layer 106 and having a first doping type (eg, n-type doping), and is located on the first GaN layer 114a and has a second Doped type (for example, p Type doped) second GaN layer 114b. For example, the n/p GaN layer may include a bottom first GaN layer 114a having a p-type doping and an upper top second GaN layer 114b having an n-type doping. The thickness and doping value of the doped III-N semiconductor material layer 114 are selectable to adjust the threshold voltage of the L-FER device. Figure 8b illustrates a cross-sectional view 800b of some embodiments of a substrate corresponding to acts 606-608.

As shown in cross-sectional view 800b, a doped III-N semiconductor material layer 114 (e.g., GaN) is selectively formed on the electron supply layer 106. On the doped semiconductor material 114 and the electron supply layer 106, a passivation layer 402 is formed. In some embodiments, a passivation layer 402 is formed adjacent the top surface of the electron supply layer 106, the top surface of the doped III-N semiconductor material 114, and one or more sidewalls of the doped III-N semiconductor material 114. . In some embodiments, passivation layer 402 can extend from anode termination 108 to cathode termination 110.

In various embodiments, for example, the passivation layer 402 may be deposited by a deposition technique (eg, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), etc.) In the range of from about 5 angstroms to about 100 angstroms. In some embodiments, passivation layer 402 can include a nitride-based passivation layer. For example, the passivation layer 402 may include aluminum nitride (AlN) or tantalum nitride (Si ₃ N ₄ ).

Figures 9a through 9b illustrate cross-sectional views 900a and 900b of some embodiments corresponding to the structure of act 610.

As shown in cross-sectional view 900a, an insulating material layer 112 is formed that is positioned over anode termination 108, cathode termination 110, and electron supply layer 106. In some embodiments, the insulating material layer 112 can include tantalum nitride (SiN) deposited by a vapor deposition technique.

As shown in cross-sectional view 900b, an insulating material layer 112 is formed that is tied to anode termination 108, cathode termination 110, and passivation layer 402, and that directly contacts anode termination 108, cathode termination 110, and passivation layer 402. In some embodiments, the passivation layer 402 is insulated The material layers are of different materials. For example, in some embodiments, passivation layer 402 can include SiN and insulating material layer 112 can include AlN.

Figures 10a through 10b illustrate cross-sectional views 1000a and 1000b of some embodiments of a substrate corresponding to act 612.

As shown in cross-sectional view 1000a, a mask layer 1002 is formed over the insulating material layer 112. The mask layer 1002 includes an opening 1004 that is tethered over the doped III-N semiconductor material 14 (eg, where the gate structure is to be subsequently formed). In some embodiments, the insulating material layer 112 is selectively exposed to the etchant 1006 according to the mask layer 1002 to remove portions of the insulating material layer 112, and thus expose the underlying doped III-N semiconductor material layer 114. .

In some embodiments, etchant 1006 can include a plasma etchant (eg, a plasma-coupled ion etchant that induces coupling, wherein high energy ion etching removes insulating material layer 112). For example, RIE plasma dry etching can be performed in a low pressure etching chamber to produce an etchant 1006.

As shown in cross-sectional view 1000b, insulating material layer 112 is selectively exposed to etchant 1006 according to mask layer 1002, a portion of insulating material layer 112 is removed, thereby exposing underlying passivation layer 402.

Figures 11a through 11b illustrate cross-sectional views 1100a and 1100b of some embodiments of a substrate corresponding to act 614.

As shown in cross-sectional view 1100a, a gate insulating material layer 116 is formed over insulating material layer 112 and doped III-N semiconductor material layer 114. In some embodiments, the gate isolation material layer 116 abuts the doped III-N semiconductor material layer within the opening 1102, and the opening 1102 is formed by selectively etching the insulating material 112 according to the mask layer 1002. The gate isolation material layer 116 provides a barrier between the subsequently formed gate structure (404) and the doped III-N semiconductor material layer 114, thereby reducing gate leakage. The gate isolation material layer 116 also prevents atoms from subsequently forming during the BEOL thermal process used to form one or more interconnect structures. The gate structure (404) diffuses to the underlying doped III-N semiconductor material layer 114.

The gate isolation material layer 116 may be deposited by a vapor deposition process (e.g., ALD, CVD, PVD, etc.) having a thickness in the range of from about 5 angstroms to about 30 angstroms. For example, in some embodiments, the gate isolation material layer 116 may include hafnium oxide (SiO ₂ ), hafnium nitride (Si ₃ N ₄ ), gallium oxide (Ga ₂ O ₃ ), aluminum oxide (Al ₂ O _{3 )} ), cerium oxide (Sc ₂ O ₃ ), cerium oxide (HfO ₂ ), or aluminum nitride (AlN).

As shown in cross-sectional view 1100b, a layer of gate isolation material 116 is formed over insulating material layer 112 and passivation layer 402. In some embodiments, the gate isolation material layer 116 abuts the passivation layer 402 within the opening 1102, and the opening 1102 is formed by selectively etching the insulating material 112 according to the mask layer 1002.

Figures 12a through 12b illustrate cross-sectional views 1200a and 1200b of some embodiments of a substrate corresponding to act 616.

As shown in cross-sectional views 1200a and 1200b, gate structure 118 is formed directly on gate isolation material layer 116. For example, a gate structure 118 can be formed using sputtering or physical vapor deposition, depositing a metal (eg, Ti, Ni, Al, NiAl, W, WN, etc.). The metal is then selectively etched, a portion of the metal is removed, and the gate structure 118 is defined.

Figures 13a through 13b illustrate cross-sectional views 1300a and 1300b of some embodiments of a substrate corresponding to act 618.

One or more metal interconnect layers 122 are formed as shown in cross-sectional views 1300a and 1300b. The one or more metal interconnect layers 122 are used to shorten the anode termination 108 to the gate structure 118. By connecting the anode termination 108 to the gate structure, the three terminal devices are converted into two terminal lateral rectifiers.

In some embodiments, the dielectric material 120 can be deposited over the substrate and the dielectric material 120 can be selectively etched to form one or more trenches to form one or more metal interconnect layers 122. Then, the trench is filled with metal to form one or more metal interconnect layers 122.

It will be understood that although the disclosure herein fully illustrates aspects of the method (e.g., the structures illustrated in Figures 7 through 13b, the method illustrated in Figure 6 is discussed), the method is not limited to the structure shown. Furthermore, the methods of use (and structures) may be considered independently of each other, and the implementation thereof is not limited to the specific aspects described. Accordingly, the layers of the present disclosure can be formed in any suitable manner, such as spin coating, sputtering, growth and/or deposition techniques, and the like.

Further, those skilled in the art can make equal changes and/or modifications after reading and/or understanding the description and drawings of the disclosure. The disclosure includes all modifications and variations and is not intended to limit the scope of the disclosure. For example, while the figures provided herein have particular doping patterns, those skilled in the art will appreciate that other doping patterns can also be used.

In addition, although certain features or aspects are disclosed only for one of the embodiments, such features or aspects may be combined with one or more other features and/or aspects of other embodiments as desired. In addition, the words "including", "having", "having", and/or variations thereof are used to include the meaning of "including". Similarly, "exemplary" refers only to examples, not to the best. It is also to be understood that the features, layers and/or elements of the present disclosure have particular dimensions and/or orientations relative to each other for purposes of simplicity of description and ease of understanding. The actual dimensions and/or orientations may be substantially different from the present disclosure. Expose the content.

The present disclosure is directed to a High Electron Mobility Transistor (HEMT) compatible power lateral field effect rectifier (L-FER) device that provides high mobility and low gate leakage.

In some embodiments, the present disclosure is directed to a High Electron Mobility Transistor (HEMT) compatible power lateral field effect rectifier (L-FER) device. The L-FER device includes a layer of semiconductor material over the substrate and an electron supply layer over the layer of semiconductor material between the anode termination and the cathode termination. The doped III-N (III-nitride) semiconductor material layer is above the electron supply layer, and the passivation layer is in the electron supply layer Above the layer of doped III-N semiconductor material. The gate structure is vertically above the doped III-N semiconductor material layer and the passivation layer.

In other embodiments, the present disclosure is directed to a lateral field effect rectifier (L-FER) device. The L-FER device includes a layer of semiconductor material over the substrate and an electron supply layer over the layer of semiconductor material disposed laterally between the anode termination and the cathode termination. The doped III-N (III nitride) semiconductor material layer is above the electron supply layer, and the nitride-based passivation layer is tied to the doped III-N semiconductor material layer and the electron supply layer and directly Contacting the doped III-N semiconductor material layer with the electron supply layer. The gate isolation material layer is above the passivation layer, which is above the doped III-N semiconductor material layer, and the gate structure is above the gate isolation material layer.

In other embodiments, the present disclosure is directed to a method of forming a lateral field effect rectifier (L-FER) device. The method includes providing a substrate having an epitaxial heterojunction between a layer of semiconductor material and an electron supply layer, and forming an anode termination and a cathode termination including an ohmic contact region at an opposite end of the electron supply layer. The method further includes selectively forming a layer of doped III-N (III-nitride) semiconductor material on the electron supply layer. The method further includes forming a passivation layer over the electron supply layer and the doped III-N semiconductor material layer. The method further includes forming a gate structure overlying the layer of doped III-N semiconductor material.

100‧‧‧L-FER device

102‧‧‧Substrate

104‧‧‧Semiconductor material layer

105‧‧‧Two-dimensional electronic gas (2-DEG)

106‧‧‧Electronic supply layer

108‧‧‧Anode terminal

110‧‧‧cathode terminal

112‧‧‧Insulation layer

114‧‧‧Doped III-N semiconductor material layer

116‧‧‧ gate isolation material layer

118‧‧‧ gate structure

120‧‧‧Dielectric materials

122a‧‧‧Metal access

122b‧‧‧metal wire

Claims (10)

A high electron mobility transistor (HEMT) compatible power lateral field effect rectifier (L-FER) device comprising: a layer of semiconductor material overlying a substrate; an electron supply layer tethered to the semiconductor Above the material layer, between the anode terminal and the cathode terminal; a doped III-N (III-nitride) semiconductor material layer that is above the electron supply layer; and a passivation layer that is tied to the electron supply layer Above the doped III-N semiconductor material layer; and a gate structure vertically above the doped III-N semiconductor material layer and the passivation layer. The L-FER device of claim 1, wherein the passivation layer is tied to the doped III-N semiconductor material layer and the electron supply layer, and directly contacts the doped III-N semiconductor material layer and The electronic supply layer. The L-FER device of claim 1, further comprising: a gate isolation material layer vertically between the passivation layer and the gate structure. The L-FER device of claim 3, wherein the gate isolation material layer is adjacent to the passivation layer and is over the doped III-N semiconductor material layer. The L-FER device of claim 1, wherein the passivation layer extends from the anode terminal to the cathode terminal. The L-FER device of claim 1, further comprising: a layer of insulating material on the passivation layer, the anode termination and the cathode termination, and directly contacting the passivation layer, the anode termination and the cathode termination Wherein the material of the passivation layer is different from the material of the layer of insulating material. The L-FER device of claim 1, further comprising: one or more metal interconnect layers for electrically coupling the gate structure to the anode termination. A lateral field effect rectifier (L-FER) device comprising: a layer of semiconductor material over a substrate; an electron supply layer positioned above the layer of semiconductor material and disposed laterally between the anode termination and the cathode termination a layer of doped III-N (III-nitride) semiconductor material, which is above the electron supply layer; a nitride is a passivation layer of the substrate, which is tied to the doped III-N semiconductor material layer On the electron supply layer, and directly contacting the doped III-N semiconductor material layer and the electron supply layer; a gate isolation material layer which is located above the passivation layer and is located on the III-N semiconductor material layer And a gate structure that is positioned above the gate isolation material layer. The L-FER device of claim 10, further comprising: a layer of insulating material on the passivation layer, the anode termination and the cathode termination, and directly contacting the passivation layer, the anode termination and the cathode termination Wherein the material of the passivation layer is different from the material of the layer of insulating material. A method for forming a lateral field effect rectifier (L-FER) device, comprising: providing a substrate having an epitaxial heterojunction between a layer of semiconductor material and an electron supply layer; forming an anode termination and a cathode termination, An ohmic contact region on opposite ends of the electron supply layer; selectively forming a doped III-N (III-nitride) semiconductor material layer on the electron supply layer; A passivation layer is formed over the electron supply layer and the doped III-N semiconductor material layer; and a gate structure is formed on the doped III-N semiconductor material layer.