TW201624288A - Cache memory device and non-transitory computer readable recording medium - Google Patents

Abstract

According to one embodiment, a cache memory device includes a nonvolatile cache memory (4), write unit (111), determination unit (112), selection unit (113), and erase unit (115). The nonvolatile cache memory (4) includes a plurality of erase unit areas. Each of the erase unit areas includes a plurality of write unit areas. The write unit (111) writes data to the nonvolatile cache memory (4). The determination unit (112) determines whether the plurality of erase unit areas satisfy an erase condition or not. The selection unit (113) selects an area to be erased from the plurality of erase unit areas when the plurality of erase unit areas satisfy the erase condition. The erase unit (115) erases the data written to the area to be erased.

Description

Cache memory device and non-transitory computer can read recording media

The embodiments set forth herein are generally directed to a cache memory device and a non-transitory computer readable recording medium.

A solid state disk drive (SSD) contains a non-volatile semiconductor memory such as a NAND flash memory. The NAND flash memory includes a plurality of blocks (physical blocks). The plurality of blocks includes a plurality of memory cells disposed at intersections of the word lines and the bit lines.

2‧‧‧ Processor

3‧‧‧ memory

4‧‧‧Non-volatile cache memory

4B‧‧‧Backend/memory communication unit

4F‧‧‧ front-end/host communication unit

5‧‧‧Solid Disk Drive

7‧‧‧ Address translation information

8‧‧‧ Address translation unit

9‧‧‧Cache Control Unit / Cache Memory / Cache Memory Control Unit

10‧‧‧Generating unit

11‧‧‧Control unit

12‧‧‧Control unit

13‧‧‧Control unit

14‧‧‧Control unit

15‧‧‧Change unit/first change unit

16‧‧‧Change unit / second change unit

17‧‧‧Information processing device

18‧‧‧Transportation unit

19‧‧‧ Receiving unit

20‧‧‧Write unit

21‧‧‧Transmission unit

22‧‧‧ Processor

23‧‧‧ memory

24‧‧‧ Non-volatile memory

25‧‧‧ Address translation unit

26‧‧‧Write unit

27‧‧‧Generating Unit/Valid/Invalid Generating Unit

28‧‧‧Selection unit

29‧‧‧Transportation unit

30‧‧‧ Receiving unit

31‧‧‧Waste collection unit

32‧‧‧ Address translation information

33‧‧‧Active/Invalid Information

34‧‧‧Delete information

35‧‧‧Information Processing System

36‧‧‧ Controller

37‧‧‧ memory system

38‧‧‧Connector

41‧‧‧Host Interface/Component

42‧‧‧Host Interface Controller/Control Unit/Component

43B‧‧‧CPU

43F‧‧‧CPU

44‧‧‧Encoding/Decoding Unit/Advanced Encryption Standard/Component

45‧‧‧ Lookup Table/Component

46‧‧‧DDRC

47‧‧‧ Dynamic Random Access Memory

48‧‧‧Direct Memory Access Controller

49‧‧‧Error Correction Code/Error Correction Unit

50‧‧‧NAND Controller/Component

61‧‧‧Management Information/List

62‧‧‧Management Information

63‧‧‧Management Information

64‧‧‧Management Information/List

100‧‧‧Storage system

111‧‧‧Write unit/first write unit

112‧‧‧Decision unit/first decision unit

113‧‧‧Selection unit / first selection unit

114‧‧‧Decision unit/second decision unit

115‧‧‧Erase unit/first erase unit

121‧‧‧Write unit/second write unit

122‧‧‧Decision unit/fifth determination unit

123‧‧‧Selection unit / third selection unit

124‧‧‧Decision unit

125‧‧‧wiping unit/second erasing unit

131‧‧‧Write unit/third write unit

132‧‧‧Decision unit/third determination unit

133‧‧‧Selection unit / second selection unit

134‧‧‧Decision unit/fourth determination unit

135‧‧‧Write unit/fifth write unit

136‧‧‧Erasing unit/third erasing unit

137‧‧‧Write unit/sixth write unit

141‧‧‧Write unit/fourth write unit

142‧‧‧Decision unit/sixth determination unit

143‧‧‧Selection Unit / Fourth Selection Unit

144‧‧‧wiping unit/fourth erasing unit

B _1,1 ‧‧‧block/first erase unit area

B _1,K ‧‧‧block/first erase unit area

B _2,1 ‧‧‧block/second erase unit area

B _2,L ‧‧‧block/second erase unit area

B _3,1 ‧‧‧block/third erase unit area

B _3,M ‧‧‧block/third erase unit area

B _4,1 ‧‧‧block/fourth erase unit area

B _4,N ‧‧‧block/fourth erase unit area

BG ₁ ‧‧‧ Block Group / First Group

BG ₂ ‧‧‧ Block Group / Second Group

BG ₃ ‧‧‧ Block Group / Third Group

BG ₄ ‧‧‧ Block Group / Fourth Group

CH0-CH3‧‧‧ channel

IB‧‧‧Internal busbar

RB‧‧‧Read buffer/read data transfer unit

RZ‧‧‧ Random Generator/Component

WB‧‧‧Write Buffer/Write Data Transfer Unit

1 is a block diagram showing a configuration example of one of the information processing devices including a cache memory device according to a first embodiment; FIG. 2 is a view showing an example of the first cache control of the first embodiment. a flow chart; FIG. 3 is a flow chart showing one example of the second cache control of the first embodiment; FIG. 4 is a flow chart showing one of the examples of the third cache control of the first embodiment; 5 is a flow chart showing one of the examples of the fourth cache control of the first embodiment; FIG. 6 is a block diagram showing one configuration example of one of the information processing systems according to a second embodiment; A flowchart of one of the examples of one of the programs executed by the information processing system according to the second embodiment; Figure 8 is a block diagram showing an example of a detailed configuration of one of the information processing systems according to a third embodiment; and Figure 9 is a perspective view showing an example of a storage system according to the third embodiment.

In general, according to one embodiment, a cache memory device includes a non-volatile cache memory, a write unit, a decision unit, a selection unit, and an erase unit. The non-volatile cache memory includes a plurality of erase unit areas. Each of the erased unit areas includes a plurality of write unit areas. The write unit writes data to the non-volatile cache memory. The determining unit determines whether the plurality of erase unit regions satisfy an erase condition. The selection unit selects an area to be erased from the plurality of erase unit regions when the plurality of erase unit regions satisfy the erase condition. The erase unit erases the material written to the area to be erased.

Embodiments will be described below with reference to the drawings. In the following description, the same component symbols indicate components having almost the same functions and configurations, and if necessary, a repeated description will be given to the components.

[First Embodiment]

In this embodiment, a cache memory device including a non-volatile cache memory is illustrated.

In this embodiment, in the non-volatile cache memory, the data is erased together for each erased unit area. The erase unit area includes a plurality of write unit areas and a plurality of read unit areas.

In this embodiment, a NAND flash memory is used as a non-volatile cache memory and a non-volatile memory. However, each of the non-volatile cache memory and the non-volatile memory may be a memory other than the NAND flash memory, provided that the memory satisfies the erase unit area, the write The above relationship between the unit area and the reading unit area.

When the non-volatile cache memory and the non-volatile memory system NAND flash memory, the erase unit area corresponds to a block. The write unit area and the read unit area correspond to one page.

In the present embodiment, for example, the erase unit area can be controlled, for example, by another unit of two blocks, which allows the data to be erased collectively.

In this embodiment, the access indication writes data to both a memory device and a data read from the memory device.

1 is a block diagram showing a configuration example of one of information processing apparatuses including a cache memory device according to the present embodiment.

An information processing system 35 includes an information processing device 17 and an SSD 5. The information processing device 17 may correspond to one of the SSDs 5 host devices.

The information processing device 17 includes a processor 2, a memory 3, and a non-volatile cache memory 4. The SSD 5 may be included in the information processing device 17, or may be connected to the information processing device 17 for transmitting and receiving data via a network or the like. Instead of the SSD 5, another non-volatile memory device such as a hard disk drive (HDD) can be used.

The information processing device 17 includes a cache memory device having a cache control unit 9, a memory 3 storing the management information 61 to 64, and a non-volatile cache memory 4. However, all or part of the cache control unit 9, the management information 61 to 64, the memory 3, and the non-volatile cache memory 4 may be provided outside the information processing device 17.

The non-volatile cache memory 4 includes block groups BG ₁ to BG ₄ . The non-volatile cache memory 4 has one access speed higher than the access speed of the SSD 5.

The block group (first group) BG ₁ contains blocks (first erase unit area) B _1,1 to B _1,K . The block group BG ₁ stores the data accessed by the processor 2 (i.e., the data used by the processor 2).

In this embodiment, when the block group BG ₁ satisfies an erasing condition (first erasing condition), the block B _1,1 in the block group BG ₁ is based on the first in first out (FIFO) to B _{1, K} selects a block to be erased (to be revoked or pushed out of the block) (first area to be erased).

For example, when the amount of data of each of the blocks B _1,1 to B _1,K of the block group BG ₁ exceeds a predetermined value, the erasing condition is satisfied. For example, when the number of pages written to each of the blocks B _1,1 to B _1,K of the block group BG ₁ exceeds a predetermined number, the erase condition can be satisfied.

When writing to the data to be erased from the block B _1,1 to B _1,K based on the FIFO is in a first low use state (for example, when the data is accessed less than The data is written to a block group BG ₂ when a first number of times is set or when less than a set first frequency is accessed. In contrast, when the data written to the block to be erased selected from the blocks B _1,1 to B _1,K is in a first high use state (for example, when the data is accessed) the first number of times or more or when it is accessed), a group of blocks to write the data BG ₃ or greater at a first frequency. The data written to the block to be erased selected from blocks B _1,1 to B _1,K is erased (ie, abolished or pushed out) per block.

The block group (second group) BG ₂ contains blocks (second erase unit area) B _2,1 to B _2,L . Group BG block ₂ is written into the storage blocks selected to be of _a Group BG erase the data in the data block is in the first state of low usage.

In the present embodiment, when the block group BG ₂ satisfies an erasing condition (third erasing condition), the block B _2,1 to B _{2, L} in the block group BG ₂ is selected based on the FIFO. The block to be erased (the third area to be erased).

When writing to the data to be erased from the block B _2,1 to B _2,L according to the FIFO is in a third low use state (for example, when the data is accessed less than The data is erased when a third number is set or when less than a set third frequency is accessed. In contrast, when writing to the block to be erased from the block B _2,1 to B _2,L is in a third high use state (for example, when the data is accessed) The data is written to a block group BG ₃ when the third time or more or when the third frequency or more is accessed. Then, the data written to the block to be erased selected from the blocks B _{2, 1} to B _{2, L} is erased by each block.

The block group (third group) BG ₃ contains blocks (third erase unit area) B _3,1 to B _3,M . Group _{BG. 3} blocks written to storage blocks selected to be of _a Group BG erase the data in the data block is in the first state of low usage. The block group BG ₃ also stores data written in the third highest usage state written in the material of the block to be erased selected from the block group BG ₂ .

In the present embodiment, when the block group BG ₃ satisfies an erasing condition (second erasing condition), the block B _3,1 to B _3,M in the block group BG ₃ is selected based on the FIFO. The block to be erased (the second area to be erased).

When the data to be erased from the block B _3,1 to B _3,M according to the FIFO is written to a second low use state (for example, when the data is accessed less than The data is written to the block group BG ₄ when a second number of times is set or when less than one set second frequency is accessed. In contrast, when writing to the block to be erased from the block B _3,1 to B _3,M is in a second high use state (for example, when the data is accessed) the second number of times or more or when the frequency is accessed to a second or more), re-writes the data to another block ₃ in the block group BG. Then, the data written to the block to be erased selected from the blocks B _{3, 1} to B _{3, M} is erased by each block.

The block group (fourth group) BG ₄ contains blocks (fourth erase unit area) B _4,1 to B _4,N . The block group BG ₄ stores the data in the second low usage state written to the material of the block to be erased selected from the block group BG ₃ .

In the present embodiment, when the block group BG ₄ satisfies an erasing condition (fourth erasing condition), the block B _4,1 to B _4,N in the block group BG ₄ are selected based on the FIFO. The block to be erased (the fourth area to be erased).

The erase is written to the data to be erased from the block B _4,1 to B _4,N according to the FIFO.

In the present embodiment, the FIFO is used as a method for selecting one of the blocks to be erased from each of the block groups BG ₁ to BG ₄ . By selecting the block to be erased in accordance with the FIFO, the erase is performed sequentially from the block having one of the oldest write time and the write order in each of the block groups BG ₁ to BG ₄ . However, for example, the block to be erased may be selected randomly or based on least recently used (LRU) or least frequently used (LFU). For example, the management information 61 to 64 includes the identification information of the data, the information indicating whether the data is the information to be deleted, and the usage status information of the data. A block having one of the largest invalid data amounts or one block having one of the invalid data amounts greater than a predetermined amount may be selected as the block to be erased based on the management information 61 to 64. For example, one of the blocks having the largest invalid data and the data to be deleted (deleted target data) or one of the invalid data and one of the data to be deleted may be selected based on the management information 61 to 64. As the block to be erased.

The memory 3 stores various types of control data such as management information (lists) 61 to 64 and address translation information 7. The memory 3 can be a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or can be a non-volatile memory. The memory 3 can be included in the non-volatile cache memory 4.

In this embodiment, the cache control unit 9 can identify the identification information of the cached data based on the management information 61 to 64 and the address translation information 7 (for example, one logical address provided from the host (for example, , logical block addressing)), the data is written to a location and one of the data usage status. For example, the cache control unit 9 can select the data cached to each of the block groups BG ₁ to BG ₄ based on the management information 61 to 64 and the address translation information 7 and according to one of the FIFO erases. Block.

The management information 61 to 64 are data written after the data written to the block groups BG ₁ to BG ₄ , respectively. For example, the management information 61 to 64 contain information indicating the state of use of the respective data by the processor 2. For example, the management information 61 to 64 includes identification information of the individual data, whether the information is the deletion information of the data to be deleted, whether the information is valid/invalid information of the valid data, and whether the content is valid for the erasing area. The block erase condition is used to determine the information.

The deletion information indicates that information about one of the data deletion commands is issued. More specific In other words, the deletion information indicates that the free processor 2 executes one of the applications or an operating system (OS) to receive information on one of the data deletion commands, and the like. In this embodiment, for example, the deletion information includes information for identifying the identification information of each block and a logical address indicating one of the to-be-deleted data written to each block.

The valid/invalid information indicates, for example, that when the same data is written to a plurality of locations, the latest data is valid and the data other than the latest data is information of the invalid data. In other words, for example, in the case of performing an update to the data written to the non-volatile cache memory 4, the valid data is updated. For example, in the case of performing an update, the invalid data is unupdated material. In this embodiment, for example, the valid/invalid information includes information that associates the identification information of each block with a logical address indicating one of valid data or invalid data written to each block.

The cache determination information includes, for example, information on at least one of the write information and the read information of each data or at least one of the write information and the read information of each block.

For example, the write information includes at least one of a write time, a write count, a write frequency, and a write order.

For example, the read information includes at least one of a read time, a read count, a read frequency, and a read order.

For example, the address translation information 7 associates one of the logical addresses of the data with a physical address of one of the non-volatile cache memories 4 corresponding to the logical address (for example, physical block addressing). For example, the address translation information 7 is managed in the form of a table.

The processor 2 functions as an address translation unit 8 and a cache control unit 9 by executing one of the memory, the memory 3, the non-volatile cache 4 or the SSD 5 stored in the processor 2. .

In this embodiment, for example, the program used to cause the processor 2 to function as the address translation unit 8 and the cache control unit 9 may be an OS, an intermediate software or a firmware. In this embodiment All or part of the address translation unit 8 or all or part of the cache control unit 9 may be implemented by hardware.

The address translation unit 8 generates information for associating a logical address of one of the written data with a physical address indicating one of the locations in the non-volatile cache 4 storing the written data, and temporarily generating the generated information. Save to address translation information7.

When the logical address of one of the read data is received from the processor 2, the address translation unit 8 translates the logical address into a physical address based on the address translation information 7.

The cache control unit 9 performs cache control for the non-volatile cache memory 4 having an access speed higher than the access speed of the SSD 5. For example, the cache control unit 9 manages the data and indicates the logical address and physical address of the data by a direct write through method or an indirect write back method.

In the direct write back method, the data is stored in the non-volatile cache memory 4 and also stored in the SSD 5.

In the indirect write back method, the data stored in the non-volatile cache memory 4 is not stored together in the SSD 5. The data is first stored in the non-volatile cache memory 4, and then the data derived from the non-volatile cache memory 4 is stored in the SSD 5.

The cache control unit 9 includes a generation unit 10, control units 11 to 14, and change units 15 and 16.

The generating unit 10 generates management information 61 to 64 corresponding to the block groups BG ₁ to BG ₄ and writes the management information 61 to 64 to the memory 3.

The control units 11 to 14 control data writing and block erasing for the block groups BG ₁ to BG ₄ , respectively.

The control unit 11 includes a writing unit 111, a determining unit 112, a selecting unit 113, a determining unit 114, and an erasing unit 115.

The write unit (first write unit) 111 writes the material accessed by the processor 2 to the block group BG ₁ .

The determination unit (first determination unit) 112 determines whether the block group BG ₁ satisfies the erasing condition (first erasing condition).

When the erase block group BG ₁ satisfies the condition, the selecting unit (the first selecting means) 113 from a group of blocks to be selected BG ₁ erase block (the first region to be erased).

The determining unit (second determining unit) 114 determines, based on the management information 61, whether each data item written to the block to be erased is in the first high use state or the first low use state and whether each item of the data is The data to be deleted.

When the data item written to the block to be erased can be abolished because each data item is written to the block group BG ₂ to BG ₃ or is to be deleted, the erasing unit (first wipe) In addition to the unit) 115, the block to be erased is erased.

The control unit 12 includes a writing unit 121, a determining unit 122, a selecting unit 123, a determining unit 124, and an erasing unit 125.

When the determining unit 114 determines that the data of the block to be erased written to the block group BG ₁ is in the first low use state and is not the data to be deleted, the writing unit (second writing unit) 121 writes the data. Enter the block group BG ₂ .

The determination unit (fifth determination unit) 122 determines whether the block group BG ₂ satisfies the erasing condition (third erasing condition).

When the block group BG ₂ satisfies the erase condition, the selection unit (third selection unit) 123 selects an to-be-erased block (third to-be-erased area) from the block group BG ₂ .

The determining unit 124 determines, based on the management information 62, whether each data item written to the block to be erased is in the third high use state or the third low use state and whether each item of the data is the data to be deleted.

When the data written to the block to be erased is in the third highest use state and is not to be deleted, and is written to the block group BG ₃ , the erasing unit (second erasing unit) 125 erases the writing. Information to be erased.

The control unit 13 includes a writing unit 131, a determining unit 132, and a selecting unit. 133, a determining unit 134, a writing unit 135, an erasing unit 136 and a writing unit 137.

When the determining unit 114 determines that the data of the block to be erased written to the block group BG ₁ is in the first high use state and is not the data to be deleted, the writing unit (third writing unit) 131 writes the material. Go to block group BG ₃ .

When the data written to the tile group BG ₂ is in the third high use state and is not the data to be deleted, the write unit (sixth write unit) 137 writes the material to the tile group BG ₃ . For example, when the data written to the block group BG _{2 is} the data to be accessed by the processor 2, the writing unit 137 can write the to-be-accessed data of the block group BG ₂ to the block. Group BG ₃ .

The determination unit (third determination unit) 132 determines whether the block group BG ₃ satisfies the erase condition (second erase condition).

When the erase block group BG ₃ satisfies condition selection unit (second selecting means) 133 BG ₃ groups selected from the blocks to be a block erase (erase region to be a second).

The determining unit (fourth determining unit) 134 determines, based on the management information 63, whether each data item written to the block to be erased is in the second high use state or the second low use state and whether each item of the data is The data to be deleted.

When the data of the block to be erased written to the block group BG ₃ is determined to be in the second high use state and is not the data to be deleted, the write unit (fifth write unit) 135 writes the data again. Enter another writable block in block group BG ₃ .

Each item of data written to the block to be erased may be written to the block group BG ₄ for each data item, written to the block group BG _{3 again,} or deleted for the data to be deleted. When abolished, the erase unit (third erase unit) 136 erases the block to be erased.

The control unit 14 includes a writing unit 141, a determining unit 142, a selecting unit 143, and an erasing unit 144.

When the determining unit 134 determines that the data of the block to be erased written to the block group BG ₃ is in the second low use state and is not the data to be deleted, the writing unit (fourth writing unit) 141 writes the material. Go to block group BG ₄ .

The determination unit (sixth determination unit) 142 determines whether the block group BG ₄ satisfies the erase condition (fourth erase condition).

When the block group BG ₄ satisfies the erasing condition (fourth erasing condition), the selecting unit (fourth selecting unit) 143 selects a block to be erased from the block group BG ₄ (fourth to be erased area) ).

The erase unit (fourth erase unit) 144 erases the data to be erased from the block to be written to the block group BG ₄ .

When the data written to the tile group BG ₂ reaches the third high use state, the change unit (first change unit) 15 increases the number of blocks included in the block group BG ₁ and reduces the block group The number of blocks included in BG ₃ . For example, when the data written to the block group BG ₂ is accessed by the processor 2, the changing unit 15 increases the number of blocks included in the block group BG ₁ and reduces the block group BG ₃ The number of blocks included in the block.

When the data written to the block group BG ₄ reaches the fourth high use state, the changing unit (second changing unit) 16 increases the number of blocks included in the block group BG ₃ and reduces the block group The number of blocks included in BG ₁ . For example, when the data written to the block group BG ₄ is accessed by the processor 2, the changing unit 16 increases the number of blocks included in the block group BG ₃ and reduces the block group BG ₁ The number of blocks included in the block.

Fig. 2 is a flow chart showing one of the examples of the first cache control according to the present embodiment. 2 exemplarily shows in which data is written to the tile group BG ₁ , data is written to the tile group BG ₂ or BG ₃ and one of the tile groups BG ₁ is erased. One of the programs.

In step S201, the writing unit 111 of the data access by the processor 2 writes to the group of blocks BG _1.

In step 202, the determination unit 112 determines whether the block group BG ₁ satisfies the erase condition.

When the block group BG ₁ does not satisfy the erase condition, the process proceeds to step S206.

When erased block group BG ₁ satisfies the condition, in step S203, the selection unit 113 from a group of blocks to be selected BG ₁ erase block.

In step S204, the determining unit 114 determines, based on the management information 61, whether each data item written to the block to be erased is in the first high use state or the first low use state and whether each item of the data is to be treated. Erase data (delete target data).

When the material item is in the first low use state and the material is not the data to be deleted (non-deleted target data), in step S301, the writing unit 121 writes the material item to the block group BG ₂ .

When the data item is in the first state and the use of high data not to be deleted, in step S401, the writing unit 131 to write the data item block group BG _3.

When each item of data written to the block to be erased can be abolished because each item of the data is written to the block group BG ₂ or the block group BG3 or the data to be deleted is deleted. In S205, the erasing unit 115 erases the block to be erased.

In step S206, the cache control unit 9 determines whether or not the program will be ended.

When the cache control unit 9 does not end the program, the program returns to step S201.

When the cache control unit 9 ends the program, the program ends.

Fig. 3 is a flow chart showing one example of the second cache control according to the present embodiment. FIG. 3 exemplarily shows a program in which data is written to the tile group BG ₂ and one of the blocks to be erased in the block group BG ₂ is erased.

When the data of the block to be erased written to the block group BG ₁ is determined to be in the first low use state and is not to be deleted in step S204, in step S301, the writing unit 121 The data is written to the block group BG ₂ .

In step S302, the determination unit 122 determines whether the block group BG ₂ satisfies the erase condition.

When the block group BG ₂ does not satisfy the erase condition, the program proceeds to step S306.

When erased block group BG ₂ satisfies the condition, in step S303, the selection unit 123 from the block group BG ₂ select a block to be erased.

In step S304, the determining unit 124 determines, based on the management information 62, whether each data item written to the block to be erased is in the third high use state or the third low use state and whether each item of the data is to be treated. Delete the data.

When the data item is in the third low use state or is to be deleted, the program proceeds to step S305.

When the data item is in the third state and not to use the high data to be deleted, in step S401, the writing unit 137 to write the data item block group BG _3.

In step S305, the erase unit 125 to erase the writing ₂ of the group of blocks to be erased BG of the data block.

In step S306, the cache control unit 9 determines whether or not the program will be ended.

When the cache control unit 9 does not end the program, the program returns to step S301.

When the cache control unit 9 ends the program, the program ends.

4 is a flow chart showing one example of a third cache control according to the present embodiment. FIG. 4 exemplarily shows a program from the data in which data is written to the tile group BG ₃ to the erase block group BG ₃ .

When the data of the block to be erased written to the block group BG ₁ is determined to be in the first high use state and is not to be deleted in step S204, in step S401, the writing unit 131 The data is written to the block group BG ₃ . When the data written to the block group BG ₂ is determined to be in the third high use state (for example, the data is accessed by the processor 2) and is not to be deleted in step S304, the writing unit 137 Writes the data of the block group BG ₂ to the block group BG ₃ .

In step S402, the determination unit 132 determines whether the block group BG ₃ satisfies the erase condition.

When the block group BG ₃ does not satisfy the erase condition, the program proceeds to step S407.

When the erase block group BG ₃ satisfies the condition, in step S403, the selection unit 133 from the block group BG ₃ selects a block to be erased.

In step S404, the determining unit 134 determines, based on the management information 63, whether each data item written to the block to be erased is in the second high use state or the second low use state and whether each item of the data is to be treated. Delete the data.

When the material item is in the second low use state and is not to be deleted, in step S501, the writing unit 141 writes the material to the block group BG ₄ .

When the data is in the second highest use state and is not to be deleted, in step S405, the writing unit 135 writes the data of the to-be-erased block written to the block group BG ₃ to the block group again. Another block in BG ₃ .

In step S406, each item of data written to the block to be erased may be written to the block group BG ₄ for each data item, written to the block group BG ₃ or the system again. When the data to be deleted is discarded, the erasing unit 136 erases the block to be erased.

In step S407, the cache control unit 9 determines whether or not the program will be ended.

When the cache control unit 9 does not end the program, the program returns to step S401.

When the cache control unit 9 ends the program, the program ends.

Fig. 5 is a flow chart showing one of the examples of the fourth cache control according to the present embodiment. 5 illustrates exemplary display of one of the _{4 4} wherein the information to write data to the program block and erase blocks Group BG Group BG.

When the data of the block to be erased written to the block group BG ₃ is determined to be in the second low state and is not to be deleted in step S404, the writing unit 141 writes the data in step S501. Write to block group BG ₄ .

In step S502, the determination unit 142 determines whether the block group BG ₄ satisfies the erase condition.

When the block group BG ₄ does not satisfy the erase condition, the process proceeds to step S505.

When erased block group BG ₄ satisfies the condition, in step S503, the selection unit 143 from the block group BG ₄ selects a block to be erased.

In step S504, the erase unit 144 to be erased is written in the ₄ blocks of Group BG erase data block.

In step S505, the cache control unit 9 determines whether or not the program will be ended.

When the cache control unit 9 does not end the program, the program returns to step S501.

When the cache control unit 9 ends the program, the program ends.

In the block group BG ₁ of the present embodiment, for example, data is first sequentially written to the block B _1,1 , and then sequentially written to the block B _1,2 , and then similarly written. To block B _1,3 to B _1,K . When the amount of data of one of the blocks B _1,1 to B _1,K included in the block group BG ₁ exceeds a predetermined amount of data, the block B _{1,1 in} which the writing is completed first is erased according to the FIFO. And the data is sequentially written to the erased block B _1,1 . After completing the writing to block B _1,1 , block B _1,2 is erased according to the FIFO. Then, the data is sequentially written to the erased block B _{1,2 again} . Repeat the same control.

In the block group BG ₁ , it is determined based on the management information 61 whether the data written to the block to be erased in the block group BG ₁ is accessed (for example) less than the first number or It is accessed at less than the first frequency. When the data written to the block to be erased in the block group BG ₁ is accessed less than the first number of times or is accessed less than the first frequency, the block group BG _{2 is selected} as the data. Write to the destination.

In contrast, when the data written to the block to be erased in the block group BG ₁ is accessed for the first time or more or accessed at the first frequency or more, the selection area The block group BG _{3 is} written to the destination as one of the materials.

When the data to be erased in the block to be erased in the block group BG ₁ is to be deleted, the data is revoked.

In the block group BG ₂ of the embodiment, the data from the block group BG ₁ in the first low use state is first sequentially written to the block B _2,1 , and then sequentially written to the block. B _2,2 and then similarly written to block B _2,3 to B _2,L . When the amount of data of one of the blocks B _2,1 to B _{2, L} included in the block group BG ₂ exceeds a predetermined amount of data, the block B _{2,1 in} which the writing is completed first is erased according to the FIFO. And the data is sequentially written to the erased block B _2,1 . After completing the writing to block B _2,1 , block B _2,2 is erased according to the FIFO. Then, the data is sequentially written to the erased block B _2,2 . Repeat the same control.

In the block group BG ₂ , it is determined based on the management information 62 whether the data written to the block to be erased in the block group BG ₂ is accessed (for example) less than the third number or Less than the third frequency is accessed. When the data written to the block to be erased in the block group BG ₂ is accessed less than the third time or accessed at less than the third frequency, the data is erased.

In contrast, when the data written to the block to be erased in the block group BG ₂ is accessed for the third time or more or accessed at the third frequency or more, the block is selected. Group BG _{3 is} written to the destination as one of the materials.

When the data to be erased in the block to be erased in the block group BG ₂ is to be deleted, the data is revoked.

In the block group BG ₃ of the embodiment, the data from the block group BG ₁ in the first high use state, the data in the third highest use state from the block group BG ₂ or from the block The rewrite data of group BG ₃ is first written to block B _{3,1 first} , then sequentially to block B _3,2 , and then similarly written to block B _3,3 to B. _{3, M.} When the amount of data of one of the blocks B _3,1 to B _3,M included in the block group BG ₃ exceeds a predetermined amount of data, the block B _{3,1 in} which the writing is completed first is erased according to the FIFO. And the data is sequentially written to the erased block B _3,1 . After completing the writing to block B _3,1 , block B _3,2 is erased according to the FIFO. Then, the data is sequentially written to the erased block B _{3,2 again} . Repeat the same control.

In the block group BG ₃ , it is determined based on the management information 63 whether the data written to the block to be erased in the block group BG ₃ is accessed (for example) less than the second number or Less than the second frequency is accessed. When the data written to the block to be erased in the block group BG ₃ is accessed less than the second number or is accessed less than the second frequency, the block group BG _{4 is selected} as one of the materials. Write to the destination.

In contrast, when the data written to the block to be erased in the block group BG ₃ is accessed for the second time or more or accessed at the second frequency or more, the data is again accessed. Write to block group BG ₃ .

When the data to be erased in the block to be erased in the block group BG ₃ is to be deleted, the data is revoked.

In the block group BG ₄ of the embodiment, the data from the block group BG ₃ in the second low use state is first sequentially written to the block B _4,1 , and then sequentially written to the block. B _4,2 and then similarly written to block B _4,3 to B _4,N . When the amount of data of one of the blocks B _4,1 to B _4,N included in the block group BG ₄ exceeds a predetermined amount of data, the block B _{4,1 in} which the writing is completed first is erased according to the FIFO. And the data is sequentially written to the erased block B _4,1 . After completing the writing to block B _4,1 , block B _4,2 is erased according to the FIFO. Then, the data is sequentially written to the erased block B _4,2 . Repeat the same control.

In this embodiment, the control unit 14 may determine whether the data written to one of the block groups BG ₄ to be erased is in a fifth high use state. When the data of the block to be erased written to the block group BG ₄ is determined to be in the fifth high use state, the data is maintained in the non-volatile cache memory 4, and the control unit 13 The data can be written to one of the block groups BG ₃ to be written to the destination area block. In this case, the processor 2 can reduce the size of the one block group _a BG.

In the present embodiment, the materials are managed based on the four block groups BG ₁ to BG ₄ .

For example, in _a block group BG in the first data managed by the first processor 2 to access (via the primary access data).

For example, if the second data in the block group BG ₁ is accessed twice or more times by the processor 2 and is derived from the block group BG ₁ based on the FIFO, the second data is self-blocked. Group BG ₁ moves to block group BG ₃ .

It should be noted that in the present embodiment, the size of the block group BG ₁ is larger than the size of the block group BG ₃ .

For example, when the third data block Group BG ₁ in _which the FIFO is not based on a case where the second access from the processor ₁ Release Group BG blocks, the data from the third block group BG ₁ moves to block group BG ₂ .

For example, if the block group BG ₃ in the fourth data is not based on the group of blocks from the FIFO is cleared by BG ₃ in the case 2 of the access processor, then data from the fourth block group BG ₃ moves to block group BG ₄ .

For example, in the block groups BG ₂ and BG ₄ , the data can be cached instead of the cached data. Subsequent information contains information related to the information. In other words, the post-data is highly abstract and additional information about the material and is attached to it.

In this embodiment, for example, when the fifth data is stored in the block group BG ₁ , the sixth data in the block group BG ₂ may be pushed out based on the FIFO.

For example, when the seventh data in the block group BG ₁ is accessed and pushed out from the block group BG ₁ based on the FIFO, the seventh data can be moved from the block group BG ₁ to the block. group BG _3, based on the FIFO block group BG ₃ and the data from the block of the eighth group BG ₃ moves to block group BG _4, and may be based on self-FIFO block group BG ₄ Release The ninth data in the block group BG ₄ .

For example, when the tenth data in the block group BG ₂ is accessed, the size of the block group BG ₁ is increased. If the size of the block group BG ₁ is increased, the eleventh data in the block group BG ₃ is moved to the block group BG ₄ based on the FIFO.

For example, when the twelfth material in the block group BG ₄ is accessed and is pushed out from the block group BG ₄ based on the FIFO, the twelfth material is moved to the block group BG ₃ , and The size of the block group BG ₁ is reduced.

In the embodiment described above, a maintenance decision determines whether to maintain the data of a block unit, and a transfer write writes the block data to be maintained to a destination area block, and writes to The data of the non-volatile cache memory 4 is erased per block.

In this embodiment, an effective cache capacity can be added, the hit rate of the non-volatile cache memory 4 can be increased, and the speed of one of the information processing devices 17 can be increased.

In the present embodiment, in the case where waste collection is not performed for the non-volatile cache memory 4, one of the performances can be prevented from being lowered. Since waste collection is not necessary, the number of writes to the non-volatile cache memory 4 can be reduced and the life of the non-volatile cache memory 4 can be increased. In addition, since waste collection is not necessary, there is no need to ensure a provisioning area. Therefore, the data capacity which can be used as one of the cache memories can be increased, and the use efficiency can be improved.

For example, when non-volatile memory is used as a cache memory and data is abolished regardless of the boundary of the block, waste collection can be performed frequently to validate data in one of the non-volatile memory blocks. Move to another block. In the present embodiment, it is not necessary to perform waste collection in the non-volatile cache memory 4. Therefore, as explained above, in the present embodiment, the life of the non-volatile cache memory 4 can be increased.

[Second embodiment]

This embodiment is a modified example of one of the first embodiments. In the present embodiment, the transmission and reception of data and information between the information processing device 17 including the cache control unit 9 and the SSD 5 are explained.

In this embodiment, a logical address is used as the identification information of the data. However, information can be identified by other information.

Fig. 6 is a block diagram showing a configuration example of one of the information processing apparatuses 35 according to the present embodiment.

In addition to the constituent elements set forth in the first embodiment, the cache control unit 9 further includes a transmission unit 18, a receiving unit 19, a writing unit 20, and a transmission unit. twenty one.

The transmission unit 18 transmits the write data for the SSD 5 and one of the addresses of the write data to the SSD 5. In this embodiment, for example, the address transmitted from the transmission unit 18 to the SSD 5 is a logical address.

The receiving unit 19 receives, from the SSD 5, block information including a logical address indicating valid data written to a block to be subjected to waste collection.

In this embodiment, the block information may include information related to the identification information of each block in the SSD 5 and the identification information of the data written to each block.

The writing unit 20 writes (transcribes) all or a part of the valid data indicated by the logical address included in the block information to the volatile memory based on the block information received from the SSD 5 and the management information 61 to 64. One of the 24 memory. For example, another memory can be a non-volatile cache memory 4.

For example, in the case of receiving a delete command, the writing unit 20 will indicate that one of the data of the data to be deleted (deletion candidate) is logical address from the logical bit indicating the valid data included in the block information. Site exclusion. Therefore, it is possible to select a valid material to be written to the block to be subjected to waste collection and not to be deleted. The writing unit 20 writes the selected material to another memory.

The transmission unit 21 generates deletion information including a logical address indicating the data to be deleted and transmits the deletion information to the SSD 5. For example, the deletion information may include a logical address indicating that the logical address of the valid data included in the block information indicates that the data is not written by the writing unit 20 to the deletion target of another memory. Instead of deleting the information, the maintenance information including the logical address of the data to be maintained may be transmitted from the transmission unit 21 to the SSD 5.

The SSD 5 includes a processor 22, a memory 23, and a non-volatile memory 24.

For example, the memory 23 stores various types of control data such as address translation information 32, valid/invalid information 33, and deletion information 34. The memory 23 can be a volatile memory such as a DRAM or an SRAM, or can be a non-volatile memory. The memory 23 can be included in the non-volatile memory 24.

The processor 22 acts as an address translation unit by executing a program stored in one of the memories in the processor 22, a program stored in the memory 23, or a program stored in the non-volatile memory 24. 25. A write unit 26, an enable/disable generating unit 27, a selecting unit 28, a transmitting unit 29, a receiving unit 30, and a waste collecting unit 31.

In this embodiment, for example, to cause the processor 22 to function as the address translation unit 25, the writing unit 26, the valid/invalid generating unit 27, the selecting unit 28, the transmitting unit 29, the receiving unit 30, and the garbage collecting unit. The program of 31 can be OS, intermediate software or firmware. In this embodiment, all of the address translation unit 25, the writing unit 26, the valid/invalid generating unit 27, the selecting unit 28, the transmitting unit 29, the receiving unit 30, and the waste collecting unit 31 may be implemented by hardware or portion.

When the self-cache control unit 9 receives the write data and the logical address of the write data, the address translation unit 25 generates a logical address for writing the data and a non-volatile memory for storing the written data. One of the locations in one of the 24 locations is related to the physical address and the information is temporarily stored in the address translation information 32.

In the present embodiment, the address translation unit 25 is implemented by the processor 22. However, the address translation unit 25 can be configured independently of the processor 22.

The address translation unit 25 translates the address based on, for example, the tabular address translation information 32. Instead, the address can be translated by a keyword-value search. For example, address translation can be implemented by means of a key-value search using a logical address as a key and a physical address as a value.

The writing unit 26 writes the write data to the location indicated by the physical address obtained by the address translation unit 25.

The valid/invalid generating unit 27 generates valid/invalid information 33 indicating whether each item of the data written to the non-volatile memory 24 is valid data or invalid data based on, for example, the address translation information 32. Then, the valid/invalid generating unit 27 will validate/invalidate the information. 33 is stored in the memory 23.

Selection unit 28 selects one of the blocks to be subjected to waste collection.

For example, selection unit 28 may select one of the blocks with the oldest write time from the block in non-volatile memory 24 as one of the blocks to be subjected to waste collection.

For example, selection unit 28 may randomly select a block to be subjected to waste collection from a block in non-volatile memory 24.

For example, the selection unit 28 may select one of the blocks having the largest amount of invalid data or having an amount of invalid data greater than a predetermined amount as one of the blocks to be subjected to waste collection based on the valid/invalid information 33.

For example, the selecting unit 28 may select, according to the valid/invalid information 33 and the deletion information 34, a block having the largest invalid data and the amount of data to be deleted or having more than a predetermined amount of invalid data and the amount of data to be deleted as to be subjected to One block of waste collection.

The transmission unit 29 generates the block information by deleting the logical address of the data indicating the one of the invalid data determined to be invalid by the valid/invalid information 33 from the instruction to the block to be subjected to the garbage collection. In other words, the block information includes information relating to the identification information of the block to be subjected to waste collection and the logical address indicating the valid data written to the block. The transmission unit 29 transmits the block information to the cache memory control unit 9.

The receiving unit 30 receives the deletion information from the cache memory control unit 9 and stores the deletion information 34 in the non-volatile memory 24.

The waste collection unit 31 automatically deletes the invalid data and the data to be deleted from the data to be subjected to the waste collection based on the valid/invalid information 33 and the deletion information 34 stored in the non-volatile memory 24, and is only for It is not the valid information of the data to be deleted to perform waste collection.

Figure 7 is a flow chart showing one of an example of a program executed by an information processing system in accordance with the present embodiment.

In step S701, the transmission unit 18 transmits the write data and a logical address to the SSD. 5.

In step S702, the address translation unit 25 receives the write data and the logical address, and temporarily stores the information related to the logical address of the write data and the physical address to the address translation information 32.

In step S703, the writing unit 26 writes the write data to a position in the non-volatile memory 24 indicated by the physical address.

In step S704, the valid/invalid generating unit 27 generates valid/invalid information 33 indicating whether each data item written to the non-volatile memory 24 is valid data or invalid data, and stores the valid/invalid information 33 in the memory. In body 23.

In step S705, the selection unit 28 selects one of the blocks to be subjected to waste collection.

In step S706, the transmission unit 29 generates by deleting the logical address of the data indicating that one of the invalid data indicated as invalid by the valid/invalid information 33 is instructed to be written to the block to be subjected to the garbage collection. The block information is transmitted to the cache control unit 9.

In step S707, the receiving unit 19 receives the block information from the SSD 5.

In step S708, the writing unit 20 writes all or a part of the data indicated by the logical address included in the block information to the SSD 5 based on the block information received from the SSD 5 and the management information 61 to 64. A memory other than the non-volatile memory 24.

For example, in the case that a delete command is received, the write unit 20 excludes the logical address included in the block information from the logical address indicating the data to be deleted, and indicates by the logical address. The data to be maintained is written to another memory.

In step S709, the transmission unit 21 transmits the deletion information including the logical address of the data to be deleted to the SSD 5.

In step S710, the receiving unit 30 receives the deletion information from the cache control unit 9 and stores the deletion information 34 in the memory 23.

In step S711, the waste collection unit 31 is based on the valid/invalid information 33 and the deletion resource. In addition, the invalid data and the data to be deleted are self-written to the data to be subjected to the waste collection, and the waste collection is performed for the valid data that is not to be deleted.

In the present embodiment set forth above, the cache control unit 9 can acquire information about the data written to one of the blocks of the non-volatile memory 24 from the SSD 5. The cache control unit 9 can thereby recognize the write status of one of the blocks in the non-volatile memory 24. For example, in this embodiment, it can be recognized whether the data written to the block of the non-volatile memory 24 is valid data or invalid data and whether the data can be deleted.

In this embodiment, the SSD 5 includes valid/invalid information 33 for determining whether the data is valid data or invalid data, and deletion information 34 for determining whether the data can be deleted. Thereby, it can be determined whether the erase is written to the material to be subjected to one of the waste collections when the waste collection is performed in the SSD 5. Therefore, an unnecessary data write can be avoided and the life of the non-volatile memory 24 can be increased.

In the present embodiment, the cache control unit 9 can prevent the deletion target data among the valid data indicated by the logical address included in the block information received from the SSD 5 from being transcribed from the non-volatile memory 24 to another Memory. In the present embodiment, the SSD 5 can delete data (for example, invalid data that can be deleted or valid data) that has not been transcribed from the cache control unit 9 to another memory from the SSD 5.

In the embodiment described above, the block information related to the block to be erased is transmitted from the SSD 5 to the information processing device 17. However, for example, the block information may include information relating each of the non-volatile memory 24 to the identification information of the data written to each of the blocks. The information processing device 17 can recognize the storage relationship between the block and the data in the SSD 5 by receiving the relationship information from the SSD 5.

[Third embodiment]

In the present embodiment, the information processing system 35 including the information processing system 17 and the SSD 5 explained in the first embodiment and the second embodiment is explained in further detail.

FIG. 8 is a diagram showing a detailed structure of one of the information processing systems 35 according to the present embodiment. A block diagram of an example.

The information processing system 35 includes an information processing device 17 and a memory system 37.

The SSD 5 according to the first embodiment and the second embodiment corresponds to the memory system 37.

The processor 22 of the SSD 5 corresponds to a CPU 43B.

The address translation information 32 corresponds to a LUT (Look Up Table) 45.

The memory 23 corresponds to a DRAM 47.

The information processing device 17 functions as a host device.

One of the controllers 36 of the memory system 37 includes a front end 4F and a rear end 4B.

The front end (host communication unit) 4F includes a host interface 41, a host interface controller 42, an encoding/decoding unit (Advanced Encryption Standard (AES)) 44, and a CPU 43F.

The host interface 41 communicates with the information processing device 17 to exchange requests (write commands, read commands, erase commands), LBA (Logical Block Addressing), and data.

The host interface controller (control unit) 42 controls communication of the host interface 41 based on the control of the CPU 43F.

The encoding/decoding unit 44 encodes the write data (plain text) transmitted from the host interface controller 42 in a data write operation. The encoding/decoding unit 44 decodes the encoded read data transmitted from the read buffer RB of the back end 4B in a data read operation. It should be noted that the transmission of the write data and the read data can be performed without using the encoding/decoding unit 44 in accordance with the temporary command.

The CPU 43F controls the above components 41, 42 and 44 of the front end 4F to control the entire function of the front end 4F.

The back end (memory communication unit) 4B includes a write buffer WB, a read buffer RB, a LUT 45, a DDRC 46, a DRAM 47, a DMAC 48, an ECC 49, a random generator RZ, a NANDC 50, and a CPU 43B.

The write buffer (write data transfer unit) WB temporarily stores the write data transmitted from the information processing device 17. Specifically, the write buffer WB temporarily stores the data straight Until it reaches a predetermined data size suitable for one of the non-volatile memories 24.

The read buffer (read data transfer unit) RB temporarily stores the read data read from the non-volatile memory 24. Specifically, the read buffer RB reconfigures the read data into an order suitable for the information processing device 17 (the order of the logical addresses LBA specified by the information processing device 17).

The LUT 45 is used to translate the logical address-LBA into one of the physical address PBA (physical block addressing).

DDRC 46 controls the double data rate (DDR) in DRAM 47.

The DRAM 47 stores, for example, one of the LUTs 45 non-volatile memory.

The direct memory access controller (DMAC) 48 transfers the write data and the read data via an internal bus IB. In Figure 8, only a single DMAC 48 is shown; however, controller 36 may include two or more DMACs 48. The DMAC 48 can be set in various locations within the controller 36.

The ECC (Error Correction Unit) 49 adds an error correction code (ECC) to the write data transmitted from the write buffer WB. When the read data is transferred to the read buffer RB, the ECC 49 corrects the read data read from the non-volatile memory 24 using the added ECC, if necessary.

In the data write operation, the random generator RZ (or scrambler) spreads the write data in a manner such that the write data is not biased toward a page or is not biased toward the non-volatile memory 24 In the direction of a word line. By distributing the written data in this manner, the number of writes can be standardized and the cell lifetime of the memory cell MC of the non-volatile memory 24 can be prolonged. Therefore, the reliability of the non-volatile memory 24 can be improved. Further, in the data reading operation, the read data read from the non-volatile memory 24 passes through the random generator RZ.

The NAND controller (NANDC) 50 uses a plurality of channels (four channels CH0 to CH3 are shown) to access the non-volatile memory 24 in parallel to meet one of a certain speed requirement.

The CPU 43B controls each of the above components (45 to 50 and RZ) of the back end 4B to control the entire function of the back end 4B.

It should be noted that the structure of the controller 36 is an example and is not intended to be limited thereby.

Figure 9 is a perspective view showing one of an example of a storage system according to the present embodiment.

A storage system 100 includes a memory system 37 as an SSD.

For example, the memory system 37 is externally sized to be a relatively small module of approximately 20 mm x 30 mm. It should be noted that the size and scale of the memory system 37 are not limited thereto and may be arbitrarily changed to various sizes.

Further, the memory system 37 can be applied to the information processing device 17 as one of a data center or a cloud computing system used in a company (enterprise) or the like. Therefore, the memory system 37 can be an enterprise SSD (eSSD).

For example, memory system 37 includes a plurality of connectors (eg, slots) 38 that are open upwardly. Each connector 38 is a serial attached SCSI (SAS) connector or the like. With the SAS connector, a high speed mutual communication can be established between the information processing device 17 and each of the memory systems 37 via one of 6 Gbps. It should be noted that the connector 38 can be a fast PCI (PCIe) or a fast NVM (NVMe).

A plurality of memory systems 37 are individually attached to the connector 38 of the information processing device 17 and supported in a configuration such that they stand in a generally vertical direction. With this configuration, the plurality of memory systems 37 can be collectively mounted in a compact size and the memory system 37 can be miniaturized. In addition, the shape of each memory system 37 of the present embodiment is a small footprint (SFF) of 2.5 inches. Due to this shape, the memory system 37 is compatible with an enterprise HDD (eHDD) and can achieve simple system compatibility with eHDD.

It should be noted that the memory system 37 is not limited to use in an enterprise HDD. For example, the memory system 37 can be used as a memory medium for a consumer electronic device such as a notebook type portable computer or a tablet terminal.

As can be understood from the above, the information processing system 35 having the structure of the embodiment and the storage The storage system 100 can achieve a large capacity storage advantage with the same advantages of the second embodiment.

The structure of the memory system 37 according to the present embodiment can be applied to the information processing apparatus 17 according to the first embodiment. For example, the processor 2 according to the first embodiment may correspond to the CPU 43B. The address translation information 7 may correspond to the LUT 45. The memory 3 corresponds to the DRAM 47. The non-volatile cache memory 4 may correspond to the non-volatile memory 24.

Although certain embodiments have been described, the embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments set forth herein may be embodied in a variety of other forms; and various omissions, substitutions and changes may be made in the form of the embodiments described herein without departing from the spirit of the invention. It is intended that the scope of the appended claims and their equivalents should

2‧‧‧ Processor

3‧‧‧ memory

4‧‧‧Non-volatile cache memory

5‧‧‧Solid Disk Drive

7‧‧‧ Address translation information

8‧‧‧ Address translation unit

9‧‧‧Cache Control Unit / Cache Memory / Cache Memory Control Unit

10‧‧‧Generating unit

11‧‧‧Control unit

12‧‧‧Control unit

13‧‧‧Control unit

14‧‧‧Control unit

15‧‧‧Change unit/first change unit

16‧‧‧Change unit / second change unit

17‧‧‧Information processing device

35‧‧‧Information Processing System

61‧‧‧Management Information/List

62‧‧‧Management Information

63‧‧‧Management Information

64‧‧‧Management Information/List

111‧‧‧Write unit/first write unit

112‧‧‧Decision unit/first decision unit

113‧‧‧Selection unit / first selection unit

114‧‧‧Decision unit/second decision unit

115‧‧‧Erase unit/first erase unit

121‧‧‧Write unit/second write unit

122‧‧‧Decision unit/fifth determination unit

123‧‧‧Selection unit / third selection unit

124‧‧‧Decision unit

125‧‧‧wiping unit/second erasing unit

131‧‧‧Write unit/third write unit

132‧‧‧Decision unit/third determination unit

133‧‧‧Selection unit / second selection unit

134‧‧‧Decision unit/fourth determination unit

135‧‧‧Write unit/fifth write unit

136‧‧‧Erasing unit/third erasing unit

137‧‧‧Write unit/sixth write unit

141‧‧‧Write unit/fourth write unit

142‧‧‧Decision unit/sixth determination unit

143‧‧‧Selection Unit / Fourth Selection Unit

144‧‧‧wiping unit/fourth erasing unit

B _1,1 ‧‧‧block/first erase unit area

B _1,K ‧‧‧block/first erase unit area

B _2,1 ‧‧‧block/second erase unit area

B _2,L ‧‧‧block/second erase unit area

B _3,1 ‧‧‧block/third erase unit area

B _3,M ‧‧‧block/third erase unit area

B _4,1 ‧‧‧block/fourth erase unit area

B _4,N ‧‧‧block/fourth erase unit area

BG ₁ ‧‧‧ Block Group / First Group

BG ₂ ‧‧‧ Block Group / Second Group

BG ₃ ‧‧‧ Block Group / Third Group

BG ₄ ‧‧‧ Block Group / Fourth Group

Claims (16)

A cache memory device, comprising: a non-volatile cache memory, comprising: a first group comprising a plurality of first erase unit regions, and one of a plurality of second erase unit regions a group and a third group including a plurality of third erasing unit areas, each of the first to third erasing unit areas including a plurality of writing unit areas; a first writing unit, Writing a data to the first group; a generating unit that generates management information indicating a usage state of one of the materials written to the first group; a first determining unit that determines the first group Whether the group satisfies a first erasing condition; a first selecting unit that selects a first to-be-erased area from the first group when the first group satisfies the first erasing condition; a second determination a unit, based on the management information, determining whether the data written to the first to-be-erased area is in a first high usage state or a first low usage state; and a second writing unit in which the data is Writing the material when it is determined to be in the first low use state To the second group; a third writing unit that writes the data to the third group when the data is determined to be in the first high usage state; and a first erasing unit The material written to the first area to be erased is erased. The cache device of claim 1, wherein the non-volatile cache memory further comprises a fourth group comprising one of a plurality of fourth erase unit regions, and The cache memory device further includes: a third determining unit that determines whether the third group satisfies a second erasing condition; and a second selecting unit that satisfies the second erasing in the third group Selecting a second to-be-erased area from the third group; a fourth determining unit determining, based on the management information, that the data written to the second to-be-erased area is in a second high use The state is still a second low use state; a fourth writing unit that writes to the second standby when the data written to the second to-be-erased area is determined to be in the second low-use state Writing the data of the erasing area to the fourth group; a fifth writing unit that again determines when the data written to the second to-be-erased area is determined to be in the second high-use state Writing the data written to the second area to be erased to the third group; and a second erasing unit erasing the material written to the second area to be erased. The cache device of claim 1, wherein the first determining unit determines that the first erasing condition is satisfied when the amount of data of the first group exceeds a predetermined amount. The cache device of claim 1, wherein the first selection unit selects the first to-be-erased region from the first group based on the first in first out. The cache device of claim 2, further comprising: a first changing unit that increases the first group when the data written to the second group reaches a third high usage state Include the number of the first erased unit regions and reduce the third erase unit regions included in the third group a number of domains; and a second changing unit that increases the third erasing unit area included in the third group when the data written to the fourth group reaches a fourth high usage state The number and the number of the first erase unit areas included in the first group are reduced. The cache device of claim 5, further comprising: a sixth writing unit that writes to the second when the data written to the second group reaches the third high usage state The data of the group is written to the third group. The cache device of claim 2, further comprising: a fifth determining unit that determines whether the second group satisfies a third erasing condition; and a third selecting unit in the second group Selecting a third to-be-erased area from the second group when the third erasing condition is satisfied; a third erasing unit erasing the data written to the third to-be-erased area; a determining unit, determining whether the fourth group satisfies a fourth erasing condition; a fourth selecting unit that selects a fourth from the fourth group when the fourth group satisfies the fourth erasing condition An area to be erased; and a fourth erasing unit that erases the material written to the fourth area to be erased. The cache device of claim 7, wherein the third selection unit selects to indicate the first write time or the first write time based on the first write time or the first write order of the plurality of second erase unit regions The first write order is the old erased unit area as the third to-be erased area, and The fourth selection unit selects an erase unit area indicating that the second write time or the second write order is old based on the second write time or the second write order of the plurality of fourth erase unit regions As the fourth to-be-erased area. A cache memory device, comprising: a non-volatile cache memory, comprising a plurality of erase unit regions, each of the erase unit regions comprising a plurality of write unit regions; a unit that writes data to the non-volatile cache memory; a determination unit that determines whether the plurality of erase unit regions meet an erase condition; and a selection unit that satisfies the plurality of erase unit regions When the erase condition is selected, an area to be erased is selected from the plurality of erase unit areas; and a erase unit erases the data written to the area to be erased. The cache device of claim 9, wherein the erasing condition is that the amount of data of one of the plurality of erased unit areas exceeds a predetermined amount. The cache device of claim 9, wherein the area to be erased is an area of one of the unit sizes erased, and the erase unit erases all of the data written to the area to be erased. The cache device of claim 9, further comprising: a generating unit that generates management information indicating a usage state of one of the materials written to the plurality of erasing unit regions; a maintenance determining unit based on Determining whether the data written to the area to be erased is maintained in the non-volatile cache memory; and a transfer write unit, the data written in the area to be erased is Determining that the data written to the area to be erased is written to the destination erased in the non-volatile cache memory when being maintained in the non-volatile cache memory Unit area. The cache device of claim 12, wherein the management information includes identification information of the data, information indicating whether the data is information to be deleted, and usage status information of the data. The cache device of claim 9, wherein the selection unit selects the write time or the write from the plurality of erase unit regions based on a write time or a write order of the plurality of erase unit regions The order is the old erased unit area as the area to be erased. The cache device of claim 9, wherein the selection unit randomly selects the region to be erased from the plurality of erase unit regions. A non-transitory computer readable recording medium, the storage of which causes a computer to function as one of: a writing unit that writes data to a non-volatile cache memory, the non-volatile cache memory Included in the plurality of erase unit regions, each of the erase unit regions includes a plurality of write unit regions; a determination unit that determines whether the plurality of erase unit regions meet an erase condition; a selection unit, Selecting an area to be erased from the plurality of erase unit areas when the plurality of erase unit regions satisfy the erase condition; and erasing the unit to erase the material written to the area to be erased.