TW201611199A - Reconfigured wide input/output memory module and package structure using same - Google Patents

Abstract

In some embodiments, it is desirable to increase memory bandwidth with a holistic solution. In an embodiment, wide I/O memory can be used. Embodiments of systems and methods for reconfiguring a wide I/O memory module are described herein. The reconfigured memory modules can be configured to cause the memory modules to function in conjunction with the current package architecture.

Description

Reconfigured wide input/output memory module and package structure using same

Embodiments described herein relate to semiconductor packages and methods for packaging semiconductor devices. More specifically, some of the embodiments disclosed herein relate to a package architecture suitable for a wide I/O memory module.

The standard for wide I/O (for example, for mobile DRAM, released in early 2012) uses 矽 via (TSV) to connect DRAM to logic on a three-dimensional integrated circuit. With its 512-bit data interface, the wide I/O single data rate (SDR) doubles the bandwidth of the low power dual data rate 2 specification without significantly increasing power consumption.

Devices using TSV connections between homogeneous grains are already available. Wide I/Os urgently require TSV connections between heterogeneous grains. By knowing a homogeneous TSV connection, a hundred-fold improvement in the delay per watt of die-to-die connectivity is required.

TSV technology with sufficient potential provides the ability to connect crystal grains with different physical properties. While it is possible to place logic, memory, radio frequency (RF), analog, power, and image sensing circuits on the same cymbal, it may be preferable to place them on separate dies to obtain the lowest cost. Best performance.

The wide I/O standard leverages 3D die stacking by greatly improving performance and power. By using low-speed, low-capacitance connections, wide I/O transfers data at approximately half the power per bit of some currently used standard. For example, wide I/O will be the same as many current standards. Power doubles the bandwidth without affecting the quality or volume of the cellular phone.

Disadvantageously, TSV technology develops more slowly than expected and TSV technology does not keep pace when wide I/O is fully developed. This has led to problems in how to utilize wide I/O technology until the TSV technology has evolved enough to utilize it.

In some embodiments, it is desirable to increase the memory bandwidth with a holistic solution. In an embodiment, wide I/O memory can be used. Embodiments of systems and methods for reconfiguring a wide I/O memory module are described herein. The reconfigured memory modules can be configured to cause the memory modules to function in conjunction with current or new package architectures.

100‧‧‧Standard Wide I/O Memory Module

110‧‧‧ channel

200‧‧‧wide I/O memory module

210‧‧‧ channel

210a‧‧‧ channel

210b‧‧‧ channel

210c‧‧‧ channel

210d‧‧‧ channel

220‧‧‧Substrate/RDL

240‧‧‧Electrical conductor

1100‧‧‧Semiconductor device package assembly

1110‧‧‧ grain

1120‧‧‧Substrate

1122‧‧‧Bottom

1125‧‧‧Substrate

1130‧‧‧First set of electrical conductors

1140‧‧‧ first surface

1150‧‧‧ second surface

1160‧‧‧Second set of electrical conductors

1170‧‧‧ memory module

1170a‧‧‧Reconfigure Wide I/O Memory Module

1170b‧‧‧Reconfigure Wide I/O Memory Module

1175‧‧‧Electrical conductor

1180‧‧‧through hole

1185‧‧‧PCB strip

1190‧‧‧Package

1200‧‧‧矽 Spacer/heat spreader

1202‧‧‧epoxy resin or thermal interface material

1210‧‧‧Electrical conductor

1250‧‧‧矽 bridge

The following detailed description refers to the accompanying drawings, which are briefly described.

Figure 1 depicts an embodiment of a standard wide I/O memory module that includes four channels.

2 depicts an embodiment of two relatively small wide I/O memory modules including two channels each positioned towards an edge of the module.

3 depicts an embodiment of a wide I/O memory module that includes four channels, with the two channels flipped toward the edge. .

4A-4B depict an embodiment of a standard wide I/O memory module that includes four channels and a post-manufacture redistribution layer (RDL) coupled to the module.

5A-5B depict an embodiment of a standard wide I/O memory module that includes four channels and a fan-out wafer level package (FOWLP) including an RDL coupled to the module.

Figure 6 depicts an embodiment of two relatively small wide I/O memory modules including two channels each positioned towards the edge of the module, coupled to the RDL of the module.

Figure 7 depicts an embodiment of two relatively small wide I/O memory modules including two channels each positioned towards the edge of the module, in combination with a FOWLP coupled to the RDL of the module.

Figure 8 depicts an embodiment of a package having a plurality of separate wide I/O memory modules, such The module is coupled to the package using a redistribution layer (RDL).

9 depicts an embodiment of a package having a plurality of separate wide I/O memory modules coupled to the package using a germanium insert or PCB strip positioned in the package.

10A-10B depict an embodiment of a package having a plurality of wide I/O memory modules configured in a fan-out wafer level package (FOWLP), the fan-out wafer level package including A monospaced I/O memory module is coupled to the RDL of the package.

11 depicts an embodiment of a package having a wide I/O memory module configured in a FOWLP that includes an RDL for coupling the wide I/O memory module to the package.

12 depicts an embodiment of a package having a wide I/O memory module that includes a post- fabrication RDL coupled to the package via a via through a via.

Figure 13 depicts an embodiment of a package having a wide I/O memory module coupled to the bottom surface of the package via the RDL of the package.

14 depicts an embodiment of a package including a die coupled to a heterogeneous RDL and a plurality of separate wide I/O memory modules.

Figure 15 depicts an embodiment of a package having a wide I/O memory module that includes a post-manufacture RDL.

16 depicts an embodiment of a package including a die and a plurality of separate wide I/O memory modules that use a 矽 bridge coupler positioned between the package RDL and the die and memory module Connected to the die.

17 depicts an embodiment of a package including a die and a plurality of separate wide I/O memory modules that are positioned on a side of the package RDL that is opposite the die and memory module. The 矽 bridge is coupled to the die.

Figure 18 depicts an embodiment of a package including a die and a memory module coupled to the die using a post- fabrication RDL.

Particular embodiments are shown by way of example in the drawings and will be described in detail herein. Of course It should be understood, however, that the drawings are not intended to be limited Rather, the invention is to cover all modifications, equivalents, and alternatives that are obvious to those skilled in the art. The examples of features provided in the present invention are intended to be illustrative and not restrictive.

The headings used herein are for organizational purposes only and are not intended to limit the scope of the description. The word "may" as used throughout this application is used in the sense of meaning (i.e., meaning possible) rather than mandatory (i.e., meaning necessary). The word "include, includes, and includes" indicates an open relationship and is therefore meant to include (but not limited to). Similarly, the word "have, having, and has" also indicates an open relationship and thus means (but is not limited to). The terms "first," "second," "third," and the like, as used herein, are used as a mark for the nouns that follow, and do not imply any type of order (eg, space, time, logic, etc.), Unless the order is otherwise explicitly specified. For example, unless otherwise specified, "the third die electrically connected to the module substrate" does not exclude the situation in which the "fourth die electrically connected to the module substrate" is connected before the third die. Similarly, the "second" feature does not require the implementation of the "first" feature prior to the "second" feature unless otherwise specified.

The various components can be described as "configured to" perform one or more tasks. In such cases, "configured to" is a broad reference that generally means "having a structure that performs one or more tasks during operation." Thus, even when the component is not currently performing a task, the component can be configured to perform the task (eg, even when the two modules are not connected, a set of electrical conductors can be configured to electrically connect one module to another) group). In some cases, "configured to" may be a broad reference to a structure that generally means "a circuit having one or more tasks performed during operation." Therefore, the component can be configured to perform tasks even when the component is not currently turned on. In general, a circuit forming a structure corresponding to "configured to" may include a hardware circuit.

For ease of description, various components may be described as performing one or more tasks. These descriptions should be interpreted to include the phrase "configured to". The description of a component configured to perform one or more tasks is expressly intended to exclude the interpretation of the component in 35 U.S.C. § 112, paragraph (f).

The scope of the present invention includes any feature or combination of features (either explicitly or implicitly) disclosed herein, or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, the new technical solution may be formulated as any such combination of features during the review of this application (or the application claiming its priority). In particular, with reference to the scope of the accompanying claims, the features from the sub-claims can be combined with the features of the individual items, and the features from the individual items can be in any suitable manner and not only as listed in the accompanying claims A combination of specific combinations.

This description includes references to "an embodiment". The appearances of the phrase "in an embodiment" are not necessarily referring to the same embodiment. Specific features, structures, or characteristics may be combined in any suitable manner consistent with the present invention.

In some embodiments, it is desirable to increase the memory bandwidth with a holistic solution. In an embodiment, wide I/O memory can be used. Embodiments of systems and methods for reconfiguring a wide I/O memory module are described herein. The reconfigured memory modules can be configured to cause the memory modules to function in conjunction with the current package architecture. In some embodiments, a standard wide I/O memory module can include a set of electrical conductors that are substantially centered within a memory module that is remote from the edge. In some embodiments, a standard wide I/O memory module can include a set of electrical conductors configured in at least four channels. In some embodiments, a reconfigured wide I/O memory module can be formed such that it is smaller than a standard wide I/O memory module. In some embodiments, the reconfigured wide I/O memory module can include a set of electrical conductors positioned substantially along the edge. In some embodiments, the reconfigured wide I/O memory module can include a set of electrical conductors configured in at least two channels. In some embodiments, the reconfigured wide I/O memory module can include any design, structure, or process changes to existing memory dies/wafers to change Memory module pad (or bump) position and/or pitch, number of channels, and/or die size. In some embodiments, wide I/O may refer herein to a wide I/O or a wide I/O2 or a wide I/O3 as defined by the JEDEC Solid State Technology Association standards and publications.

FIG. 1 depicts an embodiment of a standard wide I/O memory module 100 that includes four channels 110. The four channels can include electrical connectors of different groups. Electrical connectors can be used to electrically connect the memory module 100 to other electrical components. However, this type of standard configuration is designed to be used with TSVs in a stacked 3D package architecture. As mentioned, TSV is a viable technology to be grown. For example, one problem with the standard memory configuration depicted in Figure 1 is the long channel length configuration for electrical contacts used with non-TSV-based current architectures. For example, one problem with the standard memory configuration depicted in Figure 1 is the central configuration for electrical contacts used with non-TSV-based current architectures. Responding at least to these questions, the reconfigured wide I/O memory module can be formed into smaller units to provide flexibility so that the reconfiguration unit is properly placed in the module to reduce the memory The body module is electrically coupled to other electrical components and the channel length of the electrical contacts that improve the signal integrity (SI) performance of the system. The reconfigured memory module can include one or more channels positioned as electrical conductors adjacent one or more edges of the memory module. 2 depicts an embodiment of two relatively reconfigured relatively small wide I/O memory modules 200 that include two channels 210 each positioned toward an edge of the module.

The current electrical contact/channel configuration of the wide I/O memory module demonstrates that the package SI performance is due in part to its IO position and partly due to the precise IO spacing (approximately 40μm to 60μm), which limits Fan out configuration. In some embodiments, the reconfigured wide I/O memory module can relocate the channels of the electrical contacts to reduce congestion and vacate routing paths between the reconfigured memory modules and other electronic components. 3 depicts an embodiment of a reconfigured wide I/O memory module 200 that includes four channels 210a through 210d, with two channels 210a through 210b flipped toward the edge of the memory module.

In some embodiments, a post-manufacture substrate (eg, RDL) can be used to reposition the IO pad To improve SI performance and increase the bump pitch of the wide I/O memory module (eg, from about 40 [mu]m to about 80 [mu]m) to achieve routing flexibility. 4A-4B depict an embodiment of a reconfigured wide I/O memory module that includes four channels, wherein the post-manufacture RDL 220 of each channel 210 is coupled to the memory module. The spacing of the memory modules 200 can be increased using a larger pitch set of RDL 220 and RDL of the electrical conductors 240. Electrical conductor 240 may be optional in some embodiments.

In some embodiments, fan-out wafer level technology (eg, FOWLP) can be used to redistribute I/O to standard wide I/O such as the I/O shown in FIG. 2 or reconfigured wide I/O to It facilitates the location of the PoP package routing and increases the bump pitch of the wide I/O memory module (eg, from about 40 μm to about 80 μm). The substrate can electrically connect the electrical connectors in the memory module to the electrical connectors of the substrate positioned around the edges. 5A-5B depict an embodiment of a standard wide I/O memory module 200 that includes four channels 210 that include a substrate 220 (eg, a FOWLP including RDL) coupled to the module.

Several different strategies have been disclosed herein that are dedicated to reconfiguring standard wide I/O memory modules to function better with current non-TSV package architectures. In some embodiments, a plurality of different embodiments can be combined in a single embodiment to further increase the efficiency of electronic components employing reconfigured memory modules. (FIG. 6 needs to be revised to make it more representative.) FIG. 6 depicts an embodiment of a relatively small wide I/O memory module 200 that includes two or two that are each positioned toward the edge of the module. More than one channel 210 is coupled to the RDL 220 of the module. 7 depicts an embodiment of two relatively small wide I/O memory modules 200 including two or more channels 210 each positioned toward an edge of the module, the coupling including coupling to the mode Group of FDLLP for RDL 220.

FIG. 8 depicts an embodiment of a semiconductor device package assembly 1100 that includes a die 1110 and a substrate 1120. In some embodiments, substrate 1120 can include an item commonly referred to as a redistribution layer (RDL). The substrate 1120 can include a first set of electrical conductors 1130 coupled to the first surface 1140 of the substrate. The first set of electrical conductors 1130 can be configured to electrically connect the semiconductor device seal Assembly assembly 1100. The die 1110 can be electrically connected to the second surface 1150 of the substrate 1120 using a second set of electrical conductors 1160. In some embodiments, electrical conductor 1160 can be optional, or it can be part of substrate 1120. In some embodiments, the second surface 1150 can be substantially opposite the first surface 1140 of the substrate 1120. Assembly 1100 can include at least one reconfigured wide I/O memory module 1170. In some embodiments, the reconfigurable memory module can include an electrical conductor positioned toward an edge of the module. The memory module 1170 can be positioned in a plane substantially above the die 1110. In some embodiments, the memory module 1170 can be coupled to the substrate 1120 using vias 1180. In some embodiments, the reconfigured memory module 1170 can include a substrate (eg, a post-manufacture RDL, not shown in the figure). The substrate can couple the memory module 1170 to the via 1180 via bumps or balls and then be coupled to the substrate 1120. In some embodiments, the reconfiguration memory module 1170 can be a FOWLP. In some embodiments, mechanical bumps or balls can be added to the module 1170 to achieve mechanical balance. A primer 1122 may be present to protect the solder bumps and memory module 1170. The substrate can convert the pitch of the electrical conductors of the memory module 1170 (for example, about 40 μm) into the distance between the vias 1180 (for example, about 80 μm). The via 1180 can connect the memory module 1170 to the substrate 1120 via the package 1190. The die 1110 can be exposed or fully embedded in the package 1190. In some embodiments, the assembly 1100 can include a 矽 spacer/thermal spreader 1200.

In some embodiments, the primer 1122 can comprise an electrically insulating material. The electrically insulating material can comprise a dielectric polymer. In some embodiments, the method can include inhibiting deformation of the semiconductor device package assembly using the dielectric polymer.

In some embodiments, the memory module 1170 can be coupled to the substrate 1120 using vias 1180. The via 1180 can include a pitch (eg, about 40 [mu]m) that is substantially equal to the distance between the electrical conductors of the memory module 1170. The via 1180 can connect the memory module 1170 to the substrate 1120 via a germanium insert or PCB strip 1185 positioned in the package 1190. In some embodiments, the assembly 1100 can include a 矽 spacer/thermal spreader 1200. 9 depicts an embodiment of a package having a plurality of separate wide I/O memory modules 1170 that are positioned for use in a package The 矽 insert 1185 is coupled to the package in 1100.

In some embodiments, one or more reconfigured wide I/O memory modules 1170 can be used to include a substrate 1125 (eg, RDL) and to couple the wide I/O memory module to the die The FOWLP of the third set of electrical conductors 1210 is coupled to the die 1110. 10A-10B depict an embodiment of a package 1100 having a plurality of separate wide I/O memory modules 1170 that are configured to couple a wide I/O memory module to The grain of RDL 1125 is in the FOWLP. 11 depicts an embodiment of a package 1100 having a wide I/O memory module 1170 that is configured to include an RDL 1125 for coupling the wide I/O memory module to the die. In FOWLP. The substrate 1125 can couple the memory module 1170 to the via 1180 and then be coupled to the substrate 1120. The substrate 1125 can convert the pitch of the electrical conductors of the memory module 1170 (for example, about 40 μm) into the pitch of the vias 1180 (for example, about 80 μm). The via 1180 can connect the memory module 1170 to the substrate 1120 via the package 1190. The memory module 1170 can be at least substantially enclosed to cover the two memory modules 1170 (eg, as depicted in FIG. 10A) or cover the entire surface except the memory module 1170 (eg, as shown in FIG. 10B). Depicted in the package 1190.

12 depicts an embodiment of a package 1100 having a wide I/O memory module 1170 that includes a substrate 1120 coupled to the package via vias through the package 1190. In some embodiments, substrate 1120 can include an item commonly referred to as post-manufacture RDL 1120. The substrate 1120 can include a first set of electrical conductors 1130 coupled to the first surface 1140 of the substrate. The first set of electrical conductors 1130 can be configured to electrically connect the semiconductor device package assembly 1100. The die 1110 can be electrically connected to the second surface 1150 of the substrate 1120 using a second set of electrical conductors 1160. Electrical conductor 1160 can be part of substrate 1120. Assembly 1100 can include a wide I/O memory module 1170. The memory module 1170 can include a post- fabrication RDL layer that fan-divides the pad pitch from a smaller pitch (about 40 [mu]m) to a larger pitch (about 80 [mu]m). The memory module 1170 can be positioned on a plane substantially above the die 1110. In some embodiments, the memory module 1170 can be coupled to the substrate 1120 using vias 1180. The through hole 1180 can include substantially equal to the record The spacing between the electrical conductors 1175 of the memory module 1170 (eg, about 80 μm). The via 1180 can connect the memory module 1170 to the substrate 1120 via the package 1190. In some embodiments, the assembly 1100 can include a 矽 spacer/thermal spreader 1200. The helium spacer or heat spreader 1200 can be attached to the package via epoxy or thermal interface material 1202.

13 depicts an embodiment of a package 1100 having a wide I/O memory module 1170 that is coupled to a first side 1140 of a substrate 1120 via a substrate 1120 (eg, RDL) of the package. In some embodiments, the memory module 1170 can include at least two smaller memory modules, including positioning toward an edge of the memory module as depicted in FIG. 13 (eg, reducing the memory module and The connection distance between the dies is the electrical conductor 1210. In some embodiments, package 1100 can include an optional via 1180. The via 1180 can be configured into a second package of the package 1100 in a stacked package configuration. The through hole 1180 can be positioned in the package 1190.

14 depicts an embodiment of a package 1100 that includes a die 1110 coupled to a substrate 1120 and a plurality of reconfigured wide I/O memory modules 1170. In some embodiments, substrate 1120 can include an item commonly referred to as a heterogeneous RDL. The substrate 1120 can include a first set of electrical conductors 1130 coupled to the first surface 1140 of the substrate. The first set of electrical conductors 1130 can be configured to electrically connect the semiconductor device package assembly 1100. The die 1110 can be electrically connected to the second surface 1150 of the substrate 1120 using a second set of electrical conductors 1160. In some embodiments, the second surface 1150 can be substantially opposite the first surface 1140 of the substrate 1120. Assembly 1100 can include a plurality of reconfigured wide I/O memory modules 1170a through 1170b. The memory module 1170 can be electrically coupled to the substrate 1120 using a third set of electrical conductors 1210. The die 1110 and the memory module 1170 can be positioned adjacent to each other on the substrate 1120. The die 1110 and the memory module 1170 can be at least substantially enclosed in the package 1190.

FIG. 15 depicts an embodiment of a package 1100 having a wide I/O memory module that includes a substrate 1120. In some embodiments, substrate 1120 can include a heterogeneous RDL. In some embodiments, the memory module 1170 can contain a post-manufacture RDL layer (not shown). Electrical conductor 1160 and electrical conductor 1210 can be optional or can be part of substrate 1120.

In some embodiments, the reconfigured memory module 1170 can be electrically coupled to the die 1110 using a germanium bridge 1250. The 矽 bridge can be configured to connect the I/O pads of the memory module to the I/O pads of the die 1110. 16 depicts an embodiment of a package 1100 that includes a die 1110 and a plurality of reconfigured wide I/O memory modules 1170 that are positioned on the package substrate 1120 and the die 1110 and the memory module. A 矽 bridge 1250 between 1170 is coupled to the die. 17 depicts an embodiment of a package 1100 that includes a die 1110 and a plurality of reconfigured wide I/O memory modules 1170a through 1170b that are coupled to a die 1110 using a germanium bridge 1250, the germanium bridge Positioned on the side of the package substrate 1120 opposite the die 1110 and the memory 1170.

In some embodiments, the 矽 bridge 1250 is a hapten formed from a larger 矽 wafer. For example, a germanium wafer can be processed (eg, patterned) to form a plurality of bond line patterns, with each pattern corresponding to a separate germanium bridge. The germanium wafer can then be separated (eg, diced) to produce a plurality of germanium bridges, each of which contains a pattern of connecting lines. In some embodiments, the ankle bridge 1250 can be formed at least in part from a material other than the crucible. The bridge can be formed from a substrate material.

In some embodiments, the 矽 bridge 1250 is coupled to the die 1110 and the memory module 1170 by electrical connectors. In some embodiments, the electrical connector includes a solder interconnect. In some embodiments, the electrical connector comprises a copper or gold interconnect. The patterned connections in the 矽 bridge 1250 can have extremely precise interconnect trace spacing. For example, the traces can have an interconnect pitch of up to about 1 [mu]m. In some embodiments, the traces have an interconnect pitch between about 0.5 μm and about 1 μm, between 0.25 μm and about 1 μm, or between about 0.1 μm and about 1 μm.

18 depicts an embodiment of a package 1100 that includes a die 1110 and a memory module 1170 that is coupled to the die using a fabricated RDL 1125. In some embodiments, the memory module can include wide I/O memory or DDR memory. Memory module 1170 between bumps The distance can be increased to 80 μm via the post-manufacturing RDL. The DDR memory module can be coupled to the package 1100 or the wide I/O die-stack package can be coupled to the package 1100 using the RDL 1125 and the via 1180.

Numerous variations and modifications will become apparent to those skilled in the art of the present disclosure. The scope of the following patent application is intended to be construed as covering all such changes and modifications.

200‧‧‧ relatively small wide I/O memory module

210‧‧‧ channel

Claims (20)

A memory module includes: a memory module including a memory and at least two channels positioned adjacent to an edge of the memory module, wherein each channel includes a set of electrical connectors, A separate interface on the isoelectric connector interacts with the respective sub-portions of the memory. The memory module of claim 1, wherein the channels are electrically coupled to a substrate, the substrate being configured to adjust a distance and/or a position of the channels relative to the memory module. The memory module of claim 1, wherein the at least two channels are positioned adjacent to a single edge of the one of the memory modules. The memory module of claim 1, wherein the at least two channels are positioned adjacent to the edge of the memory module such that a longitudinal axis of each channel is substantially parallel to the edge. The memory module of claim 1, wherein at least two of the channels are positioned adjacent to the edge of the memory module such that one of the channels is substantially parallel to the edge. The memory module of claim 1, wherein the memory module comprises at least four channels such that at least one of the channels is substantially parallel to the edge, and wherein the at least four channels are not Along a longitudinal axis of each channel is positioned adjacent to each other. The memory module of claim 1, wherein the memory module further comprises a redistribution layer coupled to at least one of the channels. The memory module of claim 1, wherein the memory module further comprises a second substrate coupled to at least one of the channels, and wherein the redistribution layer Configuring to increase a spacing of the electrical connectors of the at least one channel. The memory module of claim 1, wherein the memory module further comprises a second substrate coupled to the first channel of at least one of the channels, and wherein the redistribution layer is configured The distance between the electrical connector of the at least one channel and the electrical connector of the second channel is increased. A semiconductor device package assembly comprising: a first package assembly comprising: a first substrate including one coupled to a first surface and configured to electrically connect the semiconductor device package assembly The first set of electrical conductors. a first die comprising a third surface electrically coupled to a second surface of the first substrate opposite the first surface of the first substrate; and at least one memory module Included in the memory and at least two channels positioned adjacent to an edge of the memory module, wherein each channel includes a set of electrical connectors on which an independent interface and the memory are separate And a portion of the interaction, wherein the memory module is coupled to a fourth surface of the first die of the first package assembly, wherein the fourth surface is opposite to the third surface of the die. The semiconductor device package assembly of claim 10, wherein the at least one memory module is coupled to the first substrate using a via. The semiconductor device package assembly of claim 10, wherein the at least one memory module comprises electrically coupling the at least one memory module to the second substrate of the first substrate via the via. The semiconductor device package assembly of claim 12, wherein the vias electrically connect the memory module to the first substrate via an electrically insulating material. The semiconductor device package assembly of claim 12, further comprising electrically coupling the second substrate to one of the second vias of the vias. The semiconductor device package assembly of claim 13, wherein the second substrate converts a pitch of the second set of electrical conductors of the memory module to a pitch of the vias. The semiconductor device package assembly of claim 10, further comprising coupling the memory module to an electrically insulating material of the first package assembly. The semiconductor device package assembly of claim 10, further comprising at least two memory modules, wherein the at least two memory modules are coupled to the first of the first die of the first package assembly Four surfaces. The semiconductor device package assembly of claim 17, further comprising a spacer coupled between the at least two of the memory modules coupled to the fourth surface. The semiconductor device package assembly of claim 17, further comprising a thermal spreader coupled to the fourth surface and positioned between at least two of the memory modules. The semiconductor device package assembly of claim 10, wherein the at least two channels are positioned adjacent the edge of the memory module such that a longitudinal axis of each channel is substantially parallel to the edge.