TW201611182A - Method of forming air gap between conductive lines - Google Patents

Abstract

A method of forming air gap between conductive lines includes forming a SiN liner on surfaces of conductive line structures on a substrate, forming an ultra-thin poly silicon liner covering the SiN liner, and then forming a photoresist in a plurality of trenches between the conductive line structures, wherein a top surface of the photoresist is under that of the conductive line structures. Thereafter, an oxide film is conformally formed to cover the photoresist and a surface of the ultra-thin poly silicon liner, and oxide spacers are formed on sidewalls of the conductive line structures on the photoresist by anisotropic etching the oxide film. Afterwards, the photoresist is removed to expose the ultra-thin poly silicon liner in the trenches, and then the exposed ultra-thin poly silicon liner is removed by using the oxide spacers as mask. The oxide spacers are removed and an oxidation is performed on the remaining ultra-thin poly silicon liner so as to convert it into a silicon oxide layer and close upper portions of the trenches.

Description

Method of forming an air gap between wires

The present invention relates to a technique for improving parasitic capacitance between wires, and more particularly to a method of forming an air gap between wires.

The development of semiconductor components has reached tens of nanometers or less, but as the line pitch of semiconductor wire structures has been greatly reduced, the increased parasitic capacitance has adverse effects.

Therefore, the current improvement has a material that deposits a lower dielectric constant (k) value (such as an oxide) in the space between the two-conductor structure to replace the tantalum nitride, but such a method cannot satisfy the development of the component to 30 nm. The design after the Mi Shidai. Therefore, there has recently been a space between two conductor structures to form an air gap to replace oxides because air has the lowest dielectric constant (k). For the formation of air gaps, part of the study was to deposit a non-conformal dielectric material on the wire, or to use a nanoparticle having a particle size larger than the line spacing on the wire to close the space between the wires.

However, the above method may form a highly inconsistent air gap, or The problem of filling the nanoparticles between the wires.

The present invention provides a method of forming an air gap between wires to form a uniform air gap.

In a method of forming an air gap between wires in accordance with the present invention, a substrate having a plurality of wire structures formed thereon is provided, wherein each wire structure includes at least a conductor layer and a cap layer on top of the conductor layer. A tantalum nitride liner is formed on the surface of the wire structure, and a polysilicon ultrathin liner is formed on the wire structure to cover the tantalum nitride liner. Then, the trench between the wire structures is filled with photoresist, and then part of the photoresist is removed, so that the top surface of the photoresist is lower than the top surface of the wire structure. Thereafter, an oxide layer is conformally formed over the wire structure to cover the surface of the photoresist and the polysilicon ultrathin liner. Next, the oxide layer is anisotropically etched to form an oxide spacer on the sidewall of the wire structure above the photoresist, and then the photoresist is removed to expose the polysilicon ultrathin liner in the trench. Then, using the oxide spacer as a mask, the exposed polycrystalline ultra-thin liner is removed, and the oxide spacer is removed to expose the remaining polycrystalline ultra-thin liner. Next, the polycrystalline silicon ultrathin liner is oxidized to be converted into a ruthenium oxide layer and the upper portion of the trench is closed.

In an embodiment of the invention, the method of removing a portion of the photoresist includes controlling a top surface of the photoresist above a conductor layer.

In an embodiment of the invention, the method of removing a portion of the photoresist includes controlling a top surface of the photoresist to be between 10% and 50% of a thickness of the cap layer.

In an embodiment of the invention, the polycrystalline germanium ultrathin liner has a thickness of less than 10 nm.

In an embodiment of the invention, the method of removing the exposed polysilicon ultrathin liner comprises wet etching.

In an embodiment of the invention, the method for removing a portion of the photoresist includes chemical mechanical polishing of the photoresist until the top surface is exposed, and etching the photoresist.

In an embodiment of the invention, a method of conformally forming an oxide layer on the above-described wire structure includes atomic layer deposition (ALD).

In an embodiment of the invention, the method for oxidizing the polycrystalline germanium ultrathin liner comprises radical oxidation or low-temperature wet oxidation.

In an embodiment of the invention, the polycrystalline germanium ultrathin liner may be epitaxially grown to increase its thickness prior to the oxidized polysilicon ultrathin liner.

In an embodiment of the invention, the thickness of the polysilicon ultrathin liner is increased by 1.5 times to 2 times after performing the epitaxy.

Based on the above, the present invention can precisely control the height of the air gap by controlling the top surface of the photoresist, and the sealing of the air gap can be completed by the oxidation of the polycrystalline silicon ultra-thin lining on the upper part of the wire structure, thereby achieving the effect of reducing the parasitic capacitance.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Substrate

102‧‧‧Wire structure

104‧‧‧Conductor layer

106‧‧‧ cover

108a, 116a‧‧‧ top

108b‧‧‧ sidewall

110‧‧‧ nitrided lining

112, 112a‧‧‧ Polycrystalline silicon ultra-thin lining

114‧‧‧ditch

116‧‧‧Light resistance

118‧‧‧Scope

120‧‧‧Oxide layer

120a‧‧‧Oxide spacer

122‧‧‧Oxide layer

124‧‧‧Air gap

200‧‧‧ Polycrystalline germanium epitaxial layer

S1, S2, S3‧‧‧ distance

T1, t2, t3, t4‧‧‧ thickness

1A through 1J are schematic cross-sectional views showing a manufacturing process for forming an air gap between wires in accordance with an embodiment of the present invention.

2 is a schematic cross-sectional view showing another process of the embodiment of the present invention.

The embodiments of the present invention are shown in the accompanying drawings. However, the invention may be practiced in many different forms and should not be construed as being limited to the embodiments described. Rather, the embodiments are provided so that this disclosure will be thorough and complete, and the scope of the invention will be fully conveyed to those of ordinary skill in the art.

In the drawings, the dimensions and relative dimensions of the various layers and regions may be exaggerated for clarity.

1A through 1J are schematic cross-sectional views showing a manufacturing process for forming an air gap between wires in accordance with an embodiment of the present invention.

Referring to FIG. 1A, a plurality of wire structures 102 are formed on a substrate 100. Since the figure is shown in cross section, the wire structure 102 is, for example, a linear structure extending over the substrate 100, but the invention is not limited thereto. Each wire structure 102 includes at least a conductor layer 104 and a cap layer 106 on top of the conductor layer 104. The conductor layer 104 may be a single layer or a multilayer structure, and a portion in contact with the substrate 100 may be provided with a gate oxide layer. The material of the cap layer 106 is a non-conductor material such as tantalum nitride. The conductor layer 104 is protected during subsequent processing. At this time, the distance S1 between the wire structures 102 is a line space; for example, the embodiment can be applied to the semiconductor process in the nano generation, so the distance S1 is about several tens of nanometers, such as 40 Below the meter.

Then, referring to FIG. 1B, a tantalum nitride liner 110 is formed on the substrate 100, and the thickness thereof is only a few nanometers, so that the top surface 108a and the sidewall 108b of the structure in FIG. 1B can be completely covered. At this time, the distance S2 is further shortened than the distance S1 in FIG. 1A.

Next, referring to FIG. 1C, a polysilicon ultrathin liner 112 is formed to cover the tantalum nitride liner 110. In the present embodiment, the so-called polysilicon ultrathin liner 112 refers to an ultrathin film having a thickness t1 of 10 nm or less, and the thickness t1 is basically determined by the distance S1 of FIG. 1A, preferably about 3 nm to 5 nm. In the meantime, the formation method is, for example, using silane as a raw material or using a disilane having a relatively high reaction rate as a raw material to form a dense and flat ultrathin film. After the polysilicon ultrathin liner 112 is formed, the width of the trench 114 (i.e., the distance S3) is further reduced.

Then, referring to FIG. 1D, the trenches 114 between the wire structures 102 are filled with the photoresist 116, and the photoresist 116 is formed on the substrate 100, for example, by coating.

Next, referring to FIG. 1E, a portion of the photoresist 116 is removed such that the top surface 116a of the photoresist 116 is lower than the top surface 108a. Moreover, because the location of the top surface 116a will affect the height of the subsequently formed air gap, the top surface 116a of the photoresist 116 can be further controlled above the conductor layer 104. For example, the top surface 116a of the photoresist 116 can be controlled within a range 118 between 10% and 50% of the thickness t2 of the cap layer 106. As for the method of removing a portion of the photoresist 116, for example, the photoresist 116 of FIG. 1D is chemically mechanically polished until the top surface of the polysilicon ultrathin liner 112 is exposed, and the photoresist 116 is etched back.

Thereafter, referring to FIG. 1F, an oxide layer 120 is conformally formed on the wire structure 102 to cover the surface of the photoresist 116 and the polysilicon ultrathin liner 112. A method of forming the oxide layer 120 is, for example, atomic layer deposition (ALD), and the temperature of the deposition process is, for example, between 60 ° C and 80 ° C.

Next, referring to FIG. 1G, the oxide layer 120 of FIG. 1F is anisotropically etched to form an oxide spacer 120a on the sidewall 108b of the wire structure 102 above the photoresist 116, and expose the top and the portion of the polysilicon ultra-thin liner 112. Photoresist 116.

Then, referring to FIG. 1H, all the photoresists 116 are removed, and the polysilicon ultra-thin liner 112 in the trenches 114 is exposed, and then the oxide spacers 120a are used as a mask, for example, by wet etching or the like. The exposed polysilicon ultrathin liner 112 is exposed until the tantalum nitride liner 110 within the trench 114 under the oxide spacer 120a is exposed. Since the wet etching is an isotropic etching, the polysilicon ultrathin liner 112a covered by the oxide spacer 120a is slightly retracted.

Then, referring to FIG. 1I, the oxide spacers in FIG. 1H are removed to expose the remaining polysilicon ultra-thin liner 112a.

Next, referring to FIG. 1J, the polysilicon ultra-thin liner 112a of FIG. 1I is oxidized to be transformed into the ruthenium oxide layer 122. Since the volume is expanded by about 1.6 times after oxidation, the ruthenium oxide layer 122 can close the upper portion of the trench. An air gap 124 is formed between the wire structures 102. A method of oxidizing the polycrystalline germanium ultrathin liner 112a such as radical oxidation or low-temperature wet oxidation to completely convert the polycrystalline germanium ultrathin liner 112a to hafnium oxide at a lower temperature Layer 122, but the invention is not limited thereto.

As can be seen from FIG. 1J, there is no other structure between the wire structures 102 except the tantalum nitride liner layer 110, so even if the semiconductor line pitch is gradually reduced, the effective distance of the air gap 124 can be ensured, and in this embodiment, By controlling the height of the top surface 116a when removing a portion of the photoresist 116, an air gap 124 having a position and height can be produced in a subsequent step.

In addition, the polycrystalline silicon ultrathin liner 112a in FIG. 1I may have a thickness t3 which may not close the space between the cap layers 106 after oxidation, so that the polycrystalline germanium ultrathin liner 112a may be first exposed. The crystal is increased in thickness by the grown polycrystalline germanium epitaxial layer 200. The steps of Figure 1J can then be performed. During the epitaxial deposition, since the structures of the substrate 100 and the conductor layer 104 are covered by the tantalum nitride liner 110, the epitaxial layer is not grown. After the epitaxy, the thickness t4 of the polycrystalline silicon ultra-thin liner is increased by, for example, 1.5 times to 2 times, but the present invention is not limited thereto.

In summary, the method of the present invention can control the height of the air gap by the photoresist and help seal the air gap by oxidizing the polysilicon ultrathin liner located on the upper portion of the wire structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Substrate

102‧‧‧Wire structure

104‧‧‧Conductor layer

106‧‧‧ cover

108b‧‧‧ sidewall

112‧‧‧Polysilicon ultra-thin lining

116‧‧‧Light resistance

120a‧‧‧Oxide spacer

Claims (10)

A method of forming an air gap between wires, comprising: providing a substrate on which a plurality of wire structures are formed, wherein each of the wire structures includes at least a conductor layer and a cap layer on top of the conductor layer; Forming a tantalum nitride liner on the surface of the wire structure; forming a polysilicon ultra-thin liner on the wire structure to cover the tantalum nitride liner; filling the trench between the wire structures with a photoresist; Removing a portion of the photoresist such that a top surface of the photoresist is lower than a top surface of the wire structure; forming an oxide layer conformally on the wire structure, covering the photoresist and the polysilicon thin a surface of the liner; anisotropically etching the oxide layer to form an oxide spacer on the sidewall of the wire structure above the photoresist; removing the photoresist to expose the inside of the trench a polysilicon ruthenium liner; removing the exposed polysilicon ultrathin liner with the oxide spacer as a mask; removing the oxide spacer to expose the polysilicon ultrathin liner; and oxidizing The polycrystalline silicon ultrathin liner Turn it into a silicon oxide layer and an upper portion of said closed trench. A method of forming an air gap between wires as described in claim 1, wherein the method of removing a portion of the photoresist comprises controlling the top surface of the photoresist Above the conductor layer. A method of forming an air gap between wires according to claim 2, wherein the method of removing a portion of the photoresist comprises controlling the top surface of the photoresist to be 10 of a thickness of the cap layer Between %~50%. A method of forming an air gap between wires according to claim 1, wherein the polysilicon ultrathin liner has a thickness of 10 nm or less. A method of forming an air gap between wires as described in claim 1, wherein the method of removing the exposed polysilicon ultrathin liner comprises wet etching. A method of forming an air gap between wires according to claim 1, wherein the method of removing a portion of the photoresist comprises: chemical mechanical polishing the photoresist until the polysilicon ultrathin liner is exposed a top surface; and etch back the photoresist. A method of forming an air gap between wires as described in claim 1, wherein the method of conformally forming the oxide layer on the wire structure comprises atomic layer deposition (ALD). A method of forming an air gap between wires according to claim 1, wherein the method of oxidizing the polysilicon ultrathin liner comprises a radical oxidation method or a low temperature wet oxidation method. The method of forming an air gap between wires according to claim 1, wherein before oxidizing the polysilicon ultrathin liner, the epitaxial layer of the polysilicon ultrathin liner is further included to increase the polysilicon. The thickness of the ultra-thin liner. The method of forming an air gap between wires according to claim 9, wherein the thickness of the polysilicon ultrathin liner is increased by 1.5 times to 2 times after the epitaxing.