TW201616203A - Display panel - Google Patents

Abstract

A display panel includes a first substrate, a second substrate and an electrode layer. The second substrate is disposed opposite the first substrate. The electrode layer is disposed between the first substrate and the second substrate and includes a first main interval portion and a plurality of first sub-interval portions. The first main interval portion has a first side, and the first main interval portion and the first sub-interval portions connect to each other at the first sided. A first branch electrode is disposed between the adjacent two of the first sub-interval portions, and the adjacent two of the first sub-interval portions are parallel to each other. A width of the main interval portion is greater than or equal to 1[mu]m and less than or equal to 4[mu]m.

Description

Display panel

The present invention relates to a display panel.

With the advancement of technology, flat display devices have been widely used in various fields, especially liquid crystal display devices. Due to their superior characteristics such as slimness, low power consumption and no radiation, they have gradually replaced traditional cathode ray tube display devices. It is applied to many kinds of electronic products, such as mobile phones, portable multimedia devices, notebook computers, LCD TVs and LCD screens.

At present, manufacturers of liquid crystal display devices have a stable polymer alignment (or polymer continuous alignment, Polymer Sustained Alignment, on the Multi-domain Vertical Alignment (MVA) of a thin film transistor liquid crystal display device (TFT LCD). PSA) is a technology for improving the maturity and mass production of optical properties such as aperture ratio and contrast. Among them, the PSA technology is in the panel of the One Drop Filling (ODF) process, after mixing a photoreactive monomer (monomer), and then performing ultraviolet light exposure to make the photoreactive single in the liquid crystal molecule. The body generates a chemical reaction, and the monomers after the chemical reaction are arranged according to the electric field provided by the transparent conductive layer on the thin film transistor substrate to pass the polymerized monomer to achieve the purpose of aligning the liquid crystal.

In addition, in the same brightness, the high transmittance display panel can make the display device more power-saving. Therefore, various manufacturers are working hard to improve the transmittance of the display panel to achieve power saving. The competitiveness of its products. Among them, the pattern design of the transparent conductive layer on the thin film transistor substrate is also one of the factors affecting the transmittance of the display panel, especially when the resolution (ppi) of the panel is higher and higher, in order to make the panel have higher penetration. The rate, the pattern of the transparent conductive layer is also one of the factors to be explored.

In view of the above problems, it is an object of the present invention to provide a display panel. It can improve the penetration rate, thereby saving power and facilitating the development of high-resolution display products.

To achieve the above object, a display panel according to the present invention comprises a first substrate, a second substrate, and an electrode layer. The second substrate is disposed opposite to the first substrate. The electrode layer is located between the first substrate and the second substrate and includes a first main spacer and a plurality of first spacers. The first main spacer has a first side. The first main spacer is connected to the first spacers at a first side, and the first of the first spacers has a first branch electrode, and the first spacers are The neighbors are parallel to each other. One of the first main spacers has a width of 1 μm or more and 4 μm or less.

In an embodiment, the electrode layer further includes a plurality of second spacers. The first main spacer has a second side, and the second spacer is connected to the first main spacer at the second side. A second branch electrode is disposed between adjacent ones of the second spacers, and adjacent ones of the second spacers are parallel to each other. The first spacers are alternately arranged with the second spacers.

In an embodiment, the first time intervals are arranged corresponding to the second time intervals.

In an embodiment, the electrode layer further includes a second main spacer and a plurality of third spacers. The second main spacer is disposed to intersect with the first main spacer and has a third side. The second main spacer is connected to the third spacer at a third side, and a third branch electrode is disposed between adjacent ones of the third spacers, and the third spacers are The neighbors are parallel to each other. Wherein the width of one of the second main spacers is greater than or equal to 1 micrometer and less than or equal to 4 micrometers.

In an embodiment, the electrode layer further includes a plurality of fourth spacers. The second main spacer has a fourth side, and the fourth spacer is connected to the second main side at the fourth side. A fourth branch electrode is disposed between adjacent ones of the fourth spacers, and adjacent ones of the fourth spacers are parallel to each other. The third spacers are alternately arranged with the fourth spacers.

In an embodiment, the third time interval portions are disposed corresponding to the fourth time interval portions.

In an embodiment, the first main spacer and the second main spacer have a cross shape.

In an embodiment, the width of the first main spacer and the second main spacer are the same Or not the same.

In one embodiment, one of the first spacers has a width between 0.5 microns and 5 microns.

In one embodiment, the electrode layer further includes a connection electrode that is looped and connected to the first branch electrodes.

As described above, in the display panel of the present invention, the electrode layer includes a first main spacer and a plurality of first spacers, and the first main spacer and the first spacer are at the first main interval One of the first side edges is connected to each other, and a first branch electrode is disposed between adjacent ones of the first time intervals, and adjacent ones of the first time intervals are parallel to each other, and the first main interval One of the widths is greater than or equal to 1 micrometer and less than or equal to 4 micrometers. By verification, by setting the first main spacer and when the width of the first main spacer is greater than or equal to 1 micrometer and less than or equal to 4 micrometers, the cross shading of the pixel can be reduced, and the pixel penetration rate is improved. In turn, it achieves power saving and is conducive to the development of high-resolution display products.

1, 3‧‧‧ display panel

11‧‧‧First substrate

12‧‧‧second substrate

13, 13a, 13b‧‧‧ electrode layer

131‧‧‧First main compartment

132‧‧‧First Interval

133‧‧‧Second interval

134‧‧‧Second main compartment

135‧‧‧ third interval

136‧‧‧ Fourth Interval

14‧‧‧Liquid layer

2‧‧‧Display device

4‧‧‧Backlight module

A1~A4‧‧‧ quadrant

CE‧‧‧Connecting electrode

D1, D2, D3‧‧‧ width

E‧‧‧Light

E1‧‧‧ first branch electrode

E2‧‧‧Second branch electrode

E3‧‧‧third branch electrode

E4‧‧‧fourth branch electrode

S1‧‧‧ first side

S2‧‧‧ second side

S3‧‧‧ third side

S4‧‧‧ fourth side

1 is a schematic view of a display panel in accordance with a preferred embodiment of the present invention.

2 is a partial schematic view of an electrode layer according to an embodiment of the present invention.

3 is a schematic view of an electrode layer according to another embodiment of the present invention.

4 is a schematic view of an electrode layer according to another embodiment of the present invention.

FIG. 5 is a schematic diagram of a display device according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a display panel and a display device according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings, wherein the same elements will be described with the same reference numerals.

1 is a schematic view of a display panel 1 in accordance with a preferred embodiment of the present invention. As shown in FIG. 1 , the display panel 1 of the present embodiment includes a first substrate 11 , a second substrate 12 , and an electrode layer 13 . The display panel 1 of the present embodiment is, for example but not limited to, an in-plane switch (IPS) liquid crystal display panel, a fringe field switching (FFS) liquid crystal display panel, and a vertical alignment mode. , VA mode) Liquid crystal display panel or 3D liquid crystal display panel is not limited. In addition, the display panel 1 of the embodiment is also Polymer Sustained Alignment (PSA) technology can be applied. In addition, the display panel 1 is applied to, for example, a smart phone, a tablet computer, or other electronic device, and when light passes through the display panel 1, the image can be formed by displaying the color of each (secondary) pixel of the display panel 1.

The first substrate 11 is disposed opposite to the second substrate 12, and a liquid crystal layer 14 (not shown liquid crystal molecules) is disposed between the first substrate 11 and the second substrate 12. The first substrate 11 and the second substrate 12 can be made of a light transmissive material, and is, for example, a glass substrate, a quartz substrate or a plastic substrate, which is not limited thereto.

The display panel 1 further includes a thin film transistor array, a color filter array, and a black matrix layer (not shown). The thin film transistor array is disposed on the first substrate 11, and the color filter array or the black matrix layer can be It is disposed on the first substrate 11 or the second substrate 12. The thin film transistor array, the color filter array and the liquid crystal layer 14 can form a pixel array. In an embodiment, the black matrix layer and the color filter array may be disposed on the second substrate 12. However, in another embodiment, the black matrix layer or the color filter array may also be disposed on the first substrate 11. It is made into a BOA (BM on array) substrate or a COA (color filter on array) substrate, which is not limited herein. In addition, the display panel 1 may further include a plurality of scan lines and a plurality of data lines (not shown) interlaced with the data lines and defined, for example, perpendicular to each other to define an area of the pixel array. The pixel array includes a plurality of pixels, and the second pixels are arranged in a matrix.

The electrode layer 13 is located between the first substrate 11 and the second substrate 12. In the present embodiment, the electrode layer 13 is disposed on the first substrate 11 and faces the second substrate 12, but the present invention is not limited thereto. The electrode layer 13 is a transparent conductive layer, such as, but not limited to, indium-tin oxide (ITO) or indium-zinc oxide (IZO). In this embodiment, the electrode layer 13 is a pixel electrode layer of the display panel 1 and is electrically connected to a data line (not shown). 2 is a partial schematic view of an electrode layer 13 according to an embodiment of the present invention. Here, FIG. 2 only shows a part of the electrode layer 13 of FIG. 1 (still indicated as 13), and is a pixel element of the sub-pixel of the display panel 1.

The electrode layer 13 includes a first main spacer 131 and a plurality of first spacers 132. The first main spacer 131 has a first side S1. First main spacer 131 and some The first spacers 132 are connected to each other at the first side S1. The first of the first spacers 132 has a first branch electrode E1, and the adjacent ones of the first spacers 132 Parallel to each other. The width D1 of one of the first main spacers 131 is greater than or equal to 1 micrometer and less than or equal to 4 micrometers. In addition, in the present embodiment, the width D3 of one of the first spacers 132 is exemplified between 0.5 micrometers and 5 micrometers.

The electrode layer 13 further includes a plurality of second spacers 133. The first main spacers 131 have a second side S2, and the second spacers 133 are connected to the first main spacers 131 at the second side S2. A second branch electrode E2 is disposed between adjacent ones of the second spacers 133, and adjacent ones of the second spacers 133 are parallel to each other. In the present embodiment, one of the widths of the second spacers 133 is exemplified between 0.5 micrometers and 5 micrometers. The first spacing portion 132 and the second spacing portions 133 are alternately disposed. In this embodiment, the first spacing portion 132 is disposed corresponding to the second branch electrode E2, and the second spacing portion 133 is disposed corresponding to the first branch electrode E1, such that the first spacing portion 132 and the first spacing portion 132 are These second spacers 133 are alternately arranged. It should be noted that in other embodiments, the first spacer 132 may be disposed only partially corresponding to the second branch electrode E2, and the second spacer 133 may be disposed only partially corresponding to the first branch electrode E1.

In addition, the electrode layer 13 may further include a second main spacer 134 and a plurality of third spacers 135. The second main spacing portion 134 is disposed to intersect the first main spacing portion 131 and has a third side S3. In the present embodiment, the first main spacer 131 and the second main spacer 134 are disposed to intersect each other and have a cross shape. The second main spacing portion 134 is connected to the third sub-space portions 135 at a third side S3, and a third branch electrode E3 is disposed between adjacent ones of the third sub-space portions 135. The adjacent two of the three spacers 135 are parallel to each other. In the present embodiment, one of the third spacers 135 has a width of between 0.5 micrometers and 5 micrometers as an example. The width D2 of one of the second main spacers 134 is greater than or equal to 1 micrometer and less than or equal to 4 micrometers. In addition, in the present embodiment, the widths D1 and D2 of the first main spacing portion 131 and the second main spacing portion 134 may be the same or different, and the two are the same.

Further, the electrode layer 13 may further include a plurality of fourth spacers 136. The second main spacing portion 134 has a fourth side S4, and the fourth main spacing portion 136 is connected to the second main spacing portion 134 at the fourth side S4, and the second spacing portion 136 is adjacent to the second side Have a fourth The electrode E4 is branched, and adjacent ones of the fourth spacers 136 are parallel to each other. In the present embodiment, one of the widths of the fourth spacer 136 is exemplified between 0.5 micrometers and 5 micrometers.

The third spacers 135 are alternately arranged with the fourth spacers 136. In this embodiment, the third spacing portion 135 is disposed corresponding to the fourth branch electrode E4, and the fourth spacing portion 136 is disposed corresponding to the third branch electrode E3, such that the third spacing portion 135 and the The fourth spacers 136 are alternately arranged. It should be noted that in other embodiments, the third spacer 135 may be disposed only partially corresponding to the fourth branch electrode E4, and the fourth spacer 136 may be disposed only partially corresponding to the third branch electrode E3.

Further, from another point of view, the first main spacer portion 131 and the second main spacer portion 134 of the present embodiment divide the electrode layer 13 into four quadrants A1, A2, A3, and A4. Each of the quadrants A1, A2, A3, and A4 has a sub-spacer and a branch electrode, and the sub-spacer is connected to the side of the main spacer, and the sub-interval has a branch electrode. Further, the secondary spacers and the branch electrodes of the respective quadrants are parallel to each other. In this embodiment, the four quadrants A1 to A4 are taken as an example, and the display panel 1 of the present embodiment is applied with a multi-domain vertical alignment (MVA) technology. However, the invention is not limited thereto. In addition, in the embodiment, in the quadrant A1, there is also a branch electrode between the first spacer 132 and the third spacer 135, which may be defined as a first branch electrode or a third branch electrode; Quadrants A2, A3, and A4 can be deduced by analogy.

In other words, the electrode layer 13 of the present embodiment has no trunk electrode arrangement in one (secondary) pixel. By verification, by the arrangement of the first and second main spacers 131, 134 and when the widths D1, D2 of the main spacers are greater than or equal to 1 micrometer and less than or equal to 4 micrometers, the cross shading of the pixels can be reduced, thereby improving The penetration rate of the pixels, which in turn achieves power saving and facilitates the development of high-resolution display products. Through verification, in the present embodiment, when the widths D1 and D2 are equal to 4 micrometers, the pixel transmittance can be increased by 2.3%, and when the widths D1 and D2 are equal to 3 micrometers, the pixel transmittance can be increased by 5.4%. When the widths D1 and D2 are equal to 2 micrometers, the pixel transmittance can be increased by 6.7%. When the widths D1 and D2 are equal to 1 micrometer, the pixel transmittance can be increased by 5.2%.

In addition, the pattern of the electrode layer 13 of the present embodiment may have different variations, which are exemplified below.

FIG. 3 is a schematic view of an electrode layer 13a according to another embodiment of the present invention. Figure 3 The first and second spacers 132 of the electrode layer 13a are disposed corresponding to the second spacers 133, and the third spacers 135 and the fourth The secondary spacers 136 are correspondingly arranged.

4 is a schematic view of an electrode layer 13b according to another embodiment of the present invention. As shown in FIG. 4, the main difference from the electrode layer 13 is that the electrode layer 13b further includes a connection electrode CE, which is connected to and connected to the first branch electrode E1, and in this embodiment, the connection electrode CE is further looped and The second branch electrode E2, the third branch electrode E3, and the fourth branch electrode E4 are connected. By setting the connection electrode CE, the signal of the pixel electrode can be provided more easily, and the product yield can be improved.

It should be noted that the technical features of the above embodiments may be implemented separately or in combination, and there is no limitation thereto.

FIG. 5 is a schematic diagram of a display device 2 according to an embodiment of the invention. As shown in FIG. 5, the display device 2 includes a display panel 3 and a backlight module 4 (Backlight Module). The display panel 3 is disposed opposite to the backlight module 4. The display panel 3 can have the features of the display panel 1 and its variations, and will not be described here. When the light E emitted from the backlight module 4 passes through the display panel 3, the color can be displayed through the pixels of the display panel 3 to form an image.

In summary, in the display panel of the present invention, the electrode layer includes a first main spacer and a plurality of first spacers, and the first main spacer and the first spacer are at the first main interval One of the first side edges is connected to each other, and a first branch electrode is disposed between adjacent ones of the first time intervals, and adjacent ones of the first time intervals are parallel to each other, and the first main interval One of the widths is greater than or equal to 1 micrometer and less than or equal to 4 micrometers. By verification, by setting the first main spacer and when the width of the first main spacer is greater than or equal to 1 micrometer and less than or equal to 4 micrometers, the cross shading of the pixel can be reduced, and the pixel penetration rate is improved. In turn, it achieves power saving and is conducive to the development of high-resolution display products.

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

13‧‧‧Electrode layer

131‧‧‧First main compartment

132‧‧‧First Interval

133‧‧‧Second interval

134‧‧‧Second main compartment

135‧‧‧ third interval

136‧‧‧ Fourth Interval

A1~A4‧‧‧ quadrant

D1, D2, D3‧‧‧ width

E1‧‧‧ first branch electrode

E2‧‧‧Second branch electrode

E3‧‧‧third branch electrode

E4‧‧‧fourth branch electrode

S1‧‧‧ first side

S2‧‧‧ second side

S3‧‧‧ third side

S4‧‧‧ fourth side

Claims (10)

A display panel includes: a first substrate; a second substrate, the second substrate is opposite to the first substrate; and an electrode layer between the first substrate and the second substrate, the electrode layer The method includes: a first main spacer having a first side; and a plurality of first spacers, wherein the first main spacer is connected to the first spacers on the first side, and the first A first branch electrode is disposed between adjacent ones of the first spacers, and adjacent ones of the first spacers are parallel to each other; wherein one of the first main spacers has a width greater than or equal to 1 micrometer and less than Equal to 4 microns. The display panel of claim 1, wherein the electrode layer further comprises: a plurality of second spacers, the first main spacer has a second side, the second spacers and the second a main spacer is connected to the second side, and a second branch electrode is disposed between the two adjacent spacers, and adjacent ones of the second spacers are parallel to each other; The first spacer is alternately disposed with the second spacers. The display panel of claim 1, wherein the electrode layer further comprises: a plurality of second spacers, the first main spacer has a second side, the second spacers and the second a main spacer is connected to the second side, and a second branch electrode is disposed between the two adjacent spacers, and adjacent ones of the second spacers are parallel to each other; The first spacer is provided corresponding to the second spacers. The display panel of claim 1, wherein the electrode layer further comprises: a second main spacer, intersecting with the first main spacer, and having a third side; and a plurality of third a second spacer portion, wherein the second main spacer portion is connected to the third side spacer portion, and a third branch electrode is disposed between adjacent ones of the third sub-space portions The adjacent ones of the three spacers are parallel to each other; wherein one of the second main spacers has a width of 1 μm or more and 4 μm or less. The display panel of claim 4, wherein the electrode layer further comprises: a fourth plurality of spacers, the second main spacers having a fourth side, the fourth spacers being connected to the second side of the fourth side, the fourth spacers There is a fourth branch electrode between the two adjacent electrodes, and adjacent ones of the fourth time intervals are parallel to each other; wherein the third time interval portions are alternately arranged with the fourth time interval portions. The display panel of claim 4, wherein the electrode layer further comprises: a plurality of fourth spacers, the second main spacer has a fourth side, the fourth spacers and the The two main spacers are connected at a fourth side, and the fourth of the fourth spacers have a fourth branch electrode therebetween, and the adjacent ones of the fourth spacers are parallel to each other; The third spacer is disposed corresponding to the fourth spacers. The display panel of claim 4, wherein the first main spacer and the second main spacer have a cross shape. The display panel of claim 4, wherein the width of the first main spacer and the second main spacer are the same or different. The display panel of claim 1, wherein one of the first spacers has a width between 0.5 micrometers and 5 micrometers. The display panel of claim 1, wherein the electrode layer further comprises a connecting electrode that is looped and connected to the first branch electrodes.