TW201603665A - Printed circuit board, method for manufacturing the same, and packaged package therewith - Google Patents

Abstract

A printed circuit board attached to a surface of a substrate, and a first electronic component is attached to the surface. The printed circuit board includes at least one insulating layer and the insulating layer has a cavity that houses at least a portion of the first electronic component, and the cavity has an inner surface that is formed of an insulating material.

Description

Printed circuit board, method for manufacturing the same, and packaged package therewith

The present disclosure relates to a printed circuit board, a method for fabricating the same, and a package on package having the same.

Electronic technology recently used adhesive technology (mounting) Technology) Adhesive technology is a multi-layer printed circuit board that has the ability to achieve high densification and high integration in terms of fixed components, in order to achieve miniaturization and thinning of electronic devices. The multilayer printed circuit board has components for application, such as microcircuits, bumps, and the like, to achieve high density and high integration. Recently, semiconductor packages have been actively developed, and semiconductor packages are assembled into packages by pre-adhesive electronic components on a printed circuit board, such as system in package (SIP), wafers. A chip sized package (CSP), a flip chip package (FCP). In addition, there is a need for a control device and a memory device in a package on package (POP) in a single package form, thereby reducing the high performance. Smart phones and improve their performance.

One aspect of the present disclosure can provide a printed circuit board, a method for fabricating the same, and a laminated package having the same, which has a bridge that simply reduces external connection ends and achieves fine pitch ( Fine pitch) ability.

One aspect of the disclosure may also provide a printed circuit board, a method for fabricating the same, and a stacked package having the same, the printed circuit board having the ability to reduce the overall thickness of the package.

According to one aspect of the present disclosure, a printed circuit board can be provided, the printed circuit board is connected to a surface of a substrate and includes at least one insulating layer, the substrate has a first electronic component, and the first electronic component is fixed on the surface, wherein At least one insulating layer has a cavity formed therein, the cavity housing at least a portion of the first electronic component, and the cavity having an inner surface, made of an insulating material.

The cavity may have a concave shape formed in a lower surface of one of the insulating layers.

The printed circuit board may further include a connection pad formed in the insulating layer and the connection pad being separated from the cavity.

The connection pads may have a thickness equal to or less than one of the insulating layers.

The cavity may have an entire inner surface made of the same material as the insulating layer.

According to another aspect of the disclosure, a method for fabricating a printed circuit board can include forming a cavity pattern on a carrier substrate; forming an insulating layer at a carrier substrate to embed the cavity pattern; removing the carrier substrate; and removing the cavity pattern to form a cavity.

In forming the cavity pattern, when the cavity pattern is formed, a connection pad may be further formed on the carrier substrate.

According to another aspect of the disclosure, a package may include: a lower package including a lower package substrate and a first electronic component, the first electronic component being disposed on the lower package substrate; and an upper package substrate including at least one insulation a layer, the insulating layer has a cavity formed therein, the cavity accommodating at least a portion of the first electronic component, and the cavity has an inner surface formed of an insulating material; and an external connection end formed on the lower package substrate and the upper package substrate The upper and lower package substrates are electrically connected to each other. In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

100‧‧‧Printed circuit board

110‧‧‧Connecting mat

120‧‧‧ cavity pattern

121‧‧‧ cavity

130‧‧‧Insulation

131‧‧‧First insulation

135‧‧‧Second insulation

140‧‧‧first through hole

150‧‧‧Inner circuit pattern

160‧‧‧second through hole

170‧‧‧Outer circuit pattern

180‧‧‧protection layer

190‧‧‧ surface treatment layer

195‧‧‧External connection

210‧‧‧Under package substrate

211‧‧‧Insulation

212‧‧‧ circuit pattern

220‧‧‧First electronic components

230‧‧‧Upper package substrate

240‧‧‧Second electronic components

250‧‧‧First molded component

260‧‧‧Second molded component

300‧‧‧Stacked package

310‧‧‧Package

320‧‧‧First external connection

330‧‧‧Upper package

340‧‧‧Second external connection

500‧‧‧ Carrier substrate

510‧‧‧ Carrier core

520‧‧‧metal layer

530‧‧‧Anti-plating agent

531, 541‧‧‧ openings

540‧‧‧etching resist

The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description and the accompanying drawings, wherein: FIG. 1 illustrates a printed circuit board according to an exemplary embodiment of the present disclosure. 2 through 16 are schematic views showing a method for manufacturing a printed circuit board according to an exemplary embodiment of the present disclosure; and FIG. 17 is a schematic view showing a stacked package according to an exemplary embodiment of the present disclosure.

The objectives, features, and other advantages of the present disclosure will be more apparent from the description of the appended claims. Throughout the drawings, the same reference numerals are used to refer to the same or similar elements, and the redundant description is omitted. Furthermore, in the following description, the names "first", "second", "one side", "the other side" and the like are used to distinguish specific components from other components, but the assembly of such components should not It is understood to be limited to these names. In addition, in the description of the disclosure, the detailed description of the prior art will obscure the gist of the disclosure, and the description thereof will be omitted.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a printed circuit board in accordance with an exemplary embodiment of the present disclosure.

Although not shown, the printed circuit board 100 according to an exemplary embodiment of the present disclosure is attached to a surface of a substrate to which an electronic component is attached. The printed circuit board 100 described above includes at least one insulating layer 130. The insulating layer 130 includes a cavity 121 that accommodates at least a portion (not shown) of the electronic component, and the inner surface of the cavity 121 is made of an insulating material.

Referring to FIG. 1 , a printed circuit board 100 according to an exemplary embodiment of the present disclosure includes an insulating layer 130 , a connection pad 110 , an inner layer circuit pattern 150 , an outer layer circuit pattern 170 , a first through hole 140 , and a second through hole 160 . And a protective layer 180.

According to an exemplary embodiment of the present disclosure, the insulating layer 130 may be made of a composite polymer resin, and the composite polymer resin is generally used as an interlayer insulating layer. material. For example, the insulating layer 130 may be an Ajinomoto Build up Film (ABF), and an epoxy resin such as FR-4 or Bismaleimide Triazine (BT). Or made of similar materials. However, in the exemplary embodiment of the present disclosure, the material forming the insulating layer 130 is not limited thereto. The material forming the insulating layer 130 according to an exemplary embodiment of the present disclosure may be selected from insulating materials known in the field of circuit boards.

According to an exemplary embodiment of the present disclosure, the insulating layer 130 is divided into a first insulating layer 131 and a second insulating layer 135. The second insulating layer 135 is formed on the first insulating layer 131.

In the first embodiment, the first insulating layer 131 and the second insulating layer 135 are made of the same material. However, the exemplary embodiments of the present disclosure are not limited to the example in which the first insulating layer 131 and the second insulating layer 135 are made of the same material. For example, the first insulating layer 131 is made of an insulating material including glass fibers, and the second insulating layer 135 is made of an insulating material that does not include glass fibers. As such, the materials forming the first insulating layer 131 and the second insulating layer 135 may be changed according to the choice of those having ordinary skill in the art.

According to an exemplary embodiment of the present disclosure, the first insulating layer 131 has a cavity 121 which is a trench having a predetermined depth from a lower surface of the first insulating layer 131 to an inner portion thereof. That is, according to an exemplary embodiment of the present disclosure, the cavity 121 is formed in a recessed form in the lower portion of the first insulating layer 131. According to an exemplary embodiment of the present disclosure, when the package package is formed, at least a portion (not shown) of the electronic components of the lower package are housed in the cavity 121. Therefore, according to the disclosure The cavity 121 of the exemplary embodiment has a dimension to accommodate at least a portion of the electronic component therein. Here, although not shown, the cavity 121 accommodates the electronic component in a state in which the cavity 121 is spaced apart from the electronic component by a predetermined interval. Further, according to an exemplary embodiment of the present disclosure, the cavity 121 is formed in the first insulating layer 131, and the entire inner surface of the cavity 121 is made of an insulating material. That is, the inner surface of the cavity 121 can be represented as being made of the first insulating layer 131.

Further, according to an exemplary embodiment of the present disclosure, as shown in FIG. 1, the cavity 121 has a depth which is smaller than the thickness of the first insulating layer 131.

According to an exemplary embodiment of the present disclosure, the connection pads 110 are buried in the first insulating layer 131. Although FIG. 1 illustrates an example in which the connection pads 110 are formed on the left and right sides of the cavity 121, the connection pads 110 may surround the side edges of the cavity 121.

According to an exemplary embodiment of the present disclosure, the connection pad 110 has a thickness equal to or thinner than the first insulating layer 131. Here, the connection pad 110 according to the exemplary embodiment of the present disclosure has a thickness corresponding to the depth of the cavity 121. For example, as shown in FIG. 1, the connection pads 110 have a thickness that is the same as the depth of the cavity 121. Here, the name "the same" means that the name is "substantially same". That is to say, the name "identical" means to consider the name "identical" in which an error or offset occurs during the process.

According to an exemplary embodiment of the present disclosure, as shown in FIG. 1, the connection pad 110 has a thickness that is thicker than other circuit patterns.

The connection pad 110 according to an exemplary embodiment of the present disclosure may have a metal layer formed thereunder. The metal layer 520 is formed under the connection pad 110 and has There is a structure protruding from the first insulating layer 131.

The connection pad 110 and the metal layer 520 according to the exemplary embodiment of the present disclosure are made of copper (Cu). However, the material of the connection pad 110 and the metal layer 520 is not limited to copper, and any material may be used as long as it is a conductive material used in the field of a circuit board.

According to an exemplary embodiment of the present disclosure, the inner layer circuit pattern 150 is formed in the insulating layer 130. For example, the inner layer circuit pattern 150 may be formed on the first insulating layer 131 and buried in the second insulating layer 135. Although an example in which the inner layer circuit pattern 150 is formed in a single layer is illustrated and described in accordance with the exemplary embodiments of the present disclosure, the disclosure is not limited thereto. That is, the inner layer circuit pattern 150 according to the exemplary embodiment of the present disclosure may be formed in several layers of two or more layers according to the selection of those having ordinary knowledge in the art.

According to an exemplary embodiment of the present disclosure, the outer layer circuit pattern 170 is formed on the second insulating layer 135.

The inner layer circuit pattern 150 and the outer layer circuit pattern 170 according to the exemplary embodiments of the present disclosure may be made of copper. However, the materials of the inner layer circuit pattern 150 and the outer layer circuit pattern 170 are not limited to copper, and any material may be used as long as it is a conductive material used in the field of circuit boards.

According to an exemplary embodiment of the present disclosure, the first through holes 140 are formed in the first insulating layer 131. According to an exemplary embodiment of the present disclosure, the lower surface of the first through hole 140 is bonded to the connection pad 110, and the upper surface thereof is bonded to the inner layer circuit pattern 150. The first hole 140 is electrically connected to the connection pad 110 and the inner layer circuit pattern 150 each other.

According to an exemplary embodiment of the present disclosure, the outer layer circuit pattern 170 may include a mounting pattern that is electrically connected to the external element when the external component is fixed on the insulating layer 130. For example, the fixed pattern is a portion of the outer layer circuit pattern 170 as shown in FIG. 1 such that at least a portion of the outer layer circuit pattern 170 extends from the outer layer circuit pattern 170 and is exposed outside the protective layer 180.

According to an exemplary embodiment of the present disclosure, the diameter of the upper surface of the first through hole 140 is greater than the diameter of the lower surface.

According to the exemplary embodiment of the present disclosure, the external configuration unit and the inner layer circuit pattern 150 located outside the printed circuit board 100 are electrically connected by the connection pad 110, the first through hole 140, and the metal layer 520. Here, the external configuration unit can be exemplified by an electronic component, a printed circuit board, a motherboard substrate, a package, and the like.

In addition, when the printed circuit board 100 according to the exemplary embodiment of the present disclosure is stacked on a lower printed circuit board (not shown), one of the electronic components fixed to the lower package is housed in the cavity 121. Therefore, the spacing between the printed circuit board 100 and the lower printed circuit board reduces the height of the electronic components housed in the cavity 121. Thereby, the total amount of solder for connecting to the lower printed circuit board (see the second external connection end 340 shown in FIG. 17) can be reduced by the same amount as the reduced interval. Therefore, since the incidence of bridging between such solders is also reduced, the component yield can be increased and the fine pitch of the connection pads 110 can be achieved.

The second through hole 160 is formed according to an exemplary embodiment of the present disclosure In the second insulating layer 135. According to an exemplary embodiment of the present disclosure, the lower surface of the second through hole 160 is bonded to the inner layer circuit pattern 150 and the upper surface thereof is bonded to the outer layer circuit pattern 170. The second through hole 160 electrically connects the inner layer circuit pattern 150 and the outer layer circuit pattern 170.

According to an exemplary embodiment of the present disclosure, the protective layer 180 is formed on the second insulating layer 135 and the outer circuit pattern 170. When a solder for a subsequent fixed electronic component (not shown) is coated on the outer layer circuit pattern 170 and the surface treatment layer 190, the protective layer 180 according to the exemplary embodiment of the present disclosure can prevent solder from being applied to the outer layer circuit. Pattern 170 and surface treatment layer 190. In addition, the protective layer 180 can prevent oxidation and erosion of the outer circuit pattern 170.

A protective layer 180 in accordance with an exemplary embodiment of the present disclosure is formed to expose a portion of the outer circuit pattern 170. In this example, the outer layer circuit pattern 170 exposed through the protective layer 180 may be a fixed pattern electrically connected to an external configuration unit such as an electronic component.

In addition, according to an exemplary embodiment of the present disclosure, the protective layer 180 is formed under the first insulating layer 131 to expose the metal layer 520. In this example, the metal layer 520 exposed through the protective layer 180 may be an area electrically connected to the external configuration unit.

According to an exemplary embodiment of the present disclosure, the protective layer 180 is made of a thermal resistance coating material. For example, the protective layer 180 can be made of a solder resist material.

According to an exemplary embodiment of the present disclosure, the protective layer 180 may change a region formed by the protective layer 180, according to one of ordinary skill in the art. The selection can also be omitted.

According to an exemplary embodiment of the present disclosure, the surface treatment layer 190 is formed on the outer layer circuit pattern 170 exposed via the protective layer 180. Further, the surface treatment layer 190 is formed on the metal layer 520 exposed through the protective layer 180. The surface treatment layer 190 is formed to avoid etching and oxidation of the outer layer circuit pattern 170 and the metal layer 520 via the protective layer 180. For example, as the surface treatment layer 190, any surface treatment layer known in the field of circuit boards can be used, for example, plated with nickel, tin, gold, palladium, or the like, or coated with organic insurance. Organic soldering ability preservative (OPS).

The surface treatment layer according to an exemplary embodiment of the present disclosure may be omitted in accordance with the selection of those having ordinary skill in the art.

In addition, although not shown in FIG. 1, an external connection terminal (not shown) may be formed under the printed circuit board 100. The external connection can be made of solder material.

In addition, although the connection pad 110 has a thickness similar to the depth of the cavity 121, and the first through hole 140 is electrically connected to the connection pad 110 and the inner layer circuit pattern 150 has been illustrated by way of example, in the disclosure In the exemplary embodiments, the disclosure is not limited thereto. For example, if the connection pad 110 according to the exemplary embodiment of the present disclosure has a thickness penetrating through the first insulating layer 131, the connection pad 110 is directly bonded to the inner layer circuit pattern 150, but the first through hole 140 may be omitted.

The printed circuit board 100 according to an exemplary embodiment of the present disclosure includes a cavity 121 and a connection pad 110, and the cavity 121 has an electronic component setting of the lower printed circuit board. Therein, the connection pad 110 narrows the interval between the printed circuit board 100 and the lower package. Therefore, when the package is formed, the overall thickness of the package can be reduced by the printed circuit board 100 according to the exemplary embodiment of the present disclosure. A stacked package to which the printed circuit board 100 according to the exemplary embodiment of the present disclosure is applied will be described below with reference to FIG.

Conventionally, a cavity is formed in the upper surface of the board, and the electronic components and the board accommodated in the cavity are directly electrically connected to each other. Therefore, the protective layer and the solder system need to be formed in the cavity. However, it is difficult to have a step structure on the upper surface of the plate due to the cavity, a protective layer on the upper surface of the plate and the solder in the cavity, and the like, and the like.

The printed circuit board 100 according to an exemplary embodiment of the present disclosure is not directly and electrically connected to electronic components housed in the cavity 121. Here, the name "directly and electrically connected" means that the electronic component in the cavity 121 is electrically connected to the circuit pattern of the printed circuit board 100 by solder (for example, an external connection terminal). Therefore, the printed circuit board 100 does not have the protective layer 180 and the solder is formed in the cavity 121.

2 through 16 are schematic views showing a method for manufacturing a printed circuit board according to an exemplary embodiment of the present disclosure.

Referring to Fig. 2, a carrier substrate 500 is provided.

When the insulating layer and the circuit layer for the printed circuit board are formed, the carrier substrate 500 according to the exemplary embodiment of the present disclosure supports the insulating layer and the circuit layer.

According to an exemplary embodiment of the present disclosure, the carrier substrate 500 has a structure in which the metal layer 520 is stacked on the carrier core 510.

For example, the carrier core 510 is made of an insulating material. However, the material of the carrier core 510 is not limited to an insulating material. For example, the carrier core 510 may be made of a metal material or may have one or more insulating layers and structures in which the metal layers are stacked.

For example, the metal layer 520 is made of copper. However, the material of the metal layer 520 is not limited to copper, and any material may be used without limitation as long as it is a conductive material used in the field of circuit boards.

Although in the exemplary embodiment of the present disclosure, the carrier substrate 500 has been illustrated and illustrated as a structure in which the metal layers 520 are stacked on both sides of the carrier core 510, the structure of the carrier substrate 500 is not limited thereto. That is, in the exemplary embodiment of the present disclosure, the carrier substrate 500 is schematically illustrated for purposes of illustration and understanding. For example, the carrier substrate 500 may have a structure in which a plurality of metal layers are stacked on a carrier core and a release layer is formed between the plurality of metal layers. Therefore, when the release layer is separated, the carrier substrate can be separated and removed from the printed circuit board except for the metal layer formed on the outermost layer. As such, the structure of the carrier substrate 500 is not limited to the structures illustrated and described in the exemplary embodiments of the present disclosure. That is, a carrier substrate having any structure used in the field can also be applied to the present exemplary embodiment.

Referring to FIG. 3, the plating resist 530 is formed on the carrier substrate 500.

According to an exemplary embodiment of the present disclosure, the plating resist 530 is formed on the metal layer 520 of the carrier substrate 500. In addition, the anti-plating agent 530 according to the exemplary embodiment of the present disclosure has an opening portion 531 exposing a metal layer 520 of a region, and a connection pad (not shown) and a cavity pattern (not shown) are formed in the region. in. Here, the area where the cavity pattern is formed has a size to fix the electronic component.

Referring to FIG. 4, the connection pad 110 and the cavity pattern 120 are formed on the carrier substrate 500.

According to an exemplary embodiment of the present disclosure, the connection pad 110 and the cavity pattern 120 are formed on the metal layer 520.

According to an exemplary embodiment of the present disclosure, the connection pad 110 and the cavity pattern 120 are formed by plating on the opening portion 531 of the plating resist 530. In this case, the metal layer 520 exposed through the opening portion 531 of the plating resist 530 can be regarded as a seed layer for electroplating.

The connection pad 110 according to an exemplary embodiment of the present disclosure is a circuit pattern electrically connected to an external configuration unit.

In addition, the cavity pattern 120 is formed to ensure that in a space, when the package package is formed, the electronic components fixed on the lower printed circuit board are positioned in this space. Thus, the cavity pattern 120 has a dimension to later position the electronic components in a cavity (not shown).

According to the exemplary embodiment of the present disclosure, since the connection pads 110 are formed in the same process as the cavity pattern 120, the connection pads 110 and the cavity patterns 120 have the same thickness. Here, the name "the same" means the name "substantially Substantially same. That is to say, the name "identical" means to consider the name "identical" in which an error or offset occurs during the process. However, the connection pads 110 do not have to be the same thickness as the cavity pattern 120. The connection pads 110 may be thicker or thinner than the cavity pattern 120, depending on the choice of one of ordinary skill in the art.

Referring to Figure 5, the plating resist (530, in Figure 4) is removed.

Referring to FIG. 6, the first insulating layer 131 is formed.

According to an exemplary embodiment of the present disclosure, the first insulating layer 131 is formed on the metal layer 520 to cover the connection pad 110 and the cavity pattern 120. According to an exemplary embodiment of the present disclosure, the upper surface of the first insulating layer 131 is higher than the upper surface of the connection pad 110 and the upper surface of the cavity pattern 120. That is, the first insulating layer 131 has a thickness greater than that of the cavity pattern 120.

According to an exemplary embodiment of the present disclosure, the first insulating layer 131 may be formed such that the first insulating layer 131 is stacked on the metal layer 520, the connection pad 110, and the cavity pattern 120 in a film form and then pressurized. The first insulating layer 131 according to an exemplary embodiment of the present disclosure may be formed by any method of forming an insulating layer in the field of a circuit board and the above method.

The first insulating layer 131 according to the exemplary embodiment of the present disclosure may be made of a composite polymer resin, and the composite polymer resin is generally used as an interlayer insulating material. For example, the first insulating layer 131 may be an Ajinomoto Build up Film (ABF), and an epoxy resin such as FR-4 or Bismaleimide Triazine. Made of BT), or similar materials. However, in the exemplary embodiment of the present disclosure, the first insulating layer 131 is formed. The material is not limited to this. The material forming the first insulating layer 131 according to an exemplary embodiment of the present disclosure may be selected from insulating materials known in the field of circuit boards.

Referring to FIG. 7, the inner layer circuit pattern 150 and the first through hole 140 are formed.

According to an exemplary embodiment of the present disclosure, the inner layer circuit pattern 150 is formed on the first insulating layer 131, and the first through holes 140 are formed in the first insulating layer 131.

The first through holes 140 according to the exemplary embodiment of the present disclosure are formed on the connection pads 110 in the first insulating layer 131. That is, the first through hole 140 is formed through the first insulating layer 131 on the connection pad 110 and is formed such that the upper surface of the first through hole 140 is bonded to the inner layer circuit pattern 150 and below the first through hole 140. The surface is bonded to the connection pad 110. The inner layer circuit pattern 150 and the connection pad 10 are electrically connected by the first through holes 140 formed as described above. Further, the first through hole 140 is formed such that the diameter of the upper surface thereof is larger than the diameter of the lower surface thereof.

The inner layer circuit pattern 150 and the first through hole 140 according to the exemplary embodiment of the present disclosure may be formed by cutting through holes (not shown), forming a patterned plating resist (not shown), and then performing electroplating. . Alternatively, the inner layer circuit pattern 150 and the first via hole 140 according to the exemplary embodiment of the present disclosure may perform an etching process by cutting a via hole, performing plating, and then forming an etch resist. The above method for forming the inner layer circuit pattern 150 and the first via hole 140 is an exemplary method, and the inner layer circuit pattern 150 and the first via hole 140 may be any method known in the field of circuit boards. To form.

Moreover, the inner layer circuit pattern 150 and the first via hole 140 according to an exemplary embodiment of the present disclosure may be made of a conductive material used in the field of any circuit board. For example, the inner layer circuit pattern 150 and the first through hole 140 are made of copper.

Although the exemplary embodiments of the present disclosure illustrate an example in which the inner layer circuit pattern 150 is formed in a single layer, the present disclosure is not limited to the above structure. That is, the inner layer circuit pattern 150 according to an exemplary embodiment of the present disclosure may be formed in a plurality of layers according to the selection of those having ordinary knowledge in the art. In this example, the first insulating layer 131 may also be formed in a plurality of layers, and through holes may be further formed to connect the inner layer circuit patterns 150 in the respective layers to each other.

Referring to FIG. 8, the second insulating layer 135 is formed.

According to an exemplary embodiment of the present disclosure, the second insulating layer 135 is formed on the first insulating layer 131 to cover the inner layer circuit pattern 150.

According to an exemplary embodiment of the present disclosure, the second insulating layer 135 may be formed by a method in which the second insulating layer 135 is stacked on the first insulating layer 131 and the inner layer circuit pattern 150 in a film form. And then pressurizing. The second insulating layer 135 according to an exemplary embodiment of the present disclosure can be formed by a method of forming an insulating layer known in the field of a circuit board, and the above method.

According to an exemplary embodiment of the present disclosure, the second insulating layer 135 may be made of an insulating material, and among all the interlayer insulating materials generally used, the insulating material does not include glass fibers. However, the material of the second insulating layer 135 is not limited thereto. That is, the second insulating layer 135 according to an exemplary embodiment of the present disclosure may be Any of all of the interlayer insulating materials used in the field of the circuit board, and may be made of the same material as the first insulating layer 131.

Referring to FIG. 9, the outer circuit pattern 170 and the second through hole 160 are formed.

According to an exemplary embodiment of the present disclosure, the outer circuit pattern 170 is formed on the second insulating layer 135, and the second through hole 160 is formed in the second insulating layer 135.

The outer layer circuit pattern 170 is a circuit pattern on the outermost layer of the printed circuit board 100 in accordance with an exemplary embodiment of the present disclosure. Therefore, some patterns of the outer circuit pattern may be electrically connected to an external configuration unit such as an electronic component, a package, a substrate, or the like. Here, some patterns may be fixed patterns and electrically connected to electronic components fixed on the second insulating layer 135.

The second through hole 160 according to the exemplary embodiment of the present disclosure penetrates through the second insulating layer 135 and is formed such that an upper portion thereof is bonded to the outer layer circuit pattern 170 and a lower portion thereof is bonded to the inner layer circuit pattern 150. The inner layer circuit pattern 150 and the outer layer circuit pattern 170 are electrically connected by a second through hole 160 formed as described above.

The method and material for forming the outer layer circuit pattern 170 and the second through hole 160 according to the exemplary embodiment of the present disclosure refer to the method and material for forming the inner layer circuit pattern 150 and the first through hole 140 of FIG.

Referring to FIG. 10, a protective layer 180 is formed.

According to an exemplary embodiment of the present disclosure, the protective layer 180 is formed on The second insulating layer 135 and the outer layer circuit pattern 170. When the solder for the electronic component (not shown) to be fixed later is applied on the outer layer circuit pattern 170 and the surface treatment layer 190, the protective layer 180 according to the exemplary embodiment of the present disclosure can prevent the solder from being applied to the outer layer. Circuit pattern 170 and surface treatment layer 190. In addition, the protective layer 180 can prevent oxidation and erosion of the outer circuit layer.

A protective layer 180 in accordance with an exemplary embodiment of the present disclosure is formed to expose a portion of the outer circuit pattern 170. In this case, the outer layer circuit pattern 170 exposed by the protective layer 180 may be a fixed pattern electrically connected to an external configuration unit such as an electronic component.

According to an exemplary embodiment of the present disclosure, the protective layer 180 is made of a thermal resistance coating material. For example, the protective layer 180 can be made of a solder resist material.

Referring to Figure 11, the carrier substrate 500 is removed.

According to an exemplary embodiment of the present disclosure, after the carrier core 510 and the metal layer 520 are separated from each other, the carrier core 510 is removed. When the carrier core 510 is removed, the printed circuit boards 100 formed on both sides of the carrier substrate 500 are separated.

Referring to Figure 12, an etch resist 540 is formed.

When the cavity pattern 120 is etched later, the etch resist 540 in accordance with the exemplary embodiment of the present disclosure is formed to avoid damage to the connection pads 110. Therefore, an etch resist 540 is formed under the connection pads 110 to protect the connection pads 110 from etching processes. In this example, the etch resist 540 also protects a portion of the metal layer 520, which portion of the metal layer 520 is located in a region formed by the connection pads 110.

The etch resist 540 according to the exemplary embodiment of the present disclosure is provided with an opening portion 541 to expose a region which is apart from the region where the connection pad 110 is formed.

In addition, if the etching process to be performed later uses an etchant, the etch resist 540 according to the exemplary embodiment of the present disclosure needs to be made of a material that does not react with the corresponding etchant.

Referring to Fig. 13, the cavity 121 is formed.

According to an exemplary embodiment of the present disclosure, an etching process is performed. The metal layer 520 and the cavity pattern 120 exposed by the opening portion 541 of the etch resist 540 are removed by an etching process.

According to an exemplary embodiment of the present disclosure, the etching process may be performed by an etchant that reacts with the cavity pattern (120, in FIG. 12) and the metal layer 520. In this example, the etch resist 540 must not react with the etchant used.

According to an exemplary embodiment of the present disclosure, the cavity pattern (120, in FIG. 12) is removed by an etching process to form the cavity 121. When the package package is formed, at least a portion (not shown) of the electronic components of the lower package are housed in the cavity 121 in accordance with an exemplary embodiment of the present disclosure. According to an exemplary embodiment of the present disclosure, since the cavity 121 is formed by removing the cavity pattern (120, formed in FIG. 12) formed on the first insulating layer 131, the entire inner surface of the cavity 121 is entirely insulated. Made of materials. That is, it can be understood that the inner surface of the cavity 121 is made of the first insulating material 131.

According to an exemplary embodiment of the present disclosure, when the etching process is performed, The metal layer 520 between the connection pad 110 and the etch resist 540 is not etched and is protected by the etch resist 540.

In the method for forming the cavity 121, there is a method in which the insulating film is stacked and the cavity portion is subsequently removed by laser, but according to this method, the process cost is expensive and based on the laser process, and the laser transmission is prevented. The ability of the laser sputter layer is required separately. In another method, a portion of the insulating film forming the cavity is pre-cut and then stacked, but according to this method, the pre-cut side surface is cooled by the high temperature of the process for forming the insulating layer (flows down) ) will cause the surface of the cavity wall to be uneven. However, in accordance with the present disclosure, since the cavity 121 is formed by the etched cavity pattern 120 as described above, the process cost is inexpensive and a cavity 121 having a uniform wall surface can be formed.

The depth of the cavity 121 formed as described above is smaller than the thickness of the first insulating layer 131.

Referring to Figure 14, the etch resist (540, shown in Figure 13) is removed.

According to an exemplary embodiment of the present disclosure, the metal layer 520 formed under the connection pad 110 is protected by an etch resist (540, in FIG. 13) to avoid an etching process. Therefore, when the etch resist (540, in Fig. 13) is removed, the protected metal layer 520 protrudes from the lower surface of the first insulating layer 131 as shown.

Referring to Fig. 15, a surface treatment layer 190 can be formed.

According to an exemplary embodiment of the present disclosure, the protective layer 180 is formed on Below the first insulating layer 131. The protective layer 180 formed under the first insulating layer 131 is formed to expose the metal layer 520. In this case, the exposed metal layer 520 is then attached to a portion of an external connection end (not shown).

The protective layer 180 formed under the first insulating layer 131 according to the exemplary embodiment of the present disclosure need not be formed in the current step. The protective layer 180 may be formed in any step after the metal layer 520 is patterned. In addition, the protective layer 180 formed under the first insulating layer 131 according to an exemplary embodiment of the present disclosure may be omitted according to the selection of those having ordinary knowledge in the art.

According to an exemplary embodiment of the present disclosure, the surface treatment layer 190 is formed on the outer layer circuit pattern 170 exposed by the protective layer 180. For example, the surface treatment layer 190 is formed on a fixed pattern of the outer layer circuit pattern 170. Moreover, in accordance with an exemplary embodiment of the present disclosure, the surface treatment layer 190 is formed on the metal layer 520 exposed by the protective layer 180.

The surface treatment layer 190 according to the exemplary embodiment of the present disclosure avoids erosion and oxidation of the outer layer circuit pattern 170 and the metal layer 520 exposed by the protective layer 180. For example, surface treatment layer 190 can be formed by surface treatment methods known in the art of circuit boards, such as nickel, tin, gold, palladium, or the like, or coated with an organic soldering agent. Preservative, OPS).

The step of forming the surface treatment layer 190 in accordance with an exemplary embodiment of the present disclosure may be omitted according to the choice of one of ordinary skill in the art, or may be changed after the outer circuit pattern 170 is formed. In addition, the surface treatment layer according to an exemplary embodiment of the present disclosure is selected according to the selection of those skilled in the art. 190 may also be selectively formed only on the desired pattern of outer layer circuit pattern 170 and metal layer 520.

Referring to Figure 16, the external connection end 195 is formed.

According to an exemplary embodiment of the present disclosure, the external connection end 195 is formed on the lower surface of the surface treatment layer that is positioned below the metal layer 520 and exposed to the outside of the protective layer 180. Alternatively, in the example in which the surface treatment layer 190 and the protective layer 180 are omitted, the external connection end 195 is formed on the lower surface of the connection pad 110 exposed by the first insulating layer 131. The external connection end 195 according to an exemplary embodiment of the present disclosure electrically connects the external configuration unit to the printed circuit board 100, such as a substrate, a package, a motherboard, or the like. For example, the external connection end 195 can be made of a ball type solder material. However, the form of the external connection end 195 is not limited to the ball type.

The printed circuit board 100 fabricated in accordance with an exemplary embodiment of the present disclosure has a cavity 121 formed therein. In addition, when the package package is formed, the cavity 121 receives a portion (not shown) of the electronic component fixed to the lower package (not shown). Therefore, the spacing between the printed circuit board 100 and the lower printed circuit board further reduces the thickness of the electronic components housed in the cavity 121. Therefore, the printed circuit board 100 and the lower package according to the exemplary embodiment of the present disclosure can be connected to each other by the external connection end 195 having a small size. In addition, since the size of the external connection end 195 is reduced, the external connection end 195 can be disposed at a fine interval, and thus the bridging between the external connection ends 195 can be avoided or reduced.

Manufacturing a printed circuit board according to an exemplary embodiment of the present disclosure The method of 100 is not limited to the schematic diagrams shown in Figures 2 to 16. The methods of FIGS. 2 to 16 are merely examples, and the carrier substrate, the method of forming the circuit pattern, the etching method, and the like may be changed to any structure known in the field of the circuit board according to those having ordinary knowledge in the art. And method.

FIG. 17 is a schematic diagram of a stacked package according to an exemplary embodiment of the present disclosure.

Referring to FIG. 17, a stacked package 300 according to an exemplary embodiment of the present disclosure has a structure in which an upper package 330 is stacked on a lower package 310.

According to an exemplary embodiment of the present disclosure, the lower package 310 includes a lower package substrate 210 and a first electronic component 220.

The package substrate 210 includes an insulating layer 211 and a circuit pattern 212 formed in the insulating layer 211 according to an exemplary embodiment of the present disclosure. The first electronic component 220 is disposed on the lower package substrate 210.

The first electronic component 220 in accordance with an exemplary embodiment of the present disclosure may be any kind of electronic component that can be applied to the field of packaging.

Moreover, according to an exemplary embodiment of the present disclosure, the first external connection end 320 may be formed under the lower package 310. The first external connection end 320 according to an exemplary embodiment of the present disclosure may be made of a spherical solder material.

According to an exemplary embodiment of the present disclosure, the upper package 330 includes an upper package substrate 230, a second electronic component 240, and a first molding member 250.

The package substrate 230 is the printed circuit board 100 of FIG. 1 according to an exemplary embodiment of the present disclosure.

According to the exemplary embodiment of the present disclosure, the upper package substrate 230 is connected to one surface (upper surface) of the lower package substrate 210, and the first electronic component 220 is fixed on the surface of the lower package substrate 210. The above package substrate 230 includes at least one insulating layer 130. Further, the insulating layer 130 has a cavity 121 that accommodates at least a portion of the first electronic component 220, and the inner surface of the cavity 121 is made of an insulating material.

According to an exemplary embodiment of the present disclosure, the second electronic component 240 is disposed on the upper package substrate 230. In this example, the second electronic component 240 is electrically connected to the outer layer circuit pattern 170 of the upper package substrate 230. Here, the outer layer circuit pattern 170 is electrically connected to the second electronic component 240 in a fixed pattern. Although the exemplary embodiment of the present disclosure illustrates that the second electronic component 240 and the upper package substrate 230 are connected to each other by wires, the disclosure is not limited thereto. That is, the second electronic component 240 and the upper package 330 may be electrically connected to each other by a conductive material. Moreover, in accordance with an exemplary embodiment of the present disclosure, the second electronic component 240 can be a memory device. However, the type of the second electronic component 240 is not limited to a memory device, and may be any kind of electronic component that can be used in the field of packaging.

According to an exemplary embodiment of the present disclosure, the first molding member 250 is formed on the upper package substrate 230 to cover the second electronic component 240. The first molding member 250 according to an exemplary embodiment of the present disclosure is formed to protect the second electronic component 240 from external influences. For example, the first molding member 250 may be made of an epoxy molding compound (EMC) or a silicone gel. However, the material of the first molding member 250 is not limited to EMC and coagulation. Glue, and any of the molding materials known in the field of known packaging can be used.

Moreover, in accordance with an exemplary embodiment of the present disclosure, the second external connection 340 may be formed below the upper package 330. The second external connection end 340 according to the exemplary embodiment of the present disclosure is the external connection end 195 of FIG.

According to an exemplary embodiment of the present disclosure, when the upper package 330 is stacked on the lower package 310, one portion of the first electronic component 220 is housed in the cavity 121 of the upper package substrate 230. In this example, the cavity 121 houses the first electronic component 220 in a state in which the cavity 121 is spaced apart from the first electronic component 220 by a predetermined interval.

According to an exemplary embodiment of the present disclosure, the second molding member 260 may be formed between the inner surface of the cavity 121 and the first electronic component 220. That is, the second molding member 260 fills the space between the cavity 121 and the first electronic component 220. For example, the second molding member 260 may be made of an epoxy molding compound (EMC). However, the material of the second molding member 260 is not limited to EMC, and any molding material known in the field of known packaging can be used. As shown in FIG. 17, a second molding member 260 is formed between the upper package 330 and the lower package 310, and is also formed between the cavity 121 and the first electronic component 220. However, regardless of whether the second molding member 260 is formed in other regions and the position at which the second molding member 260 is formed may be changed, the second molding member 260 is formed between the cavity 121 and the first electronic component 220.

Further, the cavity 121 is such that the interval between the upper package 330 and the lower package 310 reduces the thickness of the electronic components housed in the cavity 121. In addition, the connection The pads 110 are formed on both sides of the cavity 121 to electrically connect the inside of the upper package 330 to the second external connection end 340. Therefore, although the second external connection end 340 is formed by solder having a small size, the second external connection end 340 may be sufficient to connect the upper package 330 and the lower package 310 to each other. As such, since the second external connection end 340 is formed by solder having a small size, the plurality of second external connection ends 340 may be disposed at a fine interval. Furthermore, defects due to bridging between such second external connections 340 can be avoided or reduced. In addition, since the second external connection terminal 340 having a small size is used, the thickness of the stacked package 300 can also be reduced.

Further, according to the prior art, a cavity for fixing electronic components is formed in the lower package substrate. In the case where the cavity according to the prior art is formed in the lower package substrate, the area where the circuit may be formed is reduced as much as the area forming the cavity. Further, the protective layer and the solder (external connection end) are required to be formed in a cavity for electrically connecting to the electronic component, and the protective layer is, for example, a solder resist material. However, since the upper surface of the substrate has a stepped structure due to the cavity, it is difficult to form the protective layer and the solder.

However, the printed circuit board (100, in FIG. 1) according to the exemplary embodiment of the present disclosure is applied to the package 330 above the stacked package 300. That is, the cavity 121 accommodating the electronic component is formed in the lower surface of the upper package substrate 230. In addition, the electronic components housed in the cavity 121 are not directly connected and are not electrically connected to the package substrate 230. Therefore, the protective layer and the solder do not need to be formed in the cavity 121.

Although the embodiments of the present disclosure have been disclosed for the purpose of illustration, the disclosure is not to be construed as limited by the scope of the disclosure , various changes, Add-ons and alternatives are available.

Therefore, any and all modifications, variations and equivalent arrangements are intended to be included within the scope of the disclosure, and the scope of the disclosure is disclosed by the appended claims. In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Printed circuit board

110‧‧‧Connecting mat

121‧‧‧ cavity

130‧‧‧Insulation

131‧‧‧First insulation

135‧‧‧Second insulation

140‧‧‧first through hole

150‧‧‧Inner circuit pattern

160‧‧‧second through hole

170‧‧‧Outer circuit pattern

180‧‧‧protection layer

190‧‧‧ surface treatment layer

520‧‧‧metal layer

Claims (38)

A printed circuit board connected to a surface of a substrate and comprising at least one insulating layer, the substrate having a first electronic component fixed on the surface, wherein the at least one insulating layer has a cavity formed therein, the cavity receiving the At least a portion of the first electronic component, and the cavity has an inner surface, made of an insulating material. The printed circuit board of claim 1, wherein the cavity has a depth that is less than a thickness of one of the at least one insulating layer. The printed circuit board of claim 1, further comprising a fixed pattern formed on the at least one insulating layer and electrically connected to a second electronic component, wherein the second electronic component is fixed to the at least one On the insulation layer. The printed circuit board of claim 1, further comprising a connection pad, at least a portion of which is embedded in the at least one insulating layer. The printed circuit board of claim 4, wherein the connection pad surrounds a side edge of the cavity. The printed circuit board of claim 4, wherein the connection pad has a thickness equal to a depth of the cavity. The printed circuit board of claim 4, further comprising a uniform hole formed in the at least one insulating layer and formed on an upper surface of the connection pad. The printed circuit board of claim 7, wherein the through hole has an upper surface having a diameter larger than a diameter of a lower surface of the through hole. The printed circuit board of claim 1, wherein the entire inner surface of the cavity is made of the insulating material that is the same as the at least one insulating layer. The printed circuit board of claim 4, further comprising a metal layer formed on a lower surface of the connection pad. The printed circuit board of claim 7, further comprising an inner layer circuit pattern formed on the at least one insulating layer and bonded to an upper surface of the through hole. The printed circuit board of claim 1, wherein the cavity houses the first electronic component and the cavity is spaced apart from the first electronic component by a predetermined interval. A method for manufacturing a printed circuit board, the method comprising: forming a cavity pattern on a carrier substrate; forming an insulating layer on the carrier substrate to embed the cavity pattern; removing the carrier substrate And removing the cavity pattern to form a cavity in the insulating layer. The method of claim 13, wherein in the step of forming the cavity pattern, when the cavity pattern is formed, a connection pad is further formed on the carrier substrate. The method of claim 14, wherein in the step of forming the insulating layer, the insulating layer is formed to embed the cavity pattern and the connection pad. The method of claim 14, wherein the carrier substrate package A metal layer is disposed on a carrier core or on the carrier core and under. The method of claim 16, wherein the step of removing the carrier substrate comprises: removing the carrier core by separating the carrier core and the metal layer from each other; forming an etch resist on the metal A layer below the layer corresponds to a location of the pad; and the metal layer exposed to the etchant is removed. The method of claim 13, wherein in the step of forming the cavity pattern, the cavity pattern is formed in a plating scheme. The method of claim 15, further comprising: after the step of forming the insulating layer, forming a uniform hole in an upper surface of the connection pad and penetrating the insulating layer. The method of claim 19, further comprising: forming an inner layer circuit pattern on the insulating layer and bonding to an upper surface of the through hole during or after the step of forming the through hole. A package package comprising: a lower package comprising a lower package substrate and a first electronic component, wherein the first electronic component is disposed on the lower package substrate; and an upper package substrate comprising at least one insulating layer, the at least one insulating layer Having a cavity formed therein, the cavity housing at least a portion of the first electronic component, and the cavity having an inner surface, made of an insulating material; An external connection end is formed between the lower package substrate and the upper package substrate, and electrically connected to the upper package substrate and the lower package substrate. The package of claim 21, wherein the inner surface of the cavity in the upper package substrate is made of the same insulating material as the at least one insulating layer. The package package of claim 21, wherein the upper package substrate further comprises a metal layer formed under the upper package substrate, the metal layer contacting the external connection end. The package package of claim 21, wherein the upper package substrate further comprises an inner layer circuit pattern formed therein. The package package of claim 21, further comprising a second electronic component fixed on the upper package substrate. The package of claim 25, wherein the second electronic component is electrically connected to the upper package substrate by a wire bond. The package package of claim 25, further comprising a first molding member formed on the upper package substrate and covering the second electronic component. The package of claim 21, wherein the cavity extends from a lower surface of the upper package substrate to a middle of the upper package substrate in a concave shape. The package of claim 21, wherein the cavity houses the first electronic component such that the cavity is spaced apart from the first electronic component by a predetermined interval. The package of claim 21, wherein a second molded member is formed between the inner surface of the cavity and the first electronic component. A printed circuit board is connected to a substrate, and a first electronic component is fixed on the substrate. The printed circuit board comprises: a first insulating layer having a cavity, the cavity accommodating at least a part of the first electronic component And an inner layer circuit pattern on the first surface of the first insulating layer, the first surface of the first insulating layer being opposite to a second surface of the first insulating layer on which the cavity is disposed. The printed circuit board of claim 31, further comprising: a connection pad extending from the second surface of the first insulating layer to the inside of the first insulating layer; and a first through hole The first surface of the first insulating layer extends to the connection pad; wherein the first via hole is filled with a conductive material and the inner layer circuit pattern is disposed on the first through hole and the first first insulating layer On the surface. The printed circuit board of claim 32, further comprising: a metal layer disposed on the connection pad; a first surface treatment layer disposed on the metal layer; and a first protective layer disposed on the The first insulating layer is exposed to expose the cavity and the first surface treatment layer. The printed circuit board as described in claim 32, further comprising: a second insulating layer disposed on the first surface of the first insulating layer and burying the inner layer circuit pattern; a second through hole extending from the inner layer circuit pattern to the second insulating layer a surface, the second through hole is filled with a conductive material; an outer circuit pattern is disposed on the surface of the second through hole and the second insulating layer; a surface treatment layer covering a portion of the outer circuit pattern; and a surface a second protective layer disposed on the surface of the outer circuit pattern and the second insulating layer. The printed circuit board of claim 32, wherein the connection pad has a thickness equal to a depth of the cavity. The printed circuit board of claim 32, wherein the diameter of the first through hole increases in a direction toward one of the first surfaces of the first insulating layer. The printed circuit board of claim 31, wherein the entire inner surface of the cavity is made of the same insulating material as the first insulating layer. The printed circuit board of claim 31, wherein the cavity is spaced apart from the first electronic component by a predetermined interval.