TW201603237A - Semiconductor device - Google Patents

Abstract

A semiconductor device includes: a semiconductor layer defined with an active region thereover, wherein the active region includes a first sub-region and a second sub-region; a doped region disposed in a portion of the semiconductor layer, extending across the first and second sub-regions; a high voltage (HV) semiconductor element, disposed over the semiconductor layer in the first sub-region, wherein the HV semiconductor element comprises a portion of the doped region; and an electrostatic discharge (ESD) protection element disposed over the semiconductor layer in the second sub-region, wherein the ESD protection element comprises the other portion of the doped region.

Description

Semiconductor device

This invention relates to integrated circuit devices, and more particularly to a semiconductor device suitable for high voltage operation applications, including integrated high voltage semiconductor components and electrostatic discharge protection components.

In recent years, with the increasing demand for applications such as flat panel displays, illumination and ballast applications, power supplies, and various other products, research into the technology of high voltage semiconductor devices used therein has gradually increased. .

With the continuous advancement of semiconductor process micro-shrinking technology, it is increasingly important to improve the reliability of high-voltage semiconductor devices. However, in the process of manufacturing, processing, assembling, transporting, and using high-voltage semiconductor devices, the entire process is subject to the threat of electrostatic discharge (ESD). Without proper protection measures, high-voltage semiconductor devices will Damaged and unable to sell.

Therefore, there is a need for a high voltage semiconductor device with ESD protection components to improve its ESD protection in flat panel displays, illumination and ballast applications, power supplies, and a variety of other related applications, and to enhance the use of The reliability of high voltage semiconductor devices and the useful life of related products to which such high voltage semiconductor devices are applied.

According to an embodiment, the present invention provides a semiconductor device comprising: a semiconductor layer having an active region defined thereon, wherein the active region includes a first sub-region and a second sub-region; a first doped region, And disposed in a portion of the semiconductor layer and spanning the first sub-region and the second sub-region; a high voltage semiconductor component disposed on the semiconductor layer of the first sub-region of the active region, wherein the high voltage semiconductor The component includes one of the first doped regions in the semiconductor layer of the first sub-region of the active region; and an electrostatic discharge protection component disposed on the semiconductor layer of the second sub-region of the active region The electrostatic discharge protection element includes another portion of the first doped region in the semiconductor layer of the second sub-region of the active region.

The above described objects, features and advantages of the present invention will become more apparent and understood.

100‧‧‧Semiconductor device

102‧‧‧Semiconductor substrate

104‧‧‧Semiconductor layer

106‧‧‧Isolation components

108‧‧‧ Well Area

110‧‧‧ Well Area

112‧‧‧ Main area

114‧‧‧ gate structure

116‧‧‧Doped area

118‧‧‧Doped area

120‧‧‧Doped area

121‧‧‧Electrical components

122‧‧‧Electrical components

124‧‧‧Electrical components

126‧‧‧Electrical components

128‧‧‧Electrical components

200‧‧‧High voltage semiconductor components

300‧‧‧Electrostatic discharge protection components

400‧‧‧External wires

500‧‧‧Semiconductor device

502‧‧‧Semiconductor substrate

504‧‧‧Semiconductor layer

506‧‧‧Isolation components

508‧‧‧ Well Area

510‧‧‧ Well Area

512‧‧‧ main body area

514‧‧‧ gate structure

516‧‧‧Doped area

518‧‧‧Doped area

520‧‧‧Doped area

521‧‧‧Electrical components

522‧‧‧Electrical components

524‧‧‧Electrical components

526‧‧‧Electrical components

528‧‧‧Electrical components

550‧‧‧Doped area

560‧‧‧Doped area

570‧‧‧Doped area

580‧‧‧Doped area

600‧‧‧High voltage semiconductor components

700‧‧‧Electrostatic discharge protection components

A, B, C‧‧‧ active area

C1, C2‧‧‧ sub-area

1 is a top plan view showing a semiconductor device in accordance with an embodiment of the present invention.

Figure 2 is a schematic cross-sectional view showing a portion of the semiconductor device along line 2-2 of Figure 1; and Figure 3 is a cross-sectional view showing one of the semiconductor devices along line 3-3 of Figure 1 4 is a top view showing a semiconductor device in accordance with another embodiment of the present invention.

Figure 5 is a cross-sectional view showing a portion of the semiconductor device along line 5-5 of Figure 4; and Figure 6 is another cross-sectional view showing the semiconductor device along line 5-5 of Figure 4 And a seventh cross-sectional view showing a semiconductor device in accordance with still another embodiment of the present invention.

The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention.

Referring to the schematic diagrams of Figures 1-3, a semiconductor device 100 suitable for use in high voltage applications having operating voltages greater than, for example, 500 volts in accordance with an embodiment of the present invention is shown. 1 is a top plan view of a semiconductor device 100, and FIGS. 2-3 are cross-sectional views showing line segments 2-2 and 3-3 of the semiconductor device 100 in FIG. 1, respectively. Here, the semiconductor device 100 is used as a comparative example to illustrate the problem of size reduction of the semiconductor device including the electrostatic discharge protection element encountered by the inventor of the present invention, and is not intended to limit the present invention.

Referring to FIG. 1 , the semiconductor device 100 includes a high voltage semiconductor device 200 disposed in one active region A of a semiconductor substrate 102 . And an electrostatic discharge protection element 300 disposed in another active region B on the semiconductor substrate 102. The active regions A and B are separated by an isolation element (not shown) such as a thick oxide to electrically insulate the components in the high voltage semiconductor device 200 from the electrostatic discharge protection device. Components within 300.

In FIG. 1, the high voltage semiconductor device 200 is exemplified by a lateral double diffused MOS transistor, and the electrostatic discharge protection device 300 is a gate grounded MOS transistor. Transistor, GGMOS transistor) as an example. For the purpose of simplifying the illustration, only the gate structure (shown as the gate structure 114) and the source region in the high voltage semiconductor device 200 and the electrostatic discharge protection device 300 are partially illustrated in FIG. The source region is shown as a doped region 118), a drain region (shown as a doped region 120), a body region (shown as a doped region 116), and a conductive member (displayed as a plurality of conductive regions) The components 121, 122, 124, 126) are part of the components, and the remaining components of the high voltage semiconductor component 200 and the electrostatic discharge protection component 300 are referred to the display of the cross-sectional views in FIGS. 2-3.

Referring to FIG. 2, a cross-sectional view of one of the high voltage semiconductor devices 200 along the inner line 2-2 of FIG. 1 is shown. Here, when the high voltage semiconductor device 200 is a lateral double diffused MOS transistor, it may include a semiconductor substrate 102, a semiconductor layer 104 formed on the semiconductor substrate 102, and a semiconductor layer formed separately. a plurality of isolation elements 106 on the surface of the layer 104, a well region 108 formed in one portion of the semiconductor substrate 102, a well region 110 formed in one portion of the semiconductor layer 104, and formed in the other portion of the semiconductor layer 104 and respectively Located on one of the two symmetrical sides of the well region 110, the body region 112 is formed a gate structure 114 over one of the semiconductor layer 104 and the body region 112 and extending over one of the isolation elements 116, a pair of doped regions 116 and 118 formed in each body region 112, and formed on One of the doped regions 120 within the well region 110.

As shown in FIG. 2, well region 110 is generally located above well region 108, and such isolation elements 106 generally expose portions of portions of semiconductor layer 104, while doped regions 116, 118, 120 are generally located The spacer elements 106 are generally exposed within portions of the semiconductor layer 104 and are located, for example, within one of the body region 112 and the well region 110.

In one embodiment, the semiconductor layer 104 can be an epitaxial semiconductor layer, and the semiconductor substrate 102 and the semiconductor layer 104 can comprise a semiconductor material such as germanium. The semiconductor substrate 102, the semiconductor layer 104, the body region 112 and the doped region 116 have a first conductivity type, for example, a P-type conductivity type, and the well regions 108, 110 and the doping regions 116, 118 have opposite to the first conductivity. The second type of type is, for example, an N-type conductivity type. In one embodiment, the well region 110 is used as a drift region, the doped region 116 serves as a body contact region, and the doped regions 118 and 120 serve as a source. The source region is used with a drain region. The doped regions 116, 118, and 120 have a doping concentration that is higher than one of the adjacent body regions 112 or well regions 110. In one embodiment, the gate structure 114 may include a gate dielectric layer and a gate electrode layer (not shown) stacked on the semiconductor layer 104 in sequence.

In addition, as shown in FIG. 1-2, a plurality of spaced conductive members 121, 122, 124, and 126 are further formed on the semiconductor substrate 102 in the active region A to be physically coupled to the doped region 116 and the doped region, respectively. 118, the gate structure 114 and the doped region 120, the conductive members 121, 122, 124, 126 and the semiconductor layer 104. An intervening dielectric layer (not shown) may be further formed between the doped region 116, the doped region 118, the gate structure 114, and the doped region 120 to separate the conductive members 121, 122, 124, and 126.

Referring to Figure 3, a cross-sectional view of the ESD protection device 300 along line 3-3 of Figure 1 is shown. Here, when the electrostatic discharge protection device 300 is a gate grounded MOS transistor (GGMOS transistor), the cross-sectional structure thereof can be substantially similar to that of the lateral double-diffused MOS transistor as shown in FIG. The structure of a LDMOS transistor. As such, it may also include a semiconductor substrate 102, a semiconductor layer 104 formed on the semiconductor substrate 102, a plurality of isolation elements 106 formed on the surface of the semiconductor layer 104, and a well formed in one of the semiconductor substrates 102. a region 108 formed in one of the semiconductor layers 104, a well region 110 formed in the other portion of the semiconductor layer 104 and located on the two symmetric sides of the well region 110, respectively, on the body region 112, formed on the semiconductor layer 104 and the body a gate structure 114 on one of the regions 112 and extending over one of the isolation elements 116, a pair of doped regions 116 and 118 formed in each body region 112, and one of the well regions 110 Doped region 120. The arrangement of the above components is the same as the arrangement of the same members in the high voltage semiconductor device 200 as shown in Figs. 1-2.

Further, as shown in FIGS. 1 and 3, two conductive members 126 and 128 are formed on the semiconductor substrate 102. Unlike the implementation of the plurality of conductive members 121, 122, and 124 shown in FIGS. 1 and 2, the conductive members 128 shown in FIGS. 1 and 3 are simultaneously bonded to the doping region 116 and the doping region 118. And the gate structure 114, and the conductive member 126 is still connected to the doping region 120, thereby forming a lateral double diffused gold oxide different from the high voltage semiconductor device 200 shown in FIG. One of the semiconductor transistors is gated to a MOS transistor.

As shown in FIG. 1-3, when the semiconductor device 100 is operated, the conductive member 126 and the electrostatic discharge protection respectively electrically connected to the high voltage semiconductor device 200 can be electrically connected by an external wire 400 such as one of the bonding wires. The conductive member 130 in the component 300 is further connected in parallel with the doping region 120 for the drain in the high voltage semiconductor device 200 and the doping region 120 for the drain in the electrostatic discharge protection device 300, so as to be a semiconductor device. When the 100 is subjected to the electrostatic discharge, the electrostatic discharge protection component 300 can take the electrostatic discharge damage to avoid the damage of the main high voltage semiconductor component 200, thereby ensuring the reliability and the service life of the semiconductor device 100.

However, in view of the fact that the high voltage semiconductor device 200 included in the semiconductor device 100 shown in FIGS. 1-3 and the components in the electrostatic discharge protection device 300 are disposed in a form corresponding to the symmetric arrangement of the doping regions 120, It is necessary to occupy a larger area of one of the semiconductor substrates 102 for use of its active areas A and B. With the continuous advancement of semiconductor process micro-reduction technology, it is necessary to improve the semiconductor device 100 shown in Figures 1-3 to provide an electrostatic discharge protection suitable for high voltage applications with a smaller size and a smaller size. A semiconductor device for components.

In view of this, please refer to the schematic diagrams of Figures 4-5, showing a semiconductor device 500 suitable for high voltage applications having operating voltages higher than, for example, 500 volts in accordance with another embodiment of the present invention. Compared with the semiconductor device 100 shown in FIGS. 1-3, the semiconductor device 500 shown in FIGS. 4-5 can have a smaller and reduced size, and an electrostatic discharge protection element is integrated therein to ensure The reliability and service life of the semiconductor device 500. FIG. 4 shows a semiconductor device 500 One of the top views, and the fifth figure shows a cross-sectional view of one of the line segments 5-5 of the semiconductor device 500 in FIG.

Referring to FIG. 4, the semiconductor device 500 includes a high voltage semiconductor device 600 and an electrostatic discharge protection device 700 in a single active region C integrated on a semiconductor substrate 502. The active region C is surrounded by an isolation element (not shown) such as a thick oxide to electrically insulate the components of the high voltage semiconductor component 600 and the electrostatic discharge protection component 700 and the active region C. Other components than others. Here, the active region C includes two adjacent sub-regions C1 and C2, and the high-voltage semiconductor device 600 is formed on the semiconductor substrate 502 in the sub-region C1, and the electrostatic discharge protection device 700 is formed in the sub-region C2. On the semiconductor substrate 502.

In FIG. 4, the high voltage semiconductor device 600 is exemplified by a lateral double diffused MOS transistor, and the electrostatic discharge protection device 700 is a gate grounded MOS transistor. Transistor, GGMOS transistor) as an example. For the purpose of simplification, the gate structure (shown as gate structure 514) and the source region (source region,) in the high voltage semiconductor device 600 and the electrostatic discharge protection device 700 are only partially illustrated in FIG. Shown as doped region 518), drain region (shown as doped region 520), body region (shown as doped region 516), and conductive components (displayed as conductive member 521, Some parts of the components such as 522, 524, 526, and 528), and the other components of the high-voltage semiconductor device 600 and the electrostatic discharge protection device 700 are referred to the display of the cross-sectional view of FIG. Here, the high voltage semiconductor device 600 of the semiconductor device and the electrostatic discharge protection device 700 share a doping region 520, And a body region in the high voltage semiconductor device 600 (refer to the body region 512 shown in FIG. 5), a source region (shown as a doped region 518), and a body contact region (shown as doped The region 516) is connected to the body region of the electrostatic discharge protection device 700 (see the body region 512 shown in FIG. 5), the source region (shown as the doping region 518), and the body contact. a body contact region (shown as a doped region 516), and a conductive member 528, such that the region and the conductive member span the plurality of sub-regions C1 and C2 and are partially disposed in the semiconductor regions C1 and C2 On one of the substrates 502. In addition, the high voltage semiconductor component 600, such as the gate structure 514, and other components of the conductive members 522 and 524 are separated from the components of the electrostatic discharge protection component 700 such as the gate structure 514 and the conductive member 528. Without physical contact.

Referring to Figure 5, a cross-sectional view of the semiconductor device 500 along line 5-5 of Figure 4 is shown. Here, the semiconductor device 500 integrates the high voltage semiconductor device 600 and the electrostatic discharge protection device 700 into two sub-regions C1 and C2 of a single active region C of a semiconductor substrate 502, and forms them into a single device. As shown in FIG. 5, when the high voltage semiconductor device 600 is a lateral double diffused MOS transistor, the electrostatic discharge protection device 700 is a gate grounded MOS transistor (GGMOS). The semiconductor device 500 includes a semiconductor substrate 502, a semiconductor layer 504 formed on the semiconductor substrate 502, and a plurality of isolation elements 506 formed on the surface of the semiconductor layer 504, and formed in one of the semiconductor substrates 502. A well region 508, one well region 510 formed in one of the semiconductor layers 504, and one of the two symmetric sides of the well region 510, respectively, are formed on the semiconductor layer 504. With body area 512 A gate structure 514 extending over one of the isolation elements 516, a pair of doped regions 516 and 518 formed in each body region 512, and a doped region 520 formed in the well region 510 And forming a doped region 570 below one of the well regions 510 located within the sub-region C1 of the active region C and adjacent to the isolation element 506 of the doped region 520.

As shown in FIG. 5, well region 510 is generally located above well region 508, and such isolation elements 506 generally expose portions of portions of semiconductor layer 504, while doped regions 516, 518, and 520 are generally located The isolation elements 506 are generally exposed within portions of the semiconductor layer 504 and are located within a portion of the body region 512 and the well region 510, respectively.

In one embodiment, the semiconductor layer 504 can be an epitaxial semiconductor layer, and the semiconductor substrate 502 and the semiconductor layer 504 can comprise a semiconductor material such as germanium. The semiconductor substrate 502, the semiconductor layer 504, the body region 512 and the doped region 516 have a first conductivity type, for example, a P-type conductivity type, and the well regions 508, 510 and the doping regions 516, 518, 570 have opposite A second type of conductivity type, such as an N-type conductivity type. In one embodiment, well region 510 is used as a drift region, doped region 516 acts as a body contact region, and doped regions 518 and 520 serve as a source region, respectively. (source region) and a drain region. The doped regions 516, 518, 520, and 570 have a doping concentration that is higher than one of the adjacent body regions 512 or well regions 510. In one embodiment, the gate structure 514 can include a gate dielectric layer and a gate electrode layer (not shown) stacked on the semiconductor layer 504 in sequence.

In addition, as shown in FIGS. 4-5, a plurality of spaced conductive members 521, 522, and 524 are further formed on the semiconductor substrate 502 in the sub-region C1 of the active region C. And 526, respectively, physically connected to the doped region 516, the doped region 518, the gate structure 514, and the doped region 520 in the sub-region C1, the conductive members 522, 524, 526 and the semiconductor in the sub-region C1 An interlayer dielectric layer (not shown) may be formed between layer 504, doped regions 516 and 518, gate structure 514, and doped region 520 to separate such features.

Similarly, as shown in FIGS. 4-5, two conductive members 526 and 528 are formed on the semiconductor substrate 502 in the sub-region C2 of the active region C. Different from the implementation of the plurality of conductive members 521, 522 and 524 shown in the sub-region C1 of the active region C, the conductive members 528 shown in the sub-region C2 of the active region C are simultaneously connected to the doped region 516, doped. The region 518 is connected to the gate structure 514, and the conductive member 526 is still connected to the doping region 520, thereby forming a gated MOS semiconductor different from the lateral double-diffused MOS transistor used in the high voltage semiconductor device 600. Crystal.

As shown in FIG. 4-5, when the semiconductor device 500 is operated, the conductive member 126 and the electrostatic discharge protection member 300 for electrically connecting to the high voltage semiconductor device 200, respectively, as shown in FIG. 1 can be eliminated. The conductive member 130 is used as one of the external wires 400 of the bonding wire, and can be directly connected to the high voltage semiconductor device 600 and the electrostatic discharge protection device 700 through the doping region 520 electrically connected to the semiconductor device 500. In the electrostatic discharge protection component 700, the placement of the doped region 570 in one of the doped regions 520 is provided in the well region 510 (ie, the drift region) disposed in the sub-region C2 to reduce the static electricity. The breakdown voltage of the discharge protection component 700 is at least about the breakdown voltage of the high voltage semiconductor component 600, so that the electrostatic discharge protection component in the sub-region C2 of the active region C can be used when the semiconductor device 500 encounters an electrostatic discharge condition. 700 bears static electricity The damage of the discharge can further avoid the damage of the main high-voltage semiconductor component 600 in the sub-region C1 of the active region C, thereby ensuring the reliability and the service life of the semiconductor device 500.

Furthermore, since the semiconductor device 500 shown in FIGS. 4-5 integrates the high voltage semiconductor device 600 and the electrostatic discharge protection device 700 into a single active region, the semiconductor device as shown in FIGS. 1-3 can be used. 100 occupies a region of a smaller number of semiconductor substrates, and thus, with the continuous advancement of semiconductor process miniaturization technology, a semiconductor device having an electrostatic discharge protection element suitable for high voltage applications, which is more compact and reduced in size, is provided.

The semiconductor device having the electrostatic discharge protection element of the present invention is not limited by the implementation of Figures 4-5. In other embodiments, from the top view, the contour of the active area C is not limited to the circular shape shown in FIG. 4-5, and may be a substantially symmetrical shape such as a polygon or an ellipse. In addition, the high voltage semiconductor device 600 and the electrostatic discharge protection device 700 used in the semiconductor device 500 are not limited to the lateral double diffusion MOS transistor and the ground oxynitride transistor shown in FIG. 4-5. It can be other suitable high voltage semiconductor components and electrostatic discharge protection components. In one embodiment, the high voltage semiconductor device 600 is, for example, an element such as an insulated gate bipolar transistor (IGBT), and the electrostatic discharge protection device 700 is, for example, a diode or a controlled rectifier. , SCR) components.

Referring to FIG. 6, a cross-sectional view of a semiconductor device 500 along line 5-5 of FIG. 4 is shown in accordance with another embodiment. Here, the semiconductor device 500 as shown in FIG. 6 is obtained by modifying the high voltage semiconductor device 600 in the semiconductor device 500 in FIG. 5, and only the difference between the two will be described here. As shown in FIG. 6, a doping region 550 and a doping region 560 may be disposed from top to bottom in the well region 510 of the high voltage semiconductor device 600 adjacent to the surface of the isolation device 506, and the doping region 550 has The second conductivity type is the same as that of the well region 510, and the doped region 560 has the same conductivity type as the semiconductor substrate 502 and the semiconductor layer 504. In the present embodiment, by the arrangement of the doping regions 550 and 560, the breakdown voltage performance of the high voltage semiconductor device 600 can be further improved and the on-state resistance value (Ron) of the semiconductor device 500 can be lowered, and the setting situation contributes to The component size and the occupied area of the semiconductor device 500 are reduced.

Referring to FIG. 7, a cross-sectional view of a semiconductor device 500 along line 5-5 of FIG. 4 is shown in accordance with another embodiment. Here, the semiconductor device 500 as shown in FIG. 7 is obtained by modifying the electrostatic discharge protection element 700 in the semiconductor device 500 in FIG. 6, and only the differences between the two are described herein. As shown in FIG. 7, the well region 510 of the ESD protection device 700 can extend laterally to cover the body region 512 within the sub-region C2 and form a doped region adjacent to one of the isolation regions 506 of the doping region 520. 580 is substituted for one of the original doped regions 520, and the conductive member 526 is still bonded to the doped region 520 and the doped region 580. Doped region 580 has a first conductivity type opposite to well region 510 and has a doping concentration that is higher than the doping concentration of well region 510. In this embodiment, by changing the implementation of the well region in the sub-region C2 and adding the addition of the doping region 580 replacing one of the original doping regions 520, the sub-region C2 of FIG. 6 can be further The gate-grounded transistor component is replaced by a silicon controlled rectifier (SCR) component.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can The scope of protection of the present invention is defined by the scope of the appended claims.

500‧‧‧Semiconductor device

502‧‧‧Semiconductor substrate

504‧‧‧Semiconductor layer

506‧‧‧Isolation components

508‧‧‧ Well Area

510‧‧‧ Well Area

512‧‧‧ main body area

514‧‧‧ gate structure

516‧‧‧Doped area

518‧‧‧Doped area

520‧‧‧Doped area

570‧‧‧Doped area

521‧‧‧Electrical components

522‧‧‧Electrical components

524‧‧‧Electrical components

526‧‧‧Electrical components

528‧‧‧Electrical components

600‧‧‧High voltage semiconductor components

700‧‧‧Electrostatic discharge protection components

C‧‧‧active area

C1, C2‧‧‧ sub-area

Claims (12)

A semiconductor device comprising: a semiconductor layer having an active region defined thereon, wherein the active region includes a first sub-region and a second sub-region; a first doped region disposed in one of the semiconductor layers Across the first sub-region and the second sub-region; a high-voltage semiconductor component disposed on the semiconductor layer of the first sub-region of the active region, wherein the high-voltage semiconductor component includes the first portion of the active region a portion of the first doped region in the semiconductor layer of a sub-region; and an electrostatic discharge protection device disposed on the semiconductor layer of the second sub-region of the active region, wherein the electrostatic discharge protection component comprises Another portion of the first doped region within the semiconductor layer of the second sub-region of the active region. The semiconductor device of claim 1, wherein the high voltage component is a lateral double diffused MOS transistor or an insulated gate bipolar transistor. The semiconductor device according to claim 1, wherein the ESD protection device is a gate-grounded MOS transistor, a thyristor or a diode. The semiconductor device of claim 2, wherein the high voltage component is a lateral double diffused MOS transistor, comprising: a well region disposed in a portion of the semiconductor layer, wherein the doped region is disposed In a portion of the well region; a body region disposed in one of the semiconductor layers; a second doped region disposed in one of the body regions; an isolation member disposed on a surface of one of the well regions; a gate structure disposed in the body region, the well region, and the well region And a portion of the semiconductor layer and the isolation element between the body region; and a plurality of conductive members disposed on the first doped region, the second doped region and the gate structure Connecting the first doped region, the second doped region and the gate structure respectively, wherein the semiconductor layer and the body region have a first conductive property, and the first doped region, the first The second doped region and the well region have a second conductive characteristic opposite one of the first conductive characteristics. The semiconductor device of claim 2, wherein the first conductivity type is a P type and the second conductivity type is an N type. The semiconductor device of claim 3, wherein the electrostatic discharge protection device is a gate-grounded MOS transistor, comprising: a well region disposed in a portion of the semiconductor layer, wherein the first doping The fauna is disposed in one of the well regions; a body region is disposed in one of the semiconductor layers; a second doped region is disposed in one of the body regions; and a third doped region is disposed in the portion a portion of the well region adjacent to the first doped region; an isolation member disposed on a surface of one of the well regions; a gate structure disposed in the body region, the well region, the well region, and the a portion of the semiconductor layer and the isolation element between the body regions; and a first conductive member disposed on the first doped region within the well region to connect to the first region of the well region Doped region a second conductive member disposed on the second doped region of the body region and the gate structure to be coupled to the second doped region and the gate structure in the body region, wherein the semiconductor layer And the body region has a first conductivity characteristic, and the first doping region, the second doping region, the third doping region and the well region have a second conductivity characteristic opposite to the first conductivity characteristic . The semiconductor device of claim 6, wherein the first conductivity type is a P type and the second conductivity type is an N type. The semiconductor device of claim 3, wherein the electrostatic discharge protection device is a controlled rectifier, comprising: a well region disposed in a portion of the semiconductor layer, wherein the doped region is disposed in the well region a body portion disposed in one of the well regions; a second doped region disposed in one of the body regions; an isolation member disposed on a surface of one of the well regions; a gate structure disposed on the body region, the well region, the well region and a portion of the semiconductor layer between the isolation elements; a third doped region disposed in one of the well regions adjacent to the a first doped region and the isolation element; a first conductive member disposed on the first doped region in the well region to be respectively coupled to the first doped region and the third region in the well region a doped region; and a second conductive member disposed on the second doped region of the body region and the gate structure to connect the second doped region and the gate structure in the body region Wherein the semiconductor layer, the body region and the third doped region have a first conductive And the first doped region, the second doped region and the well The region has a second conductivity characteristic that is opposite to one of the first conductivity characteristics. The semiconductor device of claim 8, wherein the first conductivity type is a P type and the second conductivity type is an N type. The semiconductor device of claim 1, wherein the active region has a contour of a circle, an ellipse or a polygon as viewed from above. The semiconductor device of claim 1, wherein the first sub-region and the second sub-region of the active region are adjacent. The semiconductor device of claim 1, wherein the first sub-region and the second sub-region of the active region have a symmetrical profile from above.