TW201603156A - Wafer and method for testing the same - Google Patents

Abstract

The present disclosure provides a wafer, including: a first chip and a second chip juxtaposed with the first chip. The first chip and the second chip respectively have corresponding first chip conductive pads and second chip conductive pads at their opposite sides. A plurality of external conductive pads is disposed between the first chip and second chip. Each external conductive pad electrically connects the corresponding first chip conductive pad and second chip conductive pad. The present disclosure also provides a method for testing the wafer.

Description

Wafer and its test method

The present invention relates to wafers and test methods thereof, and in particular to a wafer having a conductive pad and a test method therefor.

In recent years, as the demand for multi-chip packages has increased, the demand for known good dies has also increased.

In order to be able to measure which wafers are good wafers at the wafer level, it is necessary to perform a performance test on each of the wafers in multiple stages in the wafer level. For example, each wafer must be tested at high and low temperatures to see if each wafer is functioning properly.

However, this test step leaves defects on the conductive pads of the wafer, reducing the yield of subsequent processing steps. And the more this test step, the more serious the defects left on the conductive pads. In addition, the conventional wafer measurement method must measure the performance of each probe next time (ie, contact terminal) for each wafer, so the measurement step is time consuming.

Therefore, there is a need in the industry for a wafer and its test method that allows the test steps to not affect the yield of subsequent process steps, and this test method can shorten the time required for conventional measurement steps.

The invention provides a wafer comprising: a first wafer; a second crystal a sheet, disposed alongside the first wafer, wherein the opposite sides of the first wafer and the second wafer each have a corresponding plurality of first wafer conductive pads and a plurality of second wafer conductive pads; and a plurality of first external conductive pads, The first outer conductive pad is electrically connected to the corresponding first and second wafer conductive pads.

The invention further provides a method for testing a wafer, comprising: providing a wafer, comprising: a first wafer; and a second wafer disposed side by side with the first wafer, wherein the opposite sides of the first wafer and the second wafer respectively have corresponding a plurality of first wafer conductive pads and a plurality of second wafer conductive pads; and a plurality of first external conductive pads disposed between the first wafer and the second wafer, and each of the first external conductive pads and the corresponding first a wafer conductive pad and a second wafer conductive pad are electrically connected; a tester is provided, having a plurality of contact terminals; and a plurality of contact terminals are electrically connected to the plurality of first external conductive pads to test the first wafer and/or the first Two wafers.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments of the present invention are described in detail below.

3-3‧‧‧ segments

100‧‧‧ wafer

110‧‧‧ wafer

110a‧‧‧First wafer

110b‧‧‧second chip

110c‧‧‧ third chip

110d‧‧‧fourth wafer

120a‧‧‧First wafer conductive pad

120a ₂ ‧‧‧First wafer conductive pad

120b‧‧‧Second wafer conductive pad

120b ₂ ‧‧‧Second wafer conductive pad

120c‧‧‧third wafer conductive pad

120c ₂ ‧‧‧third wafer conductive pad

120d‧‧‧fourth wafer conductive pad

120d ₂ ‧‧‧fourth wafer conductive pad

130a‧‧‧First external conductive pad

130b‧‧‧Second external conductive pad

130c‧‧‧ Third external conductive pad

140a‧‧‧Wire

140b‧‧‧Wire

140c‧‧‧ wire

150‧‧‧Switch circuit

160‧‧‧Inline structure

170‧‧‧ Guide hole

180‧‧‧Tester

190a‧‧‧Contact terminal

190b‧‧‧Contact terminal

190c‧‧‧Contact terminal

SC‧‧‧Cut Road

SC1‧‧‧ cutting road

SC2‧‧‧ cutting road

SC3‧‧‧ cutting road

S‧‧‧Substrate

M _top ‧‧‧Top metal layer

M _n ‧‧‧ metal layer

M _n-1 ‧‧‧ bottom metal layer

D _top ‧‧‧Dielectric layer

D _n ‧‧‧ dielectric layer

D _n-1 ‧‧‧ dielectric layer

1 to 2 are top views of a wafer according to an embodiment of the present invention; FIG. 3 is a cross-sectional view of a wafer according to an embodiment of the present invention; and FIGS. 4 to 6 are wafers in an embodiment of the present invention. Sectional view in .

In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element to another. It can be understood that if the device will be shown If you flip it upside down, the component described on the "lower" side will become the component on the "higher" side.

In the embodiment of the invention, the external conductive pad is used to replace the wafer conductive pad, so that the wafer conductive pad of the wafer does not cause defects due to direct contact with the tester during the testing step.

Referring to Figure 1, there is shown a top view of a wafer of an embodiment of the present invention. Wafer 100 includes a plurality of wafers 110 formed thereon. In an embodiment, the wafer 100 may divide the plurality of wafers 110 by a plurality of predetermined scribe lines SC. Wafer 100 is a semiconductor wafer, such as a germanium wafer. In addition, the semiconductor wafer may also be an elemental semiconductor, including germanium; a compound semiconductor including germanium carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including germanium Alloy, phosphorus arsenide alloy, arsenic aluminum indium alloy, arsenic aluminum gallium alloy, arsenic gallium alloy, indium gallium arsenide alloy and/or phosphorus arsenide gallium alloy or a combination thereof. In addition, the wafer 100 may also be an insulating layer overlying a semiconductor.

The wafer 110 can be a variety of memories, such as virtual static random access memory (Pseudo SRAM), low power single access synchronous dynamic random access memory, low power dual access synchronous dynamic random access memory, synchronization Dynamic random access memory, double data transfer rate synchronous dynamic random access memory, side-by-side flash memory, tandem flash memory. In addition, the wafer 110 can also be a photovoltaic element, a microelectromechanical system, a microfluidic system, a physical sensor, a light emitting diode, a solar cell, a radio frequency component, an accelerometer, a gyroscope, a micro brake, a surface acoustic wave component, and a pressure sensing. , inkjet head, power MOS half-effect transistor module, or any other similar component.

Next, see Figure 2, which is part A of wafer 100 of Figure 1. Magnified view. As shown in FIG. 2, the wafer 100 includes a first wafer 110a and a second wafer 110b. The second wafer 110b is juxtaposed with the first wafer 110a, and the opposite sides of the first wafer 110a and the second wafer 110b each have a corresponding plurality of first wafer conductive pads 120a and a plurality of second wafers. Pad 120b. In addition, the wafer 100 includes a plurality of first outer conductive pads 130a disposed between the first wafer 110a and the second wafer 110b. Each of the first outer conductive pads 130a is electrically connected to the corresponding first and second wafer conductive pads 120a, 120b, for example, by a plurality of wires disposed between the first and second wafers 110a and 110b. The first wafer conductive pad 120a, the second wafer conductive pad 120b and the first outer conductive pad 130a are electrically connected. The materials of the first wafer conductive pad 120a, the second wafer conductive pad 120b and the first outer conductive pad 130a may be single layer or multiple layers of gold, chromium, nickel, platinum, titanium, aluminum, tantalum, niobium, copper, etc. Combination or other highly conductive metal material.

When testing a conventional wafer, the contact terminals (such as probes) of the tester directly contact the wafer conductive pads, leaving defects on the wafer conductive pads and reducing the yield of subsequent processes. For example, if a wire is to be bonded to the wafer conductive pad in a subsequent process, the defect left on the conductive pad during the test step may cause the wire bond to fail. In contrast, since the wafer 100 of the present invention includes the first outer conductive pad 130a, the contact terminals of the tester can directly contact the first outer conductive pad 130a in the test step without contacting the first wafer conductive pad. 120a and a second wafer conductive pad 120b. Therefore, after the end of the testing step, the first wafer conductive pad 120a and the second wafer conductive pad 120b can remain intact and have no defects, so that the yield of the subsequent process can be further improved. For example, the subsequent bonding of the wires to the first wafer conductive pad 120a and the second wafer conductive pad 120b can be improved. Yield.

In addition, the wafer of the present invention can simultaneously measure the wafers on both sides of an external conductive pad during testing, thereby greatly reducing the cost and reducing the time required for the process. This section will be described in detail in the wafer test method of the present invention.

Continuing to refer to FIG. 2, in one embodiment, the first wafer 110a is the same as the second wafer 110b, and the first wafer 110a is disposed opposite to the second wafer 110b. As shown in FIG. 2, since the first wafer 110a is disposed opposite to the second wafer 110b, the first wafer 110a has an L-shaped designation (the first wafer conductive pad 120a with the arrow is closer to the lower side, and the arrow direction thereof The L-shaped label (to the right) and the second wafer 110b (the second wafer conductive pad 120b whose arrow is closer to the upper side, and whose arrow direction is leftward) is reversely disposed. In other words, the first wafer conductive pad 120a ₂ of the first wafer on the left side of the upper row and the second wafer conductive pad 120b ₂ of the second wafer 110b of the second row 110b of the second row 110b are the same conductive pads. .

Continuing to refer to FIG. 2, in one embodiment, the first outer conductive pad 130a is located on the scribe line SC1 between the first wafer 110a and the second wafer 110b. The width of the scribe line SC1 may be about 1.5-10 times the width of the first outer conductive pad 130a, for example, about 2-5 times. It should be noted that if the width of the scribe line SC1 is too wide, for example, about 10 times wider than the width of the first outer conductive pad 130a, the scribe line SC1 will occupy the area of the excess wafer 100, reducing the throughput of the wafer. . However, if the width of the scribe line SC1 is too narrow, for example, narrower than about 1.5 times the width of the first outer conductive pad 130a, cracks or defects generated during dicing are easily entered into the first wafer 110a and the second wafer 110b. , resulting in lower yield.

Referring to Fig. 3, there is shown a cross-sectional view of the wafer of the embodiment of the present invention extending along line 3-3 of Fig. 2. As shown in FIG. 3, the wafer 100 has a substrate S and an interconnect structure 160 formed thereon. The substrate S may be a semiconductor substrate such as a germanium substrate. The interconnect structure 160 includes metal layers M _top , M _n , M _n-1 , dielectric layers D _top , D _{n ,} and D _{n-1 ,} and via holes formed in the dielectric layer (eg, dielectric layer D _top ) 170, 170, 170. The metal layers M _top , M _n , and M _n-1 are electrically connected to each other. The material of the metal layers M _top , M _n , M _n-1 may be aluminum, aluminum beryllium copper alloy, copper, titanium, titanium nitride, tungsten, polycrystalline germanium, metal germanide, or a combination thereof, and the dielectric layer D _top The material of D _n and D _n-1 may be one or more layers of cerium oxide, cerium nitride, cerium oxynitride, borophosphonium silicate glass, phosphor bismuth glass, spin-on glass, low dielectric constant dielectric material, or Any other suitable dielectric material, or a combination of the above. The metal layer M _top is the top metal layer M _top , that is, it is the metal layer of the interconnect structure 160 closest to the first wafer conductive pad 120a, the second wafer conductive pad 120b and the first external conductive pad 130a. M _n of the metal layer on the top layer of a first metal layer under the metal layer M _top, metal layer M _n-1 located at the top of the second metal layer of the metal layer M _top.

In one embodiment, as shown in FIG. 3, the first wire 140a and 110a of the top wafer _top metal layer M at the same level, i.e., the wire 140a of the _top part of the top metal layer M and _top with the top metal layer may be M Defined in the same lithography and etching process. The wire 140a is electrically connected to the corresponding first wafer conductive pad 120a, the second wafer conductive pad 120b and the first outer conductive pad 130a. For example, the wire 140a can be electrically connected to the corresponding first wafer conductive pad 120a, the second wafer conductive pad 120b, and the first external conductive pad 130a through the via hole 170. The material of the via 170 may comprise copper, aluminum, tungsten, doped polysilicon, any other suitable electrically conductive material, or a combination thereof.

Although FIG. 3 only shows three of the metal layers M _top -M _n-1 of the interconnect structure 160, it is known to those skilled in the art that the interconnect structure 160 may include more or less. The metal layer of the layer may, for example, comprise only two metal layers or may comprise five metal layers. Further, the wire 140a may be provided in any of the metal layer, a metal layer is provided, for example M _n, interconnect structure 160 of the bottom metal layer or metal layers M _{1 n-.} Alternatively, the wire 140a may be in the same level as the first wafer conductive pad 120a, the second wafer conductive pad 120b, and the first outer conductive pad 130a.

Referring to FIG. 2, the wafer 100 may further include a switching circuit 150. The switch circuit 150 is electrically connected to the plurality of wires 140a to electrically or electrically insulate between the first outer conductive pad 130a and the first wafer conductive pad 120a, and to control the first outer conductive pad 130a and the second wafer. The conductive pads 120b are electrically connected or electrically insulated.

Referring to FIG. 2, the wafer 100 may further include a third wafer 110c. The third wafer 110c is disposed side by side with the first wafer 110a, and the second wafer 110b and the third wafer 110c are respectively located on opposite sides of the first wafer 110a. The opposite sides of the first wafer 110a and the third wafer 110c each have a corresponding plurality of first wafer conductive pads 120a and a plurality of third wafer conductive pads 120c. In addition, the wafer 100 may further include a plurality of second outer conductive pads 130b disposed between the first wafer 110a and the third wafer 110c. Each of the second outer conductive pads 130b is electrically connected to the corresponding first and second wafer conductive pads 120a and 120c. The material of the third wafer conductive pad 120c and the second outer conductive pad 130b may be single layer or multiple layers of gold, chromium, nickel, platinum, titanium, aluminum, tantalum, niobium, copper, the above combination or other conductive properties. Metal material.

Since the wafer 100 of the present invention can further include the second outer conductive pad 130b, the contact terminals of the tester can directly contact the second outer conductive pad 130b in the test step without contacting the third wafer conductive pad 120c. Therefore, in the test After the test step is completed, the third wafer conductive pad 120c can remain intact and has no defects, so that the yield of the subsequent process can be further improved.

In one embodiment, as shown in FIG. 2, the third wafer 110c is the same as the first wafer 110a and the second wafer 110b. The third wafer 110c is disposed opposite to the first wafer 110a, and the third wafer 110c is disposed in the same direction with respect to the second wafer 110b. Since the third wafer 110c is disposed opposite to the first wafer 110a and disposed in the same direction with respect to the second wafer 110b, the L-shaped label of the third wafer 110c (the third wafer conductive pad 120c with the arrow closer to the upper side, And the direction of the arrow is leftward, and the L-shaped label of the first wafer 110a (the first wafer conductive pad 120a whose arrow is closer to the lower side, and the direction of the arrow is rightward) is reversely disposed, and is opposite to the second wafer 110b. The L-shaped label (the arrow is closer to the upper second wafer conductive pad 120b, and its arrow direction is leftward) is disposed in the same direction. In other words, the third wafer conductive pad 120c _{2 of the} third wafer 110c located on the right side of the lower row and the first wafer conductive pad 120a ₂ and the second wafer 110b of the second row on the left side of the first row 110a. The second wafer conductive pads 120b ₂ located in the second right side of the lower row are the same conductive pads.

Continuing to refer to FIG. 2, in one embodiment, the second outer conductive pad 130b is located on the scribe line SC2 between the first wafer 110a and the third wafer 110c. In addition, a plurality of wires 140b are disposed between the first wafer 110a and the third wafer 110c, and are electrically connected to the corresponding first wafer conductive pad 120a, third wafer conductive pad 120c, and second external conductive pad 130b.

Furthermore, referring to FIG. 2, the wafer 100 may further include a fourth wafer 110d. The fourth wafer 110d is disposed side by side with the third wafer 110c, and the fourth wafer 110d and the first wafer 110a are respectively located on opposite sides of the third wafer 110c. The opposite sides of the fourth wafer 110d and the third wafer 110c each have a corresponding plurality of fourth The wafer conductive pad 120d and the plurality of third wafer conductive pads 120c. In addition, the wafer 100 may further include a plurality of third outer conductive pads 130c disposed between the third wafer 110c and the fourth wafer 110d. Each of the third outer conductive pads 130c is electrically connected to the corresponding third and fourth wafer conductive pads 120c and 120d. The materials of the fourth wafer conductive pad 120d and the third outer conductive pad 130c may be single or multiple layers of gold, chromium, nickel, platinum, titanium, aluminum, tantalum, niobium, copper, combinations thereof or other conductive properties. Metal material.

Since the wafer 100 of the present invention can further include the third outer conductive pad 130c, the contact terminals of the tester can directly contact the third outer conductive pad 130c in the test step without contacting the fourth wafer conductive pad 120d. Therefore, after the end of the test step, the fourth wafer conductive pad 120d can remain intact and has no defects, so the yield of the subsequent process can be further improved.

In one embodiment, as shown in FIG. 2, the fourth wafer 110d is the same as the first wafer 110a, the second wafer 110b, and the third wafer 110c. The fourth wafer 110d is disposed opposite to the third wafer 110c and the second wafer 110b, and the fourth wafer 110d is disposed in the same direction with respect to the first wafer 110a.

In some embodiments, the first wafer conductive pad 120a, the second wafer conductive pad 120b, the third wafer conductive pad 120c, the fourth wafer conductive pad 120d, the first outer conductive pad 130a, the second outer conductive pad 130b, and the first The three external conductive pads 130c can be formed by a deposition process and a process such as lithography and etching. The deposition process can be sputtering, electroplating, resistance heating evaporation, electron beam evaporation, chemical vapor deposition, or any other suitable deposition method. This etching process includes dry etching, wet etching, or a combination thereof.

It should be noted that although the above embodiment uses only four wafers as For example, it will be apparent to those skilled in the art that the structure of the present invention is applicable to structures having more wafers and is not limited to the embodiments of the present invention.

The advantages of the present invention are further apparent from the description of the following test methods. 4-6 are cross-sectional views of the wafer of the embodiment of the present invention which are depicted in the test step by the line 3-3 of Fig. 2. In one embodiment, as shown in FIG. 4, the wafer 100 described above is first provided. Next, a tester 180 is provided. This tester 180 has a plurality of contact terminals 190a. It should be noted that since FIG. 4 is a cross-sectional view, although the tester 180 has a plurality of contact terminals 190a, FIG. 4 only shows one contact terminal 190a.

Next, the plurality of contact terminals 190a are electrically connected to the plurality of first outer conductive pads 130a to test the first wafer 110a and/or the second wafer 110b. For example, each of the external conductive pads can be electrically connected or electrically insulated from the wafer conductive pads on both sides thereof by the switch circuit 150. In an embodiment, as shown in FIG. 2 and FIG. 4, the switch circuit 150 can control the electrical connection between the first outer conductive pad 130a and the first wafer conductive pad 120a and the second wafer conductive pad 120b. The tester 180 can simultaneously test the first wafer 110a and the second wafer 110b. In other embodiments, the switch circuit 150 can control one of the first outer conductive pad 130a and the first wafer conductive pad 120a, and the first outer conductive pad 130a and the second wafer conductive pad 120b to be electrically connected. The other is electrically insulated so that the tester 180 can test the first wafer 110a or the second wafer 110b separately.

The contact terminal 190a can include a pogo pin, a probe pin, a conductive pad, or any other suitable contact terminal.

In another embodiment, as shown in FIG. 5, the tester 180 includes Contacting the terminals 190a, 190b, and the testing method of the wafer 100 further includes electrically connecting the plurality of contact terminals 190a, 190b to the plurality of first outer conductive pads 130a and the plurality of second outer conductive pads 130b, respectively, to test the first Wafer 110a, second wafer 110b, and/or third wafer 110c.

In another embodiment, as shown in FIG. 6, the tester 180 includes contact terminals 190a, 190b, and 190c, and the test method of the wafer 100 further includes a plurality of contact terminals 190a, contact terminals 190b, and contact terminals 190c, respectively. Simultaneously electrically connecting the plurality of first outer conductive pads 130a, the plurality of second outer conductive pads 130b, and the plurality of third outer conductive pads 130c to test the first wafer 110a, the second wafer 110b, the third wafer 110c, and/or The fourth wafer 110d.

The traditional wafer measurement method must separately measure the next probe of each wafer (that is, the contact pad is electrically connected to the corresponding conductive pad of each wafer) to measure its performance, or it needs several times the number of probes to simultaneously Test multiple wafers. For example, if a wafer has four wafers to test, the next four probes are required, or four times the number of probes is required to test four wafers simultaneously. On the contrary, since the testing method of the wafer 100 of the present invention is measured by electrically connecting the external conductive pads between the wafers, the wafers on both sides of the external conductive pads can be simultaneously measured, thereby greatly reducing the required exploration. The number of stitches is measured in the same step of the lower probe. For example, in the embodiment shown in FIG. 6, the contact terminal 190a, the contact terminal 190b, and the contact terminal 190c are electrically connected to the plurality of first outer conductive pads 130a, the plurality of second outer conductive pads 130b, and the plurality of The third outer conductive pad 130c can measure the performance of the first wafer 110a, the second wafer 110b, the third wafer 110c, and/or the fourth wafer 110d in the same step of lowering the probe, compared to the conventional measuring method. Can significantly reduce costs and reduce process Time required.

It should be noted that although the above embodiment illustrates the wafer measuring method of the present invention with only four wafers as an example, it is known to those skilled in the art that the measuring method of the present invention can be applied to measuring crystals having more wafers. The circle is not limited to the embodiments of the invention.

In summary, since the wafer of the present invention includes the external conductive pad, the contact terminals of the tester can directly contact the external conductive pad in the test step without contacting the wafer conductive pad. Therefore, after the test step is completed, the wafer conductive pad of the wafer of the present invention can remain intact and has no defects, so that the yield of the subsequent process can be further improved. In addition, since the test method of the wafer of the present invention is measured by electrically connecting the external conductive pads between the wafers, the number of wafers measured in the same step of the lower probe can be increased, and the cost and the reduction are greatly reduced. The time required for the process.

3-3‧‧‧ segments

100‧‧‧ wafer

110a‧‧‧First wafer

110b‧‧‧second chip

110c‧‧‧ third chip

110d‧‧‧fourth wafer

120a‧‧‧First wafer conductive pad

120a ₂ ‧‧‧First wafer conductive pad

120b‧‧‧Second wafer conductive pad

120b ₂ ‧‧‧Second wafer conductive pad

120c‧‧‧third wafer conductive pad

120c ₂ ‧‧‧third wafer conductive pad

120d‧‧‧fourth wafer conductive pad

120d ₂ ‧‧‧fourth wafer conductive pad

130a‧‧‧First external conductive pad

130b‧‧‧Second external conductive pad

130c‧‧‧ Third external conductive pad

140a‧‧‧Wire

140b‧‧‧Wire

140c‧‧‧ wire

150‧‧‧Switch circuit

SC1‧‧‧ cutting road

SC2‧‧‧ cutting road

SC3‧‧‧ cutting road

Claims (13)

A wafer comprising: a first wafer; a second wafer disposed side by side with the first wafer, wherein the opposite sides of the first wafer and the second wafer each have a corresponding plurality of first wafer conductive pads and a plurality of second wafer conductive pads; and a plurality of first outer conductive pads disposed between the first wafer and the second wafer, and each of the first outer conductive pads and the corresponding first wafer conductive pad And electrically connecting the second wafer conductive pads. The wafer of claim 1, wherein the first wafer is the same as the second wafer, and the first wafer is disposed opposite to the second wafer. The wafer of claim 1, further comprising: a third wafer disposed side by side with the first wafer, wherein the second wafer and the third wafer are respectively located on opposite sides of the first wafer, wherein Each of the first wafer and the third wafer has a corresponding plurality of first wafer conductive pads and a plurality of third wafer conductive pads; and a plurality of second external conductive pads are disposed on the first wafer and the first wafer Between the third wafers, each of the second outer conductive pads is electrically connected to the corresponding first and second wafer conductive pads. The wafer of claim 3, wherein the third wafer is the same as the first wafer and the second wafer, the third wafer is oppositely disposed with respect to the first wafer, and the third wafer It is disposed in the same direction with respect to the second wafer. The wafer of claim 1, wherein the plurality of first outer conductive pads are located on a scribe line between the first wafer and the second wafer. For example, the wafer described in the first paragraph of the patent application includes: A plurality of wires are disposed between the first wafer and the second wafer, and electrically connected to the corresponding first wafer conductive pad, the second wafer conductive pad and the first external conductive pad. The wafer of claim 6, wherein the plurality of wires are at the same level as the top metal layer of the first wafer. The wafer of claim 6, further comprising: a switch circuit electrically connecting the plurality of wires to control between the plurality of first outer conductive pads and the plurality of first wafer conductive pads or The plurality of first outer conductive pads and the plurality of second wafer conductive pads are electrically connected or electrically insulated. A method for testing a wafer, comprising: providing a wafer, comprising: a first wafer; and a second wafer disposed side by side with the first wafer, wherein the first wafer and the second wafer have opposite phases Corresponding a plurality of first wafer conductive pads and a plurality of second wafer conductive pads; and a plurality of first external conductive pads disposed between the first wafer and the second wafer, and each of the first external conductive pads Corresponding to the first wafer conductive pad and the second wafer conductive pad; providing a tester having a plurality of contact terminals; and electrically connecting the plurality of contact terminals to the plurality of first external conductive pads To test the first wafer and/or the second wafer. The method for testing a wafer according to claim 9 , wherein the wafer further comprises: a third wafer disposed side by side with the first wafer, and the second wafer and the third wafer are respectively located at the first The opposite side of a wafer, wherein the first wafer and the The opposite sides of the third wafer each have a corresponding plurality of first wafer conductive pads and a plurality of third wafer conductive pads; and a plurality of second external conductive pads are disposed between the first wafer and the third wafer, And each of the second external conductive pads is electrically connected to the corresponding first and second wafer conductive pads; and the method for testing the wafer further comprises: electrically connecting the plurality of contact terminals simultaneously The plurality of first outer conductive pads and the plurality of second outer conductive pads to test the first wafer, the second wafer, and/or the third wafer. The method of testing a wafer according to claim 9, wherein the first wafer is the same as the second wafer, and the first wafer is disposed opposite to the second wafer. The method for testing a wafer according to claim 10, wherein the third wafer is the same as the first wafer and the second wafer, and the third wafer is reversely disposed with respect to the first wafer, and the The third wafer is disposed in the same direction with respect to the second wafer. The method for testing a wafer according to claim 9, wherein the wafer further comprises: a plurality of wires disposed between the first wafer and the second wafer, and electrically connecting the corresponding first a wafer conductive pad, the second wafer conductive pad, and the first outer conductive pad.