TW201547024A - Transistor device structure - Google Patents

Abstract

A transistor device structure including a substrate, a first transistor layer and a second transistor layer is provided. The second transistor layer is disposed between the substrate and the first transistor layer. The first transistor layer includes an insulating structure and a first transistor unit. The insulating structure disposed on the second transistor layer has two trenches, wherein the two trenches define a protruding part. The first transistor unit disposed on the insulating structure includes a first gate structure, a first source/drain region and a channel. Besides, the first source/drain region defined in one of the two tranches has a first semiconductor layer inside. The channel defined between the protruding part and the first gate structure is composed of a second semiconductor layer.

Description

Transistor element structure

The present invention relates to a transistor element structure, and more particularly to a three-dimensional stacked transistor element structure.

The conventional technology is faced with two major problems in the fabrication of ultra-thin channel transistors below 30 nm. First, the ultra-thin channel layer causes the series impedance to rise sharply. Second, in the dry etching metal contact window to the source/汲The polar regions are susceptible to over-etching through the source/drain layers, causing component failure.

In this regard, the above two problems can be solved by a raised source/drain or a recess source/drain. However, there are limitations to applying it to a three-dimensional stacked structure wafer. Since the lift-up structure must be fabricated through a high-temperature epitaxial process (greater than 800 ° C), the characteristics of the bottom transistor are destroyed. In addition, although the recessed structure can be fabricated by low-temperature dry etching, the dry etching process is easy to make. Interface surface roughness caused by increased surface roughness or plasma bombardment, and deterioration of component characteristics, is not conducive to the development of high-performance semiconductor components. In view of this, how to develop high-efficiency three-dimensional stacked structure wafers is the main purpose of the development of this case.

The invention provides a transistor element structure, which can not only adopt a low whole process The warm budget process improves component characteristics, and also effectively reduces series impedance and defect density, as well as avoiding the problem of over-etching.

To achieve the above advantages or other advantages, a transistor element structure according to an embodiment of the present invention includes a substrate, a first transistor layer, and a second transistor layer. The second transistor layer is disposed between the substrate and the first transistor layer. Wherein, the first transistor layer comprises an insulating structure and a first transistor unit. The insulating structure is disposed above the second transistor layer and has two grooves, the two grooves defining protrusions. The first transistor unit is disposed above the insulating structure and includes a first gate structure, a first source/drain region, and a channel region. The first source/drain region is disposed in one of the two recesses and has a first semiconductor layer. The channel region is disposed between the protruding portion and the first gate structure and is composed of a second semiconductor layer.

In an embodiment of the invention, the foregoing transistor component structure further includes a back gate structure disposed in the protrusion and isolated from the channel region and the first source/drain region.

In an embodiment of the invention, the first source/drain region further includes a conductor layer disposed conformally on the bottom of the two recesses and the sidewall surface, and the first polycrystalline semiconductor layer is disposed on the conductor layer. .

In an embodiment of the invention, the first semiconductor layer and the second semiconductor layer are polycrystalline semiconductor material layers, and the polycrystalline semiconductor material layer comprises bismuth (Si), germanium (Ge), germanium telluride (SiGe). Or alumina (Al ₂ O ₃ ), both having a crystallite diameter greater than 1 micron.

In an embodiment of the invention, the first semiconductor layer and the second semiconductor layer are single crystal semiconductor material layers, and the single crystal semiconductor material layer comprises bismuth (Si), germanium (Ge), germanium telluride (SiGe). , four or six groups of materials such as molybdenum selenide (MoSe ₂ ), tungsten sulfide (WS ₂ ) and their compounds or three or five family materials.

In an embodiment of the invention, the first transistor layer is further included Including another first transistor unit, and the first transistor unit and the other first transistor unit are respectively N-type and P-type; and the second transistor layer further includes another second transistor unit, and The two transistor units and the other second transistor unit are N-type and P-type, respectively.

In an embodiment of the invention, the first transistor layer and the second transistor layer have the same structure.

In an embodiment of the invention, the transistor structure further includes a plurality of third transistor layers disposed between the first transistor layer and the second transistor layer.

In an embodiment of the invention, the thickness of the second semiconductor layer of the channel region is less than 30 nm.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

10, 20‧‧‧Optoelectronic component structure

50, 60, 601‧‧‧ substrates

100, 200, 300‧‧‧ transistor layer

101‧‧‧Insulation structure

150, 240, 1011, 1012‧‧‧ insulating material layer

101a, 101b‧‧‧ grooves

101c‧‧‧Protruding

110‧‧‧Amorphous semiconductor layer

112‧‧‧ polycrystalline semiconductor layer

120‧‧‧ gate structure

121, 231‧‧ ‧ gate dielectric layer

122, 232‧‧ ‧ gate electrode

123, 233‧‧ ‧ spacer

125‧‧‧Metal semiconductor compound layer

131, 431‧‧‧ source area

132, 432‧‧ ‧ bungee area

133, 602‧‧‧ semiconductor layer

140‧‧‧Channel area

160, 460‧‧‧through holes

230‧‧‧Optocell unit

302, 402‧‧‧ Back gate structure

310a, 310b‧‧‧ conductor layer

C2‧‧‧ interface

1 is a schematic cross-sectional view showing an embodiment of a transistor element structure developed by the present invention; FIG. 2 is a cross-sectional view showing an embodiment of a transistor element structure developed by the present invention; and FIG. 3A is a diagram showing the development of the present invention. FIG. 3B is a schematic cross-sectional view showing an embodiment of a transistor element structure developed by the present invention; FIG. 4A is a schematic cross-sectional view showing an embodiment of a transistor element structure developed by the present invention; 4B is a cross-sectional view showing an embodiment of a transistor element structure developed by the present invention; and FIGS. 5A to 5L are partial cross-sectional views showing various embodiments of the transistor device structure developed by the present invention; FIG. 7A to FIG. 7E are schematic cross-sectional views showing a method of fabricating a transistor element structure according to an embodiment of the present invention; and FIG. 8A to FIG. A schematic flowchart of a manufacturing method of a transistor element structure according to an embodiment; and FIGS. 9A to 9E are schematic flow charts showing a manufacturing method of a transistor element structure according to an embodiment of the present invention.

Please refer to FIG. 1 , which is a cross-sectional view showing an embodiment of a transistor element structure developed by the present invention. The transistor element structure 10 includes a substrate 50, a first transistor layer 100, and a second transistor layer 200 to form a monolithic 3D stacked device structure. The second transistor layer 200 is disposed between the substrate 50 and the first transistor layer 100. The material of the substrate 50 may be a semiconductor such as germanium or an insulating material such as glass, and the substrate 50 may also be a flexible substrate.

In the embodiment, the first transistor layer 100 may include the insulating structure 101 and the first transistor unit. The first transistor unit is disposed above the insulating structure 101. The insulating structure 101 can be disposed above the second transistor layer 200, and has two grooves 101a and 101b, and the two grooves 101a, 101b define a protruding portion 101c. In other words, the protruding portion 101c of the insulating structure 101 is located at two grooves. Among 101a and 101b. The foregoing insulating structure 101 is, for example, a silicon oxide. Worth to talk about The top surface of the protruding portion 101c may be a flat surface or may be slightly lower than or coplanar with the top surface of one of the recesses 101a and 101b away from the protruding portion 101c.

The first transistor unit may include a gate structure 120, a source region 131, a drain region 132, and a channel region 140. The gate structure 120 can be aligned with the protrusion 101c. It should be noted that the source region 131 and the drain region 132 may be respectively defined in the grooves 101a and 101b of the insulating structure 101, that is, a so-called embedded source/drain is formed. In addition, the source region 131 and the drain region 132 each have a first semiconductor layer 133. The ultra-thin channel region 140 is defined between the gate structure 120 and the protruding portion 101c of the insulating structure 101, and may be composed of a second semiconductor layer, and may have a thickness of less than 30 nm or even less than 10 nm. The first semiconductor layer and the second semiconductor layer may both be a single crystal semiconductor material layer or a polycrystalline semiconductor material layer, and may have the same or different materials. The single crystal semiconductor material layer may include four or six chemical elements such as germanium (Si), germanium (Ge), germanium telluride (SiGe), molybdenum selenide (MoSe ₂ ), tungsten sulfide (WS ₂ ), or the like. For example, a tri- or five-member chemical element. The polycrystalline semiconductor material layer may comprise germanium (Si), germanium (Ge), germanium telluride (SiGe) or aluminum oxide (Al ₂ O ₃ ).

The gate structure 120 can include a gate dielectric layer 121, a gate electrode 122, and a spacer 123. The gate dielectric layer 121 is disposed between the channel region 140 and the gate electrode 122, and the spacer wall 123 surrounds the sidewalls of the gate electrode 122 and the gate dielectric layer 121.

In the present embodiment, the surface of the source region 131 and the drain region 132 may have a metal semiconductor compound layer 125, which may be disposed on the surface of the first semiconductor layer 133, to further reduce the series resistance of the transistor element structure 10. The foregoing metal semiconductor compound layer 125 is, for example, a metal telluride or a metal telluride, and may also contain a dopant such as a tri- or five-group chemical element therein. It is to be noted that the upper surface of the metal semiconductor compound layer 125 may be coplanar with the upper surface of the channel region 140.

The first transistor layer 100 further includes an insulating material layer 150 disposed on the first Above a transistor unit. One of the layers of insulating material 150 may be greater than the thickness of the gate structure 120. The transistor component 10 can further include a through hole 160 extending through the insulating material layer 150 to the source region 131 or the drain region 132. The through hole 160 has a conductive material and can be in electrical contact with the first semiconductor layer 133. Or direct contact.

In addition, the second transistor layer 200 stacked between the substrate 50 and the first transistor layer 100 may include the second transistor unit 230 and the insulating material layer 240. The second transistor unit 230 may include a gate dielectric layer 231, a gate electrode 232, and a spacer 233. The second transistor unit 230 can be aligned with the protrusion 101c and the gate structure 120. The insulating material layer 240 is, for example, cerium oxide, and belongs to the junction of the first transistor layer 100 and the second transistor layer 200, and the insulating structure 101.

In summary, the transistor element structure 10 of the embodiment of the present invention can be widely applied to a laminated three-dimensional stacked transistor structure, having a flat ultra-thin channel region, and an open circuit voltage of higher than 80 uA/um, I _on /I _off >10 ⁶ , and its embedded source / drain region is thicker, can avoid breaking through the source / drain region when forming the through hole, it is worth noting that this embodiment uses the embedded structure can use low temperature process (less than 500 ° C) This is done so that the second transistor layer 200 at the bottom is not destroyed, and the defect density of the recessed structure due to dry etching can be avoided.

2 is a cross-sectional view showing an embodiment of a transistor element structure developed by the present invention. The embodiment shown in FIG. 2 is mostly similar to the embodiment of FIG. 1, and is not described again. However, in the present embodiment, the transistor element structure 20 further includes a back gate structure 302 disposed in the protruding portion 101c of the insulating structure 101. In addition, the insulating structure 101 may include an insulating material layer 1011 and an insulating material layer 1012, which are sequentially disposed above the second transistor layer 200, and the insulating material layers 1011 and 1012 may jointly cover the back gate structure 302 for backing The gate structure 302 is isolated from the channel region 140 and may also isolate the back gate structure 302 from the source region 131 and the drain region 132. The material of the back gate structure 302 of this embodiment is, for example, tantalum nitride (TaN), nitrided. Titanium (TiN), aluminum/bismuth/copper alloy (AlSiCu) or a conductor material having a melting point above 650 °C.

Accordingly, in the transistor element structure 20 illustrated in FIG. 2, the transistor layer 200 and the transistor layer 100 are sequentially stacked on the substrate 50, and the transistor layer 100 has the aforementioned embedded source/drain region and super In addition to the benefits of the thin channel region, the electrical characteristics of the device can also be modulated by the gate structure (front gate) 120 and the back gate structure 302.

3A and 3B are cross-sectional views showing an embodiment of a transistor element structure developed by the present invention, respectively. In order to further reduce the series impedance of the transistor component and improve the component performance, the source/drain region may further comprise a conductor layer. 3A is substantially the same as the transistor element structure 10 illustrated in FIG. 1 and FIG. 3B is substantially the same as the transistor element structure 20 illustrated in FIG. The main difference is that the source region 131 and the drain region 132 of the embodiment illustrated in FIG. 3A and FIG. 3B respectively include a conductor layer 310a and a conductor layer 310b disposed on the bottom and sidewalls of the recess 101a and the recess 101b, respectively. On the surface, the configuration of the conductor layer 310a and the conductor layer 310b may be conformed to the groove 101a and the groove 101b, respectively. In addition, the first semiconductor layer 133 is disposed on the conductor layers 310a and 310b, in other words, the conductor layer 310a is interposed between the first semiconductor layer 133 and the recess 101a, and covers the first semiconductor layer 133. The material of the conductor layer 310a and the conductor layer 310b is, for example, a metal, a highly doped polycrystalline semiconductor (a dopant concentration higher than the first semiconductor layer 133), or other high conductivity low Schottky barrier. Material.

Next, FIG. 4A and FIG. 4B are respectively schematic cross-sectional views showing an embodiment of a transistor element structure developed by the present invention. The transistor layer 300 and the transistor layer 100 are sequentially stacked on the substrate 50 of the embodiment, and the structures of the transistor layer 100 and the transistor layer 300 may be the same. For example, in FIG. 4A, the source of the transistor layer 300 is Region 431 and drain region 432, as well as transistor layer 100, are embedded source/drain regions, as well as ultra-thin, flat channel regions. In addition, one of the benefits of the embedded source/drain region is that the height of the through hole 460 between the transistor layer 100 and the transistor layer 300 can be shortened. Therefore, there is a lower vertical wiring impedance. The transistor layer 300 of FIG. 4B has the same structure as its transistor layer 100, for example, also has a back gate structure 402, embedded source/drain regions 431 and 432, an ultra-thin channel region, etc., according to which, FIG. 4B is penetrated. Hole 460 can also achieve the same benefits. In addition, if the transistor unit of the transistor layer 300 of FIG. 4A or FIG. 4B is changed to a raised source/drain (not shown), the height of the through hole between the two layers can be shortened. , can reduce the vertical wiring impedance.

5A-5L are partial cross-sectional views showing various embodiments of a transistor element structure developed by the present invention. It should be noted that the protrusion of the insulating structure of the transistor element structure may have a polygonal or circular arc profile in a certain section. Further, the protrusions of FIG. 5A to FIG. 5D may be deformed by the protrusions 101c illustrated in FIG. 1. For example, the cross-sectional shape of the protrusions 101c may be a rectangle, a circular arc, a hexagon, a trapezoid, etc., and Limited to this. 5E to FIG. 5L may be a deformation of the protruding portion illustrated in FIG. 2, wherein in FIG. 5E to FIG. 5H, the back gate structure 302 may have a polygonal or circular arc profile in a cross section, and the insulating structure 101 The back gate structure 302 can be conformally covered, and thus the cross section of the protrusion 101c also has a polygonal or circular arc profile. In addition, the insulating structure 101 may not conformally cover the back gate structure 302. For example, the distance between the sidewall of the back gate structure 302 and the source region 131 or the drain region 132 may be increased, as shown in FIG. 5I to FIG. This reduces the chance of leakage currents caused by the back gate structure bias.

It is worth mentioning that, depending on the different needs of the industry, the transistor element structure may stack two or more transistor layers, and each transistor layer may have one or more transistor units, and Any two transistor units may be combined with different embodiments such as the same type or different types (such as P type or N type), or have the same structure or different structures, for example, can be applied to the volatile memory based on the transistor unit. (volatile memory), a combination of different embodiments of non-volatile memory, logic circuits (such as inverters, NOR logic gates, or NAND logic gates). The invention is not limited to the above. For example, FIG. 6 is a transistor developed by the present invention. A schematic cross-sectional view of one embodiment of an element structure. The transistor layer 200 has two transistor units of P-type and N-type, respectively, and the transistor layer 100 stacked thereon has two transistor units of N-type and P-type, respectively, and both have back gates. The pole structure regulates the electrical properties of the component. The P-type transistor and the N-type transistor may be alternately arranged in the same transistor layer or different transistor layers.

7A-7E are schematic flow charts showing a method of fabricating a transistor element structure according to an embodiment of the present invention. The transistor element structure 10 shown in Fig. 1 can be completed by the present manufacturing method. Referring first to FIG. 7A, the method of fabricating a transistor element structure of the present invention includes the following steps: First, a substrate 50 is provided. Next, the above-described transistor unit 230 is formed on the substrate 50, wherein the transistor unit 230 may include a gate dielectric layer 231, a gate electrode 232, and a spacer 233. Next, an insulating material layer 240 is formed on the transistor unit 230 to complete the transistor layer 200.

It is worth noting that since this embodiment adopts a full low thermal budget technique (less than 500 ° C), all subsequent processes can be directly performed on the transistor layer 200 without damaging the transistor layer 200 that has been completed at the bottom. . First, an insulating material layer may be further formed on the insulating material layer 240, and then an etching process is performed to etch the insulating material layer into two grooves 101a and 101b, and the two grooves 101a and 101b define a protruding portion 101c. An insulating structure 101 is formed which is W-shaped in a cross-sectional shape.

Referring to FIGS. 7A and 7B in common, a thick amorphous semiconductor layer 110 is formed on the surface of the insulating structure 101, which fills the two grooves 101a and 101b and covers the protruding portion 101c of the insulating structure. The material of the amorphous semiconductor layer 110 is, for example, a semiconductor material of amorphous germanium or amorphous germanium. The manner of forming the amorphous semiconductor layer 110 is, for example, Plasma Enhanced Chemical Vapor Deposition (PECVD) or other low temperature deposition process, but the invention is not limited thereto.

Next, the amorphous semiconductor layer 110 is subjected to a crystallization process to It is convenient to induce micron-order crystal grains in the amorphous semiconductor layer, and convert the amorphous semiconductor layer 110 into a polycrystalline semiconductor layer, and the crystal grain diameter thereof is, for example, more than 1 micrometer, and the polycrystalline semiconductor layer having a larger crystal grain is closer to The characteristics of the single crystal can effectively reduce the probability of the component crossing the boundary area of the lattice to enhance the electrical performance of the component. The above crystallization process is, for example, a low-temperature green pulse-laser crystallization process or a microwave crystallization process.

Referring to FIG. 7C, next, a thickness reduction process is performed to obtain an ultra-thin planarized polycrystalline semiconductor layer 112 having an epitaxial structure such as a micron-sized crystal grain adjacent to the protruding portion 101c. The thickness reduction process described above is, for example, a chemical-mechanical planarization (CMP) of the nanometer or micrometer scale. The thickness reduction process described above can simultaneously improve the roughness of the surface of the polycrystalline semiconductor layer 112, so that the surface roughness is less than 0.5 nm, and the thickness of the polycrystalline semiconductor layer can be reduced.

After the thickness reduction process is completed, a multi-stage interface modification process is performed, which comprises: immersing the polycrystalline semiconductor layer 112 in the first mixed solution at 75 ° C for 10 minutes, wherein the composition of the first mixed solution includes NH ₄ OH:H ₂ O ₂ :H ₂ O=1:4:20; Next, the polycrystalline semiconductor layer 112 is immersed for 10 minutes under a second mixed solution of 75 ° C, wherein the composition of the second mixed solution includes HCl:H ₂ O ₂ :H ₂ O=1:1:6; Thereafter, the polycrystalline semiconductor film 112 is immersed in a pure H ₂ O ₂ solution at 75° C. for 10 minutes or by a plasma oxidation process to form Sacrificial oxide layer; Finally, the sacrificial oxide layer is removed by using a dilute solution of hydrofluoric acid, and the step of multi-stage low-temperature interface modification process is completed, and the manufacturing process of the polycrystalline semiconductor layer is completed. It is worth mentioning that the multi-stage low-temperature interface modification process described above can further reduce the thickness of the polycrystalline semiconductor film 112 having an epitaxial structure such as micron-sized grains by about 1 to 2 nm, and reduce the surface thereof. Defect density. Accordingly, the thickness of the polycrystalline semiconductor layer 112 adjacent to the protrusion 101c can be made less than 10 nm, and the crystal grain diameter can be greater than 1 μm.

Referring to FIG. 7D and FIG. 7E simultaneously, a gate structure 120 is formed on the surface of the polycrystalline semiconductor layer 112. The steps may include sequentially forming a gate dielectric layer 121 on the surface of the polycrystalline semiconductor layer 112, and then forming a gate. A gate electrode 122 is formed on the surface of the dielectric layer 121. Then, a spacer 123 is formed on the sidewalls of the gate dielectric layer 121 and the gate electrode 122, thereby completing the gate structure 120. Then, the exposed polycrystalline semiconductor layer 112 can be doped by using the gate structure 120 as a mask to form the source region 131 and the drain region 132, and the source region 131 and the drain region The polycrystalline semiconductor layer 112 between 132 is the aforementioned second polycrystalline semiconductor layer located in the channel region 140, and has an ultrathin thickness, for example, less than 10 nm.

Next, a metal semiconductor compound process is performed, and a metal layer is laid on the element structure of FIG. 7D, and a self-aligned property is used to chemically react with the metal on the surface of the exposed polycrystalline semiconductor layer 112 to form a metal. The semiconductor compound, for example, forms a metal compound layer 125 on the surface of the source region 131 and the drain region 132, and the polycrystalline semiconductor layer 112 that does not react with the metal is the first semiconductor layer 133 illustrated in FIG. 7E. Next, a thicker insulating material layer 150 is formed, covering the gate structure 120 and the metal semiconductor compound layer 125, and subsequent metal wiring is performed, for example, the through hole 160 to the source region are etched before the insulating material layer 150. The 131 or the drain region 132 is further filled with a conductive material for electrically connecting to the first semiconductor layer 133. Accordingly, an embodiment of the laminated three-dimensional stacked transistor element structure of the present invention is completed in a low temperature environment.

8A to 8C are partial flow diagrams showing a method of fabricating a transistor element structure according to an embodiment of the present invention. The structure of the transistor element illustrated in Fig. 1 of the present invention can be accomplished by the embodiment of the manufacturing method. The difference between the embodiment and the embodiment shown in FIG. 7A to FIG. 7E is that the present embodiment can adopt a smart cut method, and the semiconductor/insulating layer structure including the embedded source/drain region is used as a wafer. Wafer bonding technology re-bonds it to another wafer of completed components.

As shown in FIG. 8A, one side of the support substrate 60 is subjected to lithography etching and filling with an insulating material or the like to form the insulating structure 101 on one side of the support substrate 60. Next, a high dose of gas ions such as hydrogen or blunt gas is implanted into the support substrate 60 at an interface c2 extended by a broken line. Then, the insulating structure 101 is bonded to the completed transistor layer 200 on the substrate 50 away from one side of the supporting substrate 60, as shown in FIG. 8B, and then subjected to heat treatment to cause the plasma to generate many at the interface c2. The microbubbles are then joined into a single piece, thereby separating the support substrate 60 from the interface c2 up and down to discard the substrate 601 and the semiconductor layer 602. Referring to FIG. 8C, the semiconductor layer 602 can be subjected to a thickness reduction process (such as CMP), and an ultra-thin planarization channel region having a thickness of less than 10 nm can be obtained at the protruding portion 101c of the insulating structure 101. The subsequent process is the same as the steps shown in FIG. 7D and FIG. 7E, and will not be described again. It should be noted that the support substrate 60 of the present embodiment may be a single crystal semiconductor material layer. Therefore, the semiconductor layer of the channel region 140 or the semiconductor layer 133 of the embedded source/drain regions 131 and 132 may be formed. The material can be a single crystal semiconductor material layer, so that the transistor element structure has better performance. Accordingly, the combination of the wisdom cutting method can also be applied to the low-temperature budget laminated type three-dimensional stacked transistor element structure.

9A-9E are schematic flow charts showing a method of fabricating a transistor element structure according to an embodiment of the present invention. The structure of the transistor element shown in Fig. 2 of the present invention can be completed by the embodiment of the manufacturing method. Referring to FIG. 9A, in the embodiment, after the insulating material layer is formed over the transistor layer 200, the insulating material layer 1011 having a large recess is etched into the insulating material layer, and then, the insulating material layer 1011 is large. A back gate structure 302 is formed over the bottom surface of the recess, and an insulating material layer 1012 is further disposed, so that the insulating material layer 1012 conformally covers the insulating material layer 1011 and the back gate structure 302, thereby forming the foregoing insulating structure 101. The back gate structure 302 can be completely covered by the insulating structure 101, and the two grooves 101a and 101b of the insulating structure 101 are also defined. Next, the flow chart illustrated in FIGS. 9B to 9E and the manufacturing method illustrated in FIGS. 7B to 7E are The application process is the same, so it will not be described again. Accordingly, an embodiment of the low temperature budget laminated type three-dimensional stacked transistor element structure of the present invention is completed. In addition, this embodiment can also be completed in combination with the wisdom cutting method as described in FIG. 8A to FIG. 8B.

In summary, the laminated three-dimensional stacked transistor wafer fabricated by the present invention can have an ultra-thin channel region of single crystal or polycrystalline semiconductor, and the whole process is a low temperature process (less than 500 ° C), so there is no need to worry about the traditional high temperature process. Will destroy the electrical performance of the stacked components and the metal back gate structure. In addition, the combination of the embedded source/drain region in the laminated three-dimensional stacked transistor structural component not only avoids the metal contact window passing through the source/drain layer, but also preserves the surface uniformity of the ultra-thin channel. Moreover, the laminated three-dimensional stacked transistor component structure and the manufacturing method thereof of the present invention can also relatively improve the alignment accuracy between the plurality of transistor units. Furthermore, by the method of manufacturing the laminated three-dimensional stacked transistor of the present invention, the heterogeneous integration of the stacked three-dimensional stacked transistor wafers of different materials or different functions can be realized. In addition, the invention has the advantages of easy mass production, low cost, low working hours and the like.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10‧‧‧Optoelectronic component structure

50‧‧‧Substrate

100, 200‧‧‧ transistor layer

101‧‧‧Insulation structure

150, 240‧‧‧Insulation layer

101a, 101b‧‧‧ grooves

101c‧‧‧Protruding

120‧‧‧ gate structure

121, 231‧‧ ‧ gate dielectric layer

122, 232‧‧ ‧ gate electrode

123, 233‧‧ ‧ spacer

125‧‧‧Metal semiconductor compound layer

131‧‧‧Source area

132‧‧‧Bungee Area

133‧‧‧Semiconductor layer

140‧‧‧Channel area

160‧‧‧through holes

230‧‧‧Optocell unit

Claims (14)

A transistor component structure includes: a substrate, a first transistor layer, and a second transistor layer, wherein the second transistor layer is disposed between the substrate and the first transistor layer, and The first transistor layer includes: an insulating structure disposed above the second transistor layer, having two grooves, the two grooves defining a protrusion; and a first transistor unit disposed on the insulation structure The upper portion includes: a first gate structure disposed above the protrusion; a first source/drain region defined in one of the two grooves and having a first semiconductor layer; and a channel region And defined between the protrusion and the first gate structure, and is composed of a second semiconductor layer. The transistor component structure of claim 1, further comprising a back gate structure disposed in the protrusion and isolated from the channel region and the first source/drain region. The transistor device structure of claim 1, wherein the first source/drain region further comprises a conductor layer disposed conformally on the bottom and sidewall surfaces of one of the two grooves, and The first semiconductor layer is disposed on the conductor layer. The transistor component structure of claim 1, wherein the first transistor layer further comprises a first insulating material layer disposed on the first transistor unit. The structure of the transistor component as described in claim 4 of the patent application, which further includes A through hole extends through the first layer of insulating material into the first source/drain region. The transistor component structure of claim 1, wherein the first semiconductor layer and the second semiconductor layer are polycrystalline semiconductor material layers, each having a crystal grain diameter greater than 1 micron. The transistor device structure of claim 1, wherein the first source/drain region further has a metal semiconductor compound layer disposed above the first semiconductor layer. The transistor device structure of claim 1, wherein the first gate structure comprises: a first gate dielectric layer disposed above the channel region; and a first gate electrode disposed at Above the first gate dielectric layer; and a first spacer disposed on the sidewall of the first gate dielectric layer and the gate electrode. The transistor component structure of claim 1, wherein one of the protrusions has a polygonal or circular arc profile. The transistor element structure of claim 1, wherein the first semiconductor layer and the second semiconductor layer are single crystal semiconductor materials. The transistor component structure of claim 1, wherein the second transistor layer comprises: a second transistor unit, comprising: a second gate dielectric layer disposed on the second gate electrode of the substrate, disposed on the second gate dielectric layer; and a second spacer disposed on the second gate dielectric layer And a sidewall of the second gate electrode; and a second layer of insulating material covering the second transistor unit. The transistor component structure of claim 11, wherein the second transistor unit further comprises: a second source/drain region disposed above the surface of the substrate. The transistor component structure of claim 1, further comprising a plurality of third transistor layers disposed between the first transistor layer and the second transistor layer. The transistor component structure of claim 1, wherein a thickness of the second semiconductor layer of the channel region is less than 30 nm.