TW201534939A - Binning method of chips - Google Patents

Abstract

A binning method of chips is provided. In the method, the chips are operated on a first operating frequency to acquire first working currents of the chips, wherein the chips are located on a wafer which has not been separated. The first working currents of the chips are compared with a first threshold current corresponding to the first operating frequency to determine whether the chips pass a first current detecting process of the first operating frequency. When the chips pass the first current detecting process of the first operating frequency, a current delay value of each of the chips is determined through a process monitor of each of the chips. The current delay values of the chips are compared with a default delay value to determine the chip pass an efficiency monitor process. The chips are binned according to whether pass the first current detecting process of the first operating frequency and the efficiency monitor process.

Description

Wafer discrimination method

The present invention relates to a method for distinguishing wafers, and more particularly to a method for distinguishing wafers in a chip probing or circuit probing (CP) test phase.

In recent years, consumer electronic devices have various functions (for example, Internet access, drawing, writing, games, etc.), and thus integrated circuits (ICs) or chips (for example, A central processor unit (CPU), a microprocessor (microprocessor), etc., will determine the processing performance of the electronic device.

The wafer is formed by wafer dicing. Since wafer yield and performance can vary due to different wafer processing/semiconductor processes, multiple wafers with different operating frequencies may be available on the same wafer. Therefore, wafer manufacturers typically classify wafers according to their highest operating frequency to determine the pros and cons of the wafers and sell them to system plants or consumers at different models or prices. However, for traditional wafer discrimination methods, wafer manufacturers usually have to undergo final testing (FT) or even system on board; SB) test to classify all wafers. Therefore, there is a need to provide a quick and easy way to distinguish wafers.

The present invention provides a method of discriminating wafers that can distinguish wafers of different operating frequencies during the chip probing/circuit probing (CP) test phase.

The present invention provides a method of distinguishing wafers, the method of distinguishing comprising the following steps. The wafer is operated at a first operating frequency to obtain a first operating current of the wafer in accordance with the first operating frequency, wherein the wafer is on the undivided wafer. Comparing the first threshold current corresponding to the first operating current of the wafer with the first operating frequency to determine whether the wafer passes the first current detecting procedure of the first operating frequency according to the first threshold current. When the wafer passes the first current detecting program of the first operating frequency, the current delay value of each wafer is judged by a process monitor unit in each wafer. The current delay value of the wafer and the preset delay value are compared to determine whether the wafer passes the efficiency monitoring program according to the comparison result. The wafer is distinguished according to the first current detecting program of the first operating frequency and the passage of the efficiency monitoring program.

In an embodiment of the invention, the step of operating the wafer at the first operating frequency to obtain the first operating current of the wafer in accordance with the first operating frequency comprises the following steps. The wafer is subjected to a first voltage in accordance with the first operating frequency. The wafer is measured to obtain a first operating current of the wafer based on the measurement result.

In an embodiment of the invention, the first operating current of the comparison wafer is The first threshold current corresponding to the first operating frequency, and the first current detecting procedure for determining whether the wafer passes the first operating frequency according to the comparison result includes the following steps. When the first operating current of the wafer is less than the first threshold current, the first current detecting procedure of the first operating frequency is judged by the wafer. In other words, when the first operating current of the wafer is greater than the first threshold current, it is determined that the wafer does not pass the first current detecting procedure of the first operating frequency.

In an embodiment of the invention, the process monitoring unit includes a first counter, a second counter, an oscillator, and a delay circuit. The first counter is coupled to the second counter and the oscillator, and the oscillator is coupled to the delay. Circuit.

In an embodiment of the invention, when the wafer passes the first current detecting program of the first operating frequency, the process of monitoring the current delay value of each wafer by the process monitoring unit in each wafer includes the following steps. The oscillation clock of the oscillator is input to the first counter and the delay circuit, and the delay circuit generates a delayed output signal according to the oscillation clock. The input clock is input to the second counter, and the second counter resets the signal according to the input clock count. The first counter generates a current delay value of each wafer according to the reset signal, the oscillation clock, and the input clock.

In an embodiment of the invention, comparing the current delay value with the preset delay value to determine whether the wafer passes the efficiency monitoring program includes the following steps. When the current delay value is less than the preset delay value, the wafer is judged to pass the efficiency monitoring program. In other words, when the current delay value is greater than the preset delay value, it is judged that the wafer has not passed the efficiency monitoring program.

In an embodiment of the invention, the first current detecting program according to the first operating frequency and the pass or fail of the efficiency monitoring program distinguish the wafers including the following step. When the wafer passes the first current detection procedure of the first operating frequency and passes the efficiency monitoring program, the wafer is divided into a first category that conforms to the first operating frequency. When the wafer passes the first current detection routine of the first operating frequency but does not pass the efficiency monitoring procedure, the wafer is divided into a second category that conforms to the second operating frequency.

In an embodiment of the invention, after comparing the first threshold current corresponding to the first operating frequency of the wafer with the first operating frequency to determine whether the wafer passes the first current detecting procedure of the first operating frequency, the method further includes the following steps. . When the wafer does not pass the first current detection routine of the first operating frequency, the wafer is subjected to a second voltage in accordance with the second operating frequency. The wafer is measured to obtain a second operating current of the wafer based on the measurement result. Comparing the second operating current of the wafer with the second threshold current corresponding to the second operating frequency to determine whether the wafer passes the second current detecting procedure of the second operating frequency.

In an embodiment of the invention, after the second threshold current corresponding to the second operating frequency of the comparison wafer and the second operating frequency is determined to determine whether the wafer passes the second current detecting procedure of the second operating frequency, the method further includes the following steps. . When the wafer passes the second current detection procedure of the second operating frequency, the wafer is divided into a second category that conforms to the second operating frequency.

In an embodiment of the invention, after the second threshold current corresponding to the second operating frequency of the comparison wafer and the second operating frequency is determined to determine whether the wafer passes the second current detecting procedure of the second operating frequency, the method further includes the following steps. . When the wafer does not pass the second current detection procedure of the second operating frequency, the wafer is divided into a third category that does not conform to the first operating frequency and the second operating frequency.

Based on the above, in the wafer probe testing stage, the operating frequency is applied to the wafer on the wafer to determine whether the wafer passes the current detecting program, and the process monitoring unit in each wafer determines whether the wafer passes the efficiency monitoring program. And the wafer is distinguished by the current detection program and the passage of the efficiency monitoring program. This allows wafer manufacturers to differentiate wafers that meet the highest operating frequencies during the wafer probe test phase to save on the cost of the process.

The above described features and advantages of the invention will be apparent from the following description.

S110~S190‧‧‧Steps

300‧‧‧Process Monitoring Unit

310, 330‧‧‧ counter

350‧‧‧Oscillator

370‧‧‧Delay circuit

371, 373‧‧‧D positive and negative

S410~S470‧‧‧ Process

OSC_CLK‧‧‧ oscillation clock

DOS‧‧‧ delayed output signal

CLK‧‧‧ input clock

RST_N‧‧‧Reset signal

SEL, SE‧‧‧ selection signal

EN‧‧‧Enable signal

STOP‧‧‧ stop signal

D‧‧‧Data input

Q‧‧‧ data output

SN, RN‧‧‧D flip-flops

COUNT‧‧‧ count value

1 is a flow chart illustrating a method of discriminating a wafer in accordance with an embodiment of the invention.

2 is a simulation diagram of the operating current versus delay time for the threshold current corresponding to the measured plurality of wafers.

FIG. 3 is a circuit diagram of a process monitoring unit according to an embodiment of the invention.

FIG. 4 is a schematic flow chart of a distinguishing method according to an embodiment of the invention.

FIG. 5 is a schematic diagram of a zone partition block corresponding to an operating current versus delay time according to an embodiment of the invention.

The wafer testing process passes through three test processes, including wafer probe testing, final testing, and system board testing. In the wafer probe test process, wafer manufacturers test wafers that have not been diced (eg, memory built-in self test (MBIST), design for testability; DFT), analog/digital test, etc., and distinguishes the first category of wafers that meet the first operating frequency (eg, 600 HMz) based on the test results. In the final test process, the wafer manufacturer will test the packaged wafer (for example, memory built-in self-test, testability design, analog/digital test, etc.), and test whether the packaged wafer meets the requirements. A functional test of two operating frequencies (eg, 900 MHz) to distinguish wafers that are less than or equal to the second operating frequency (eg, 800 MHz or 900 MHz). Then, in the system board test process, the engineer places the chip on a circuit board, a developed board, or a mother board to verify the operating frequency of the wafer.

According to the above description, the wafer manufacturer usually has to go through the final test or even the system board test to complete the process of wafer differentiation. Therefore, the chip manufacturer must consume the test cost of the final test and the system board test. Therefore, in the wafer probe (CP) test stage, the wafer on the wafer can be tested according to different operating frequencies, thereby distinguishing the advantages and disadvantages of the wafer on the wafer, thereby accelerating the screening of the wafer and Save on the cost of distinguishing processes. This method of obtaining the operating power of the wafer on the wafer according to the operating frequency (for example, 600 MHz, 800 MHz, etc.) The flow determines whether the operating current of the wafer passes the current detecting program, determines whether the wafer passes the efficiency monitoring program through the process monitor unit in each wafer, and distinguishes the wafer according to the detection result of the current detecting program and the efficiency monitoring program. In this way, the chip manufacturer can eliminate the cost of the differentiation process of the final test (FT) or system on board (SB) test phase.

1 is a flow chart illustrating a method of discriminating a wafer in accordance with an embodiment of the invention. Referring to FIG. 1, each process of the method for distinguishing may be adjusted according to an implementation situation, and is not limited thereto.

In step S110, the wafer is operated at a first operating frequency to obtain a first operating current of the wafer in accordance with the first operating frequency, wherein the wafer is on the undivided wafer. Specifically, the wafer is subjected to a first voltage in accordance with the first operating frequency. The wafer is measured to obtain a first operating current of the wafer based on the measurement result. For example, a fixed voltage of 1.2 volts is applied to each wafer on the wafer in accordance with the operating frequency of 800 HMz, and the current generated by the measurement of the wafer at a voltage of 1.2 volts is 0.12 amps.

In step S130, the first threshold current corresponding to the first operating frequency of the wafer is compared to determine whether the wafer passes the first current detecting procedure of the first operating frequency according to the first threshold current. Specifically, when the first operating current of the wafer is less than the first threshold current, the first current detecting procedure of the wafer passing the first operating frequency is determined. In other words, when the first operating current of the wafer is greater than the first threshold current, it is determined that the wafer does not pass the first current detecting procedure of the first operating frequency. For example, when the first threshold current corresponding to the operating frequency of 800 HMz is 0.18 amps, if the first operating current measured by the wafer is 0.12 amps, the wafer is judged to pass the first A current detecting procedure, and if the first operating current measured by the wafer is 0.24 amps, it is judged that the wafer does not pass the first current detecting procedure.

It should be noted that, refer to Table (1), which applies a 1.05 volt burner to two integrated circuits (IC) IC1 and IC2 (for example, a central processing unit (CPU) of 800 MHz/DDR1333). An example of a burn-in or test result of a reliability test. The two integrated circuits IC1 and IC2 have been tested since 17:40. The operating current and surface temperature of IC2 are measured at each measuring time (for example, 17:50, 18:00 and 18:10). The grading is higher than the operating current and surface temperature of IC1. Assuming that the highest heat-resistant temperature of IC1 and IC2 is 111 degrees, the test machine of the device IC2 will be hanged at 18:00. As can be seen from the above description, when the operating current of the IC is higher, the surface temperature may rise and the machine may be down. Therefore, the present invention determines that the wafer whose operating current exceeds the threshold current is a failed current detecting routine.

In addition, the present invention selects the first threshold that meets the first operating frequency standard. Flow methods include tool simulation, measurement statistics, and system verification. In the tool simulation method, the working current of the wafer is calculated by using a tool simulation, and the operating current is multiplied by a multiple (about 3) to estimate the threshold current. In the measurement statistics method, the operating current of a plurality of wafers is counted, and the threshold current is multiplied by a standard deviation (about 1.5) of the operating current of two times of multiple wafers to estimate the threshold current. In the system verification method, a plurality of wafers (for example, three thousand) are applied with a fixed voltage (for example, 1 volt), and the operating current and the delay time of each wafer reacting to the fixed voltage are measured, and the measurement result is passed. The threshold current is analyzed, and the delay time of each wafer will be described later. For example, FIG. 2 is a simulation diagram of the operating current versus delay time of the threshold current corresponding to the measured plurality of wafers. Referring to FIG. 2, the working current versus delay time of the plurality of wafers measured in the cloud-like range in FIG. 2, and the threshold current calculated by the tool simulation method, the measurement statistical method, and the system verification method are respectively 0.170. Amperes, 0.190 amps, and 0.180 A amps.

In another aspect, the method for measuring the operating current of the measuring wafer of the present invention comprises a memory built-in self test (MBIST), a double data rate (DDR), and a testability design (DFT), wherein the present invention The logical self-test method of the testability design is used as a better measurement method so that the measured difference in operating current is smaller and more accurate, and can cover more logic gates (for example, 99% of logic gates).

Returning to the flow of FIG. 1, in step S150, when the wafer passes the first current detecting program of the first operating frequency, the current delay value of each wafer is judged by the process monitoring unit in each wafer. In this embodiment, each of the wafers in the wafer has At least one process monitoring unit, for example, four process monitoring units mounted around the wafer. The process monitoring unit of the present invention can determine the process monitoring benefit (eg, process value (PM value)) or current delay value of each wafer in addition to testing the wafer to know the overall benefit of the wafer (eg, Propagation delay).

FIG. 3 is a circuit diagram of a process monitoring unit according to an embodiment of the invention. Referring to FIG. 3, the process monitoring unit 300 includes a counter 310, a counter 330, an oscillator 350, and a delay circuit 370. The counter 310 is coupled to the counter 330 and the oscillator 350, and the oscillator 350 is coupled to the delay circuit 370 (by D The flip-flops are composed of 371 and 373). Counter 310 is, for example, a 15-bit digital logic counter, counter 330 is, for example, a 10-bit digital logic counter, and oscillator 350 is, for example, a ring oscillator.

In the present embodiment, the oscillation clock OSC_CLK of the oscillator 350 is input to the counter 310 and the delay circuit 370, and the delay circuit 370 generates the delayed output signal DOS in accordance with the oscillation clock OSC_CLK. The input clock CLK is input to the counter 330, and the counter 330 counts the reset signal RST_N according to the input clock CLK. The counter 310 generates a current delay value of each wafer according to the reset signal RST_N, the oscillation clock OSC_CLK, and the input clock CLK. For example, an external input clock CLK (eg, 27 MHz) is input to the counter 330, and the oscillator 350 provides an internal oscillation clock OSC_CLK to the counter 310. By calculating the difference between the count values of the counters 310 and 330, the internal oscillation clock OSC_CLK can be derived, and the delay output signal DOS is generated by the delay circuit 370 to generate the delayed output signal DOS. The current delay value. It should be noted that, in other embodiments, the process monitoring unit may have different types of counters, delay circuits, and oscillators, which may be changed by a person skilled in the art according to design requirements.

Returning to the flow of FIG. 1, in step S170, the current delay value of the wafer and the preset delay value are compared to determine whether the wafer passes the efficiency monitoring program according to the comparison result. Specifically, when the current delay value is less than the preset delay value, the wafer is judged to pass the efficiency monitoring program. In other words, when the current delay value is greater than the preset delay value, it is judged that the wafer has not passed the efficiency monitoring program. For example, when the preset delay value is 35 nanoseconds (ns), if the current delay value measured by the process monitoring unit is 30 ns, the wafer is judged to pass the efficiency monitoring program, and if the process monitoring unit measures the current The delay value is 36 ns, and it is judged that the wafer does not pass the efficiency monitoring program.

It should be noted that the current delay value in this embodiment may represent the performance of the associated wafer, and the performance of the wafer is worse when the current delay value is larger. Please refer to Table (2), which is the burn-in or reliability of three integrated circuits (IC) IC3, IC4, IC5 (for example, the central processing unit (CPU) of 800MHz/DDR1333). An example of the test results of the test. IC3's current delay value is 20ns, and the reliability test can be passed by applying 1.2 volts and 1.05 volts to IC3. The current delay value of IC4 is 30 ns, and the application of 1.05 volts to IC4 fails the reliability test. IC5's current delay value is 40ns, and the application of 1.2 volts and 1.05 volts to IC5 failed the reliability test. As can be seen from the above description, when the current delay value (or the process monitoring value PM value) is too large, the wafer cannot pass the reliability test. Therefore, the present invention determines that the wafer whose current delay value exceeds the preset delay value is not to pass the preset delay value.

In addition, the method for selecting a preset delay value according to the present invention may perform statistics by measuring a current delay value of a process monitoring unit on a plurality of wafers by referring to a system verification method for selecting a first threshold current, and may also be accompanied by a burn-in test or The reliability test determines the size of the preset delay value. For example, a chip with a current delay value of 20 ns and 25 ns can be tested by applying a voltage of 1.2 volts and 1.05 volts. A wafer with a current delay value of 30 ns can only be tested by applying a 1.2 volt voltage to the burner. Chips with current delay values of 40 ns and 45 ns are not tested by applying a voltage of 1.2 volts and 1.05 volts. Engineers can determine the preset delay value based on the test results.

In step S190, the wafer is distinguished according to the first current detecting program of the first operating frequency and the passage of the efficiency monitoring program. Specifically, when the wafer passes the first current detection program of the first operating frequency and passes the efficiency monitoring program, the wafer is divided into a first category that conforms to the first operating frequency. When the wafer passes the first current detection routine of the first operating frequency but does not pass the efficiency monitoring procedure, the wafer is divided into a second category that conforms to the second operating frequency. For example, it will pass 800MHz The chips of the current detection program and the efficiency monitoring program are classified into the first category conforming to 800 MHz, and the wafers not passing the efficiency monitoring program are classified into the second category conforming to 600 MHz.

In this way, the wafer manufacturer can distinguish wafers that meet different operating frequencies during the wafer probe testing phase, and only need to verify the differentiated categories in the final test (FT) process, saving the final test. And the test flow of the system on board (SB) test.

FIG. 4 is a schematic flow chart of a distinguishing method according to an embodiment of the invention. Referring to FIG. 4, the detailed steps of the processes S410, S420, S430, and S440 refer to the description of steps S110 to S190 in FIG. 2, and details are not described herein again. The difference from FIG. 2 is that the present invention can continue to classify these wafers when a portion of the wafers fail the first current sensing procedure of the first operating frequency. In the process S460, the wafer is applied with a second voltage according to the second operating frequency. The wafer is measured to obtain a second operating current of the wafer based on the measurement results. Comparing the second operating current of the wafer with the second threshold current corresponding to the second operating frequency to determine whether the wafer passes the second current detecting procedure of the second operating frequency.

For example, a fixed voltage of 1 volt is applied to each wafer on the wafer in accordance with the operating frequency of 600 HMz, and the current generated by the measurement of the wafer at a voltage of 1 volt is 0.21 amps. When the second threshold current corresponding to the operating frequency of 600 HMz is 0.23 amps, if the second operating current measured by the wafer is 0.21 ampere, the wafer is judged to pass the second current detecting procedure, and if the wafer is measured, When the operating current is 0.26 amps, it is judged that the wafer does not pass the second current detecting procedure.

When the wafer passes the second current detecting procedure of the second operating frequency, the wafer is divided into a second category that conforms to the second operating frequency (flow S440). When the wafer does not pass the second current detecting procedure of the second operating frequency, the wafer is divided into a third category that does not conform to the first operating frequency and the second operating frequency (flow S470). For example, when the wafer passes the current detection procedure of 600 HMz, the wafer is classified as a second category that conforms to 600 HMz. Instead, the wafer is classified as a third category.

For example, FIG. 5 is a schematic diagram of a zone partition block corresponding to an operating current versus delay time simulation diagram according to an embodiment of the invention. Referring to FIG. 5, the cloud-like range is the measured data of the operating current versus delay time of the plurality of wafers, and the first threshold current is 0.18 amps, the second threshold current is 0.23 amps, and the preset delay of 800 MHz is met. The value is 82ns. A wafer whose operating current is less than the first threshold and whose current delay value is less than the preset delay value may be classified as 800 MHz or 600 MHz, and the wafer whose operating current is less than the first threshold and whose current delay value is greater than the preset delay value may be classified as 600 MHz. A wafer having an operating current between the first threshold and the second threshold may be classified as conforming to 600 MHz, and a wafer having an operating current greater than the second threshold may be classified into the third category.

It should be noted that, in other embodiments, the wafer belonging to the second category or the third category may further change the preset delay by using steps similar to steps S150 to S1710 in FIG. 2 and the flow S420 in FIG. The values continue to be categorized for wafers belonging to the second or third category. In this way, the wafer manufacturer can distinguish at least three types of wafers in the wafer probing test flow.

In summary, the embodiment of the present invention can be used during the wafer probe test phase. The wafer on the wafer applies an operating frequency to determine whether the wafer passes the current detecting program, determines whether the wafer passes the efficiency monitoring program through the process monitoring unit in each wafer, and distinguishes the wafer by the current detecting program and the pass or fail of the efficiency monitoring program. This allows wafer manufacturers to differentiate wafers that meet the highest operating frequencies during the wafer probe test phase to save on the cost of the process.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

S110~S190‧‧‧Steps

Claims (10)

A method for distinguishing a wafer, the method comprising: operating at least one wafer at a first operating frequency to obtain a first operating current of the at least one wafer, wherein the at least one wafer is on an undivided wafer; a first threshold current corresponding to the first operating frequency of the at least one wafer to determine whether the at least one wafer passes a first current detecting procedure of the first operating frequency; when the at least one wafer passes The first current detecting program of the first operating frequency passes through a process monitoring unit of each of the at least one wafer to determine a current delay value of each of the at least one wafer; and compares a current delay value of the at least one wafer with a pre- Setting a delay value to determine whether the at least one wafer passes an efficiency monitoring program; and distinguishing the at least one wafer according to the first current detecting program of the first operating frequency and the pass or fail of the efficiency monitoring program. The method of distinguishing the at least one wafer from the first operating frequency to obtain the first operating current of the at least one wafer, according to the method of claim 1, wherein the step of: Applying a first voltage to a wafer; and measuring the at least one wafer to obtain a first operating current of the at least one wafer. The distinguishing method of claim 1, wherein comparing the first operating current of the at least one wafer with the first threshold current corresponding to the first operating frequency to determine whether the at least one wafer passes the first operation The first current of the frequency The step of detecting the program includes: determining, when the first operating current of the at least one wafer is less than the first threshold current, the first current detecting procedure of the at least one wafer passing the first operating frequency; and when the at least one wafer is When the first operating current is greater than the first threshold current, determining that the at least one wafer does not pass the first current detecting procedure of the first operating frequency. The method of distinguishing the method of claim 1, wherein the process monitoring unit comprises: a first counter, a second counter, an oscillator, and a delay circuit, the first counter is coupled to the second counter and the An oscillator, and the oscillator is coupled to the delay circuit. The distinguishing method of claim 4, wherein when the at least one wafer passes the first current detecting program of the first operating frequency, the process monitoring unit in each of the at least one wafer is used to determine each The step of at least one current delay value of the chip includes: inputting an oscillation clock of the oscillator to the first counter and the delay circuit, and the delay circuit generates a delayed output signal according to the oscillation clock; The pulse is input to the second counter, and the second counter counts a reset signal according to the input clock; and the first counter generates each of the at least the reset signal, the oscillation clock and the input clock. The current delay value of a wafer. The method of distinguishing as described in claim 1 of the patent application, wherein the current And the step of determining the at least one wafer to pass the efficiency monitoring program includes: determining that the at least one wafer passes the efficiency when the current delay value of the at least one wafer is less than the preset delay value And monitoring the program; and when the current delay value of the at least one wafer is greater than the preset delay value, determining that the at least one wafer does not pass the efficiency monitoring program. The distinguishing method according to claim 1, wherein the step of distinguishing the at least one wafer according to the first current detecting program of the first operating frequency and the pass or fail of the efficiency monitoring program comprises: when the at least one When the wafer passes the first current detecting program of the first operating frequency and passes the efficiency monitoring program, distinguishing the at least one wafer into a first category that conforms to the first operating frequency; and when the at least one wafer passes the first When the first current detecting program of the operating frequency does not pass the efficiency monitoring program, the at least one wafer is distinguished as a second category that conforms to a second operating frequency. The distinguishing method of claim 1, wherein comparing the first operating current of the at least one wafer with the first threshold current corresponding to the first operating frequency to determine whether the at least one wafer passes the first operation After the step of the first current detecting process of the frequency, the method further includes: when the at least one wafer fails the first current detecting process of the first operating frequency, applying the at least one wafer according to a second operating frequency a second voltage; measuring the at least one wafer to obtain a second operating current of the at least one wafer; And comparing a second operating current of the at least one wafer with a second threshold current corresponding to the second operating frequency to determine whether the at least one wafer passes a second current detecting procedure of the second operating frequency. The distinguishing method of claim 8, wherein comparing the second operating current of the at least one wafer with the second threshold current corresponding to the second operating frequency to determine whether the at least one wafer passes the second operation After the step of the second current detecting process of the frequency, the method further includes: when the at least one wafer passes the second current detecting process of the second operating frequency, distinguishing the at least one chip as a first one that meets the second operating frequency Two categories. The distinguishing method of claim 8, wherein comparing the second operating current of the at least one wafer with the second threshold current corresponding to the second operating frequency to determine whether the at least one wafer passes the second operation After the step of the second current detecting process of the frequency, the method further includes: when the at least one wafer fails the second current detecting process of the second operating frequency, distinguishing the at least one chip from not meeting the first operating frequency and A third category of the second operating frequency.