TW201524132A - Arrangement and method for converting a photocurrent - Google Patents

Abstract

The invention, which relates to an arrangement and method for converting a photocurrent, is based on the object of specifying a solution that is used to achieve a reduction in the area requirement for the arrangement by eliminating operational amplifier and integrator capacitance, and also a reduction in the necessary operating current. This object is achieved for the arrangement in that the photodiode is connected to a constant current source and to an input of a comparator via a second switch. This object is achieved for the method in that the integrator capacitance used is a junction capacitance of a photodiode, in that this junction capacitance is discharged by means of a light-dependent photocurrent until a prescribed voltage has been reached and that subsequently a reference current and a determined time are used to charge the junction capacitance in order to ascertain the digital representation.

Description

Device and method for converting photocurrent

The present invention relates to a device for converting photocurrent having an inlet connected to a photodiode and an outlet connected to a counter.

The present invention also relates to a method of converting photocurrent by integrating the integrated capacitance through photocurrent control and then comparing to form a digital representation of the photocurrent.

For example, when processing an optical signal for controlling an instrument or transmitting data by an optical signal, it is necessary to convert the optical signal into a digital electrical signal. To achieve this, an analog-to-digital converter is used, in which the analog-to-digital converter converts the input voltage or input current into corresponding digital values.

The analog-digital converter voltage input operating according to the principle of charge balance is the same, that is, the integrator is used to integrate the signal to be converted, and then the integrated output voltage is evaluated by a comparator and a counter according to a reference voltage and a time base, wherein the integrator It consists of an operational amplifier OPV, a resistor and an integrating capacitor.

Similarly, an integrator can be used to convert the input current into a suitable form, that is to say into a sequence of digital output signals.

A disadvantage of the above known devices is that the operational amplifier and the integrating capacitor occupy a large area in the precision integrator, and in order to achieve the required slew rate, the amplifier must have a large frequency bandwidth, so the correspondingly needs a large amount. Working current.

An advantage of the above arrangement is that the selection of the integrating capacitor can be adjusted, and/or affect the modulation range, and the reverse voltage across the sensor (e.g., the photodiode integrated on the wafer) remains fixed.

SUMMARY OF THE INVENTION The object of the present invention is to provide a device for converting photocurrent in order to reduce the area occupied by the operational amplifier and the integrating capacitor in the device and to reduce the required operating current.

To achieve the above object, the apparatus of the present invention is characterized in that the photodiode constituting the integral capacitance required for the integration process is connected to a constant power source via a second switch and directly connected to the inlet of a comparator.

In particular, the device of the present invention utilizes the capacitance inherent in the photodiode barrier layer and discharges it via the photocurrent determined by the light. Next, after the connected voltage detection stage reaches a specific detection voltage, the capacitance of the photodiode is recharged via a reference power supply for a specific period of time (eg, half a pulse repetition period).

Since there is one reverse operating amplifier circuit that is less than the standard integrator of the prior art, the above process is reversed, that is, integrated by the discharge of the barrier capacitor controlled by the photocurrent of the photodiode. Since the capacitance of the photodiode (sensor) is also an integral capacitor, an integrator-operating amplifier is not required.

Contrary to the general solution using an operational amplifier and a separate integrating capacitor, in the present invention, the bias deviation of the photodiode cannot be kept constant because the barrier capacitance is also carried in the form of a signal voltage. Points data.

Therefore, the precision of the system is determined by two factors, one is the state of starting integration, that is, the initial charging state of the photodiode capacitor, and the other factor is the voltage characteristic of the barrier capacitance of the photodiode. In the case where the degree of modulation is relatively small and the reverse voltage is large enough, the barrier capacitance has a sufficiently large linearity.

According to one embodiment of the invention, a D-type flip-flop (D-Flip-Flop) and an anti-gate are provided between the outlet of the comparator and the outlet for which the device provides a signal to the connected counter.

A comparator is provided behind the comparator and a selection gate that forms a particular count pulse for the latter counter.

According to another embodiment of the present invention, a delay circuit is provided between the clock inlet of the D-type flip-flop and the entrance of the anti-gate to delay the clock edge of the adjacent clock signal.

The transit time from the clock pulse inlet to the outlet through the D-type flip-flop can be compensated by the delay of the clock signal. This makes it possible to accurately use a half pulse repetition period as the time base for the balancing process.

In order to achieve the object of the present invention, the present invention also provides a method for converting photocurrent by using a barrier capacitance of a photodiode (as a necessary sensor) for generating photocurrent as an integrating capacitor, wherein the barrier capacitance is The photocurrent determined by the light of the sensor is discharged until the specified voltage is reached, and then the barrier capacitance is charged with a reference current for a specific time to obtain a digital representation, wherein the digital representation is transmitted through the D-type. The number of clock phases at the high exit of the counter exit is indicated.

The present invention realizes a so-called charge balancing method in which a barrier capacitance of a photodiode is used as an integrating capacitor, and the value of the input current can be obtained without using an operational amplifier to be used in the prior art.

One embodiment of the underlying invention sets a working point for a comparator that monitors a specified voltage before discharging the barrier capacitor.

Set the operating point of the comparator to determine the starting value of the first integration. This also tracks the integrated voltage to avoid reference current spikes.

Figure 1 shows a prior art device 1 for converting a photo-electric Ip into a digital output value. The photocurrent 7 at the inlet of the device 1 is integrated by an integrator 2. The integrator 2 is composed of an operational amplifier 3 and its integrated integrating capacitor 4. The comparator 5, consisting of the switching points of the data entry of the flip-flop, evaluates the output signal of the integrator 2, and then the counter 6 forms a value representative of the digits of the photocurrent 7. This value is the output value of device 1.

The method of the present invention can be divided into three single steps as described below.

The first step is to pre-adjust the integrated voltage to the comparator's parameters, which is the start control signal 16 "autozero". In this step, the first switch 12 and the third switch 14 in Fig. 2 are turned on. The second switch 13 remains in the off state.

The operating point of the comparator 22 is charged to the barrier capacitance of the photodiode 15 to complete the pre-adjustment of the initial value of the integration.

The reference voltage of comparator 22 is formed by the threshold voltage of first transistor 26. Since comparator 22 is already at the switching point, the first so-called "charge balancing process" will be performed directly and a result will be produced at the exit. Without having to overcome the center of the score. This can be corrected, wherein the pre-adjustment of the counter (not shown in Figure 2) connected to the circuit in Figure 2 is performed at -1 during the first step.

The value flip-flop 23 remains in the reset state during the first step.

At the same time, the photodiode reverse voltage is charged to the drain interface of the reference power supply 25 via the turned-on third switch 14 and decoupling amplifier 24. This is done to avoid voltage transients at the beginning of the next phase of de-integration. The decoupling amplifier 24 operates in a quasi-static manner, so under the same system parameters, the decoupling amplifier 24 must meet the requirements in terms of frequency characteristics and precision far less than the requirements that the integrating amplifier must meet, so the decoupling amplifier 24 occupies The area and power consumption are much smaller than the integrating amplifier.

In the next second step, that is, in the so-called integration or measurement phase, the first switch 12 and the second switch 13 are turned off while the third switch 14 is turned "on". In this step, the voltage on the photodiode 15 is deflected until the critical value of the comparator 22 is reached.

Similarly, the barrier capacitance of the photodiode 15 begins at the previously set Autozero-charge state, and when the counter clock pulse 17 "CLK" is activated, the photocurrent 7 determined by the light is more or less rapidly discharged. This process continues until the switch point of comparator 22 is reached.

During integration, the voltage on the thermal termination of the reference power supply 25 is maintained at the latest integrated voltage value so that the power supply-drain can be smoothly switched at all times, that is, without affecting the current balance.

In the third step, that is, in the so-called "equilibrium phase", the first switch 12 and the third switch 14 are turned off while the second switch 13 is turned on. In this step, the charge of the integrating capacitor of the photodiode 15 is compensated. This process uses a reference current that is divided into so-called current packets with a certain duration of action.

During the high-clock pulse half cycle of the photocurrent 7 that continues to flow, re-charging of the barrier capacitance or integrating capacitance occurs. In order to compensate for the time error between the exit of the flip-flop 23 and the rising edge of the clock signal 17, the strobe of the gate 27 is delayed by the control of the delay circuit 28.

Passing the pulse duty factor of the clock signal 17 (preferably adjusted to a ratio of 1:1) and the number of clock pulses measured during the discharge phase, in the case where the number of clock pulses is 2 ⁿ , in the counter The count pulse to be counted by the outlet 18 (not shown) produces a ratio proportional to the photocurrent 7 of the photodiode 15. This is equivalent to the analog photocurrent 7 being finally converted to a digital output value. The number of pulses at the exit 18"out" can be calculated using the following formula:

Where: Z represents the number of pulses at the exit "out" N represents the total clock pulse I _ref represents the reference current I _ph represents the photocurrent

The feedback-free action of the anti-gate 27 connected to the integral signal via the D-type flip-flop 29 is determined by the integrated potential. It is therefore important to distinguish the digital supply voltage from the analog supply voltage.

The comparator shown in Fig. 3 is limited to its peak current by the depleted power sources 30 and 31 which constitute the load of the amplifying transistors 26 and 32. This has great advantages when the switching current is applied to a longitudinal regulator in the system. At the same time, the total power consumption and its noise spectrum can be optimized.

The reference voltage of comparator 22 is the threshold voltage of the first n-channel transistor 26. Therefore, there is no need to provide other reference voltages, and of course there is no need to stabilize other reference voltages. The gate of the transistor 26 is the inlet of the comparator 22 of the present invention and is designated by the symbol "in" in Figure 3. The outlet of the comparator 22 is indicated by the component symbol "q", and this outlet is also an outlet of the value flip-flop 23.

From the perspective of all transients in a digital circuit, another positive effect of decoupling the analog operating voltage from the digital operating voltage is to avoid variations in the supply voltage of the analog circuit.

The analog portion 19 of the circuit is powered by a first operating voltage 8 vdd1 and the digital portion 20 is powered by a second operating voltage 9 vdd2.

The analog portion 19 and the digital portion 20 of the comparator circuit can be connected to the same ground 21 GND.

The switching signals of the second switch 13 and the third switch 14 measured from the exit of the opposite gate 27 are inverted by the inverter 33 of the second switch 13, since these switches are always turned on in reverse with each other.

1‧‧‧ Analog-Digital Converter ADC
2‧‧‧Integrator
3‧‧‧Operational amplifier OPV
4‧‧‧Integral capacitor C
5‧‧‧Comparative instrument
6‧‧‧Counter
7‧‧‧Input current Ip
8‧‧‧First working voltage vdd1
9‧‧‧second working voltage vdd2
10‧‧‧clock pulse (clk)
11‧‧‧Reset signal (autozero)
12‧‧‧ first switch
13‧‧‧Second switch
14‧‧‧The third switch
15‧‧‧Photoelectric diode
16‧‧‧Control signal "autozero"
17‧‧‧Counter clock pulse
18‧‧‧Export "out"
19‧‧‧Digital circuit part
20‧‧‧Digital Circuit Section
21‧‧‧ Grounding "GND"
22‧‧‧Comparative instrument of the invention
23‧‧‧ Valued flip-flops
24‧‧‧Decoupling amplifier
25‧‧‧Reference power supply
26‧‧‧N type metal oxide semiconductor (NMOS)
27‧‧‧Anti-gate (NAND)
28‧‧‧Delay circuit
29‧‧‧D type flip-flop
30‧‧‧The first depleted power supply
31‧‧‧Second depleted power supply
32‧‧‧Second transistor
33‧‧‧Inverter

The contents of the present invention will be further described below in conjunction with the drawings and an embodiment. among them:

Figure 1: Circuit configuration of a prior art analog-to-digital converter for converting optoelectronic Ip.

Fig. 2 is a view showing an embodiment of a circuit configuration for converting photoelectric Ip of the present invention.

Figure 3: Portion of the comparator circuit in the circuit configuration as in Figure 2.

8‧‧‧First working voltage (vdd1)

9‧‧‧second working voltage (vdd2)

10‧‧‧clock pulse (clk)

11‧‧‧Reset signal (autozero)

12‧‧‧ first switch

13‧‧‧Second switch

14‧‧‧The third switch

15‧‧‧Photoelectric diode

16‧‧‧Control signal "autozero"

17‧‧‧Counter clock pulse

18‧‧‧Export "out"

19‧‧‧Digital circuit part

20‧‧‧Digital Circuit Section

21‧‧‧ Grounding "GND"

22‧‧‧Comparative instrument of the invention

23‧‧‧ Valued flip-flops

24‧‧‧Decoupling amplifier

25‧‧‧Reference power supply

26‧‧‧N type metal oxide semiconductor (NMOS)

27‧‧‧Anti-gate (NAND)

28‧‧‧Delay circuit

29‧‧‧D type flip-flop

30‧‧‧The first depleted power supply

31‧‧‧Second depleted power supply

32‧‧‧Second transistor

33‧‧‧Inverter

Claims (5)

The device for converting photocurrent has an inlet connected to the photodiode and an outlet connected to the counter, wherein the photodiode constituting the integral capacitance required for the integration process is via the second switch and A constant power connection and direct connection to the inlet of a comparator. The device of claim 1 is characterized in that: a D-type flip-flop and a reverse gate are provided between the outlet and the outlet of the comparator. A device as claimed in claim 1 or 2, characterized in that: a delay circuit is provided between the clock pulse inlet of the D-type flip-flop and the entrance of the reverse gate, the function of which is to delay the adjacent clock The clock edge of the signal. A method of converting photocurrent by integrating an integrating capacitor through photocurrent control and then comparing to form a digital representation of the photocurrent, characterized by: using a barrier capacitance of a photodiode that produces photocurrent As the integral capacitor, the barrier layer capacitor discharges through the photocurrent determined by the light until the specified voltage is reached, and then the barrier capacitor is charged with a reference current for a specific time to obtain a digital representation. The method of claim 4, characterized in that before the discharge of the barrier capacitor, an operating point is set for the comparator that monitors the specified voltage.