TW201513229A - Method of manufacturing junction barrier schottky diode and structure thereof - Google Patents

Abstract

A method of manufacturing a junction barrier schottky (JBS) diode is provided. An epitaxial layer and a patterned photoresist layer are formed on a semiconductor substrate in order. Using the patterned photoresist layer as a mask to perform an ion implanting process on the epitaxial layer which defines an active region and a terminative region, so as to form a plurality of ion implantation areas in the active region and the terminative region. The upper surface of the epitaxial layer is a planar or has a plurality of trenches. A dielectric layer is formed to cover the terminative region and a schottky metal is formed to cover the active region of the epitaxial layer. Then, a bonding metal layer is used to connect the schottky metal. A structure of the (JBS) diode is also provided. This manufacturing method may reduce the manufacture cost and the JBS diode has higher performance.

Description

Manufacturing method and structure of junction barrier Schottky diode

The present invention relates to a method of fabricating a diode, and more particularly to a method of fabricating a junction barrier Schottky (JBS) diode and a structure thereof.

Generally, the Schottky diode 10 is mainly formed on a highly doped N+ germanium substrate 12 to form a lightly doped N-germanium epitaxial layer 14, as shown in FIG. 1, and in the N-矽 epitaxial layer 14 A dopant is implanted on the surface to form a P+ diffusion gate 16, and a Schottky metal layer 18 is formed on the surface of the P+ diffusion gate 16 and the N-矽 epitaxial layer 14 between the P+ diffusion gates 16. .

Wherein, the P+ diffusion gate 16 is formed by deep implantation of the dopant into the N-矽 epitaxial layer 14 by a high-temperature diffusion process so that the P+ diffusion gate 16 is opposite to the N when the Schottky diode 10 is reverse-conducted. - The pinning region of the PN junction formed by the germanium epitaxial layer 14 has a pinch-off function, thereby achieving the effect of reducing the surface electric field of the Schottky diode 10.

However, in the high-temperature diffusion process, in addition to diffusing downward (longitudinal) from the surface of the N-矽 epitaxial layer 14, the dopant also produces lateral diffusion, and the width of such lateral diffusion will cause the current to be effective. The conduction width w is reduced to reduce the expected forward conduction function of the Schottky diode 10. Therefore, on the premise of achieving the same forward voltage, the size of the Schottky diode 10 is increased in order to obtain a sufficient current conduction width w. However, such a design that increases the component size of the Schottky diode 10 does not conform to the design concept that today's electronic components tend to be miniaturized.

In order to solve the above problems, an object of the present invention is to provide a method for fabricating a junction barrier Schottky diode in which ion implantation can be shortened by ion implantation of an epitaxial semiconductor layer simultaneously in an active region and a termination region. The process steps of the barrier Schottky diode to reduce production costs.

One of the objects of the present invention is to provide a method for fabricating a junction barrier Schottky diode, which utilizes an ion implantation step to implant dopants into the active region, which is different from the conventional high temperature diffusion process. The problem of the conventional conduction width reduction caused by lateral diffusion can be avoided, so that the junction barrier Schottky diode fabricated by the present invention has the advantage of higher efficiency.

In order to achieve the above object, a method for fabricating a junction barrier Schottky diode according to an embodiment of the present invention includes: forming an epitaxial semiconductor layer on a semiconductor substrate, the epitaxial semiconductor layer defining an active region and a termination region Forming a first dielectric layer and a first patterned photoresist layer on the epitaxial semiconductor layer, wherein the first patterned photoresist layer comprises a plurality of first openings to expose a portion of the surface of the first dielectric layer The first patterned photoresist layer is used as a mask, and the epitaxial semiconductor layer including the active region and the termination region is ion implanted to implant dopants in a part of the surface of the epitaxial semiconductor layer; a first patterned photoresist layer; a second dielectric layer and a second patterned photoresist layer are sequentially formed on the first dielectric layer, wherein the second patterned photoresist layer comprises at least one second opening corresponding to the active layer a second patterned photoresist layer is used as a mask to remove the second dielectric layer and the first dielectric layer exposed through the second opening to expose the active region; and removing the second patterned photoresist layer; Forming a Schottky barrier metal layer covering at least the active region; A bonding metal layer can be connected to at least the Schottky barrier metal layer.

A method for fabricating a junction barrier Schottky diode according to still another embodiment of the present invention includes: forming an epitaxial semiconductor layer on a semiconductor substrate, the epitaxial semiconductor layer defining an active region and a termination region; sequentially forming a first dielectric layer and a first patterned photoresist layer on the epitaxial semiconductor layer, wherein the first patterned photoresist layer comprises a plurality of first openings to expose a portion of the surface of the first dielectric layer; The patterned photoresist layer is a mask, and a portion of the first dielectric layer and a portion of the epitaxial semiconductor layer are removed to form a plurality of trenches in the epitaxial semiconductor layers of the active region and the termination region; and the first patterned photoresist layer is a mask, simultaneously implanting an epitaxial semiconductor layer including an active region and a termination region to implant a dopant in a portion of the surface of the epitaxial semiconductor layer; removing the first patterned photoresist layer; forming a first a dielectric layer covering the first dielectric layer and covering at least the wall surface and the bottom surface of the trench; forming a second patterned photoresist layer covering the second dielectric layer on the first dielectric layer and in the trench , The second patterned photoresist layer includes at least one second opening corresponding to the active region; the second patterned photoresist layer is used as a mask to remove the second dielectric layer and the first dielectric layer exposed by the second opening, And exposing the epitaxial semiconductor layer of the active region and the trenches on the active region; removing the second patterned photoresist layer; forming a Schottky barrier metal layer covering at least the epitaxial semiconductor layer of the active region and actively a wall and a bottom surface of the trench on the region; and forming a bonding metal layer to connect at least the Schottky barrier metal layer.

A method for fabricating a junction barrier Schottky diode according to still another embodiment of the present invention includes: forming an epitaxial semiconductor layer on a semiconductor substrate, the epitaxial semiconductor layer defining an active region and a termination region; The photoresist layer is a mask, and the epitaxial semiconductor layer including the active region and the termination region is ion implanted to form an ion implantation region in a part of the surface of the epitaxial semiconductor layer; forming a dielectric layer covering the termination region The epitaxial semiconductor layer; forming a Schottky barrier metal layer covering at least the epitaxial semiconductor layer of the active region; and forming a bonding metal layer connecting at least the Schottky barrier metal layer.

A junction barrier Schottky diode of another embodiment of the present invention comprises: a semiconductor substrate; an epitaxial semiconductor layer disposed on the semiconductor substrate, the epitaxial semiconductor layer defining an active region and a termination region, and A plurality of trenches are formed on the crystalline semiconductor layer to be distributed in the active region and the termination region; the plurality of ion implantation regions are formed in the epitaxial semiconductor layer of the active region and the termination region, and the ion implantation region corresponds to the bottom surface position of the trench; The electrical layer structure covers the surface of the epitaxial semiconductor layer and the trench of the termination region in the termination region; a Schottky barrier metal layer covers at least the surface of the epitaxial semiconductor layer of the active region and the inner and bottom surfaces of the trench of the active region; A bonding metal layer connects at least the Schottky barrier metal layer.

The purpose, technical contents, features, and effects achieved by the present invention will become more apparent from the detailed description of the appended claims.

10‧‧‧Schottky diode

12‧‧‧N+矽 substrate

14‧‧‧N-矽 epitaxial layer

16‧‧‧P+ diffusion barrier

18‧‧‧Schottky metal layer

W‧‧‧ conduction width

20, 22, 24, 26, 28 ‧ ‧ steps

30‧‧‧N type semiconductor substrate

32‧‧‧N type epitaxial semiconductor layer

34‧‧‧Active Area

36‧‧‧End zone

38‧‧‧First dielectric layer

40‧‧‧First patterned photoresist layer

42‧‧‧ first opening

44‧‧‧P type planting area

46‧‧‧Second dielectric layer

48‧‧‧Second patterned photoresist layer

50‧‧‧second opening

51‧‧‧Light-shielding shelter

511‧‧ ‧ junction

52‧‧‧ Schottky barrier metal layer

54‧‧‧Join metal layer

56, 66‧‧ ‧ joint barriers, Schottky diodes

58‧‧‧Dielectric layer structure

60, 60a‧‧‧ trench

62‧‧‧ bottom

64‧‧‧ wall

Figure 1 shows the structure of a conventional Schottky diode.

2 is a flow chart showing a method of manufacturing a junction barrier Schottky diode according to an embodiment of the present invention.

3a-3h are cross-sectional views showing a method of fabricating a junction barrier Schottky diode according to a first embodiment of the present invention.

4a-4i illustrate a second embodiment of the present invention, a junction barrier, a Schottky diode Schematic diagram of the manufacturing method of the body.

The detailed description is as follows, and the preferred embodiment is not intended to limit the invention.

2 is a flow chart showing a method of manufacturing a junction barrier Schottky diode according to an embodiment of the present invention. Forming an epitaxial semiconductor layer on a semiconductor substrate, the epitaxial semiconductor layer defining an active region and a termination region, which is step 20; using a patterned photoresist layer as a mask, and simultaneously including an active region and a termination region The epitaxial semiconductor layer is ion implanted to form an ion implantation region in a part of the surface of the epitaxial semiconductor layer, which is step 22; forming a dielectric layer structure covering the epitaxial semiconductor layer of the termination region, which is step 24 Forming a Schottky barrier metal layer overlying the epitaxial semiconductor layer of the active region, which is step 26; and forming a bonding metal layer to connect at least the Schottky barrier metal layer, which is step 28.

3a-3h are schematic cross-sectional views showing a method of fabricating a junction barrier Schottky diode according to a first embodiment of the present invention. In the figures, some of the dimensions of the structure or parts may be exaggerated relative to other structures or parts and are not drawn to actual scale and thus may be used to show the general structure of the invention.

As shown in FIG. 3a, an epitaxial semiconductor layer is formed on a semiconductor substrate. In one embodiment, the semiconductor substrate is a high concentration doped N-type semiconductor substrate 30 (shown as N+), and the epitaxial semiconductor layer is low. The concentration-doped N-type epitaxial semiconductor layer 32 (shown as N-) defines an active region 34 and a termination region 36, and the termination region 36 is located around the N-type epitaxial semiconductor layer 32. region.

As shown in FIG. 3b, a first dielectric layer 38 and a first patterned photoresist layer 40 are sequentially formed on the N-type epitaxial semiconductor layer 32. The first patterned photoresist layer 40 includes a plurality of first layers. The opening 42 is to expose a portion of the surface of the first dielectric layer 38. In one embodiment, the first dielectric layer 38 is an oxide layer, such as a hafnium oxide layer.

As shown in FIG. 3c, the N-type epitaxial semiconductor layer 32 is ion implanted with the first patterned photoresist layer 40 as a mask to simultaneously form the N-type epitaxial semiconductor layer 32 of the active region 34 and the termination region 36. The surface is implanted with a dopant and rapidly tempered to activate the dopant, in one embodiment, The dopant is a P-type dopant to form a P-type implant region 44 in the N-type epitaxial semiconductor layer 32, and a PN interface depletion region is formed between the P-type implant region 44 and the N-type epitaxial semiconductor layer 32. . Thereafter, the first patterned photoresist layer 40 is removed, as shown in FIG. 3d, leaving the first dielectric layer 38.

Next, as shown in FIG. 3e, a second dielectric layer 46 is formed on the first dielectric layer 38, and a second patterned photoresist layer 48 is disposed on the second dielectric layer 46, wherein the second patterning is performed. The photoresist layer 48 includes at least one second opening 50 corresponding to the position of the active region 34. In one embodiment, the second dielectric layer 46 is an oxide layer, and the second dielectric layer 46 is made of the same material or different from the material of the first dielectric layer 38.

As shown in FIG. 3f, the second patterned photoresist layer 48 is used as a mask to sequentially remove the second dielectric layer 46 and the first dielectric layer 38 exposed through the second opening (shown in FIG. 3e). The N-type epitaxial semiconductor layer 32 and the P-type implant region 44 of the active region 34 are exposed, and the first dielectric layer 38 and the second dielectric layer 46 on the termination region 36 are retained.

Thereafter, the second patterned photoresist layer 48 is removed, and as shown in FIG. 3g, a Schottky barrier metal layer 52 is formed to cover the surface of the N-type epitaxial semiconductor layer 32 and the P-type implant region 44 of the active region 34. In order to form a metal-semiconductor Schottky contact, in one embodiment, the Schottky barrier metal layer may be made of silver, aluminum, gold, titanium or platinum.

As shown in FIG. 3h, a bonding metal layer is formed to connect at least the Schottky barrier metal layer 52. In one embodiment, the bonding metal layer 54 covers the surface and a portion of the Schottky barrier metal layer 52. The surface of the electrical layer 46.

Continuing to refer to FIG. 3h, the junction barrier Schottky diode 56 of the present invention includes an N-type semiconductor substrate 30; an N-type epitaxial semiconductor layer 32 is disposed on the semiconductor substrate 30, N-type. The epitaxial semiconductor layer 32 defines an active region 34 and a termination region 36; a plurality of P-type implant regions 44 are formed in the N-type epitaxial semiconductor layer 32 of the active region 34 and the termination region 36; and a first dielectric layer 38 And a dielectric layer structure 58 stacked on the second dielectric layer 46 covers the surface of the N-type epitaxial semiconductor layer 32 of the termination region 36 and the P-type implant region 44 in the termination region 36; a Schottky barrier The metal layer 52 covers the surface of the N-type epitaxial semiconductor layer 32 of the active region 34; and a bonding metal layer 54 covers the surface of the Schottky barrier metal layer 52 and a portion of the dielectric layer structure 58. The dielectric layer structure 58 located in the termination region 36 serves to eliminate the problem of edge leakage current due to Schottky contact of the metal-semiconductor.

4a-4I are cross-sectional views showing a method of fabricating a junction barrier Schottky diode according to a second embodiment of the present invention. In the figures, some of the dimensions of the structure or parts may be exaggerated relative to other structures or parts and are not drawn to actual scale and thus may be used to show the general structure of the invention.

As shown in FIG. 4a, an epitaxial semiconductor layer is formed on a semiconductor substrate. In one embodiment, the semiconductor substrate is a high concentration doped N-type semiconductor substrate 30 (shown as N+), and the epitaxial semiconductor layer is The low concentration doped N-type epitaxial semiconductor layer 32 (shown as N-), and the N-type epitaxial semiconductor layer 32 defines an active region 34 and a termination region 36, and the termination region 36 is located in the N-type epitaxial semiconductor layer 32. The surrounding area.

As shown in FIG. 4b, a first dielectric layer 38 and a first patterned photoresist layer 40 are sequentially formed on the N-type epitaxial semiconductor layer 32, wherein the first patterned photoresist layer 40 includes a plurality of first layers. The opening 42 is to expose a portion of the surface of the first dielectric layer 38. In one embodiment, the first dielectric layer 38 is an oxide layer, such as a hafnium oxide layer.

As shown in FIG. 4c, a portion of the first dielectric layer 38 and a portion of the N-type epitaxial semiconductor layer 32 are removed by using the first patterned photoresist layer 40 as a mask to form an N-type of the active region 34 and the termination region 36. A plurality of trenches 60 are formed on the epitaxial semiconductor layer 32, and each of the trenches 60 has a bottom surface 62 and opposite sidewall surfaces 64.

As shown in FIG. 4d, the N-type epitaxial semiconductor layer 32 is ion implanted with the first patterned photoresist layer 40 as a mask, and simultaneously on the surface of the N-type epitaxial semiconductor layer 32 of the active region 34 and the termination region 36. The dopant is implanted and rapidly tempered to activate the dopant. In one embodiment, the dopant is a P-type dopant for the underside 62 of the N-type epitaxial semiconductor layer 32 and the trench 60. A P-type implant region 44 is formed underneath, and a PN interface depletion region is formed between the P-type implant region 44 and the N-type epitaxial semiconductor layer 32. Thereafter, the first patterned photoresist layer 40 is removed, as shown in FIG. 4e, leaving the first dielectric layer 38.

Next, as shown in FIG. 4f, a second dielectric layer 46 is formed on the first dielectric layer 38, so that the second dielectric layer 46 covers the bottom surface 62, the wall surface 64 and the adjacent trenches 60 of each trench 60. a second patterned photoresist layer 48 is disposed on the second dielectric layer 46, wherein the second patterned photoresist layer 48 includes at least one second opening 50 corresponding to the active The location of the region 34, preferably the second opening 50 of the second patterned photoresist layer 48 and the photoresist mask The junction 511 of the portion 51 is located above the second dielectric layer 46 of one of the trenches 60a, that is, one side of the photoresist mask 51 covers a portion of the second dielectric layer 46 on the trench 60a. In one embodiment, the second dielectric layer 46 is an oxide layer, and the second dielectric layer 46 is made of the same material or different from the material of the first dielectric layer 38.

As shown in FIG. 4g, the second patterned photoresist layer 48 is used as a mask to sequentially remove the second dielectric layer 46 and the first dielectric layer 38 exposed through the second opening 50 to expose the active region 34. The surface of the N-type epitaxial semiconductor layer 32, the surface of the P-type implant region 44, and the plurality of trenches 60 on the active region 34, and retaining the first dielectric layer 38 and the second dielectric layer 46 on the termination region 36, As shown in Figure 4g, in one embodiment, the second dielectric layer 46 within the trench 60a is partially removed and partially retained.

Thereafter, the second patterned photoresist layer 48 is removed, as shown in FIG. 4h, forming a Schottky barrier metal layer 52 covering the active region 34 of the N-type epitaxial semiconductor layer 32, the P-type implant region 44, and the active The wall 64 and the bottom surface 62 of the trench 60 of the region 34 form a metal-semiconductor Schottky contact. In one embodiment, as shown in Figure 4h, the Schottky barrier metal layer 52 and the second dielectric layer The 46 contact connection is located at the bottom surface 62 of the groove 60a, but is not limited thereto. The material of the Schottky barrier metal layer can be silver, aluminum, gold, titanium or platinum.

As shown in FIG. 4i, a bonding metal layer 54 is formed to connect at least the Schottky barrier metal layer 52. In one embodiment, the bonding metal layer 54 covers the surface and portions of the Schottky barrier metal layer 52. The surface of the second dielectric layer 46.

Referring to FIG. 4i, the junction barrier Schottky diode 66 of the present invention includes an N-type semiconductor substrate 30; an N-type epitaxial semiconductor layer 32 is disposed on the N-type semiconductor substrate 30. The N-type epitaxial semiconductor layer 32 defines an active region 34 and a termination region 36; a plurality of P-type implant regions 44 are formed in the N-type epitaxial semiconductor layer 32 of the active region 32 and the termination region 34, and the P-type implant region 44 corresponds to the position of the bottom surface 62 of the trench 60; a dielectric layer structure 58 stacked by the first dielectric layer 38 and the second dielectric layer 46 covers the N-type epitaxial semiconductor layer 32 of the termination region 36. The surface, the P-type implant region 44 of the termination region 36 and the trench 60 of the termination region 36; a Schottky barrier metal layer 52 covering the surface of the N-type epitaxial semiconductor layer 32 of the active region 34, and the P-type of the active region 34 The trenches 60 of the implant region 44 and the active regions 34; and a bonding metal layer 54 cover the surface of the Schottky barrier metal layer 52 and a portion of the dielectric layer structure 58.

Fabrication of junction barrier Schottky diodes of the first embodiment and the second embodiment The difference between the two is mainly in the second embodiment. A plurality of trenches 60 are formed on the surface of the N-type epitaxial semiconductor layer 32, and then an ion implantation process is performed, so that the distribution of the P-type implanted regions 44 corresponds to the trenches 60. In the first embodiment, the surface of the N-type epitaxial semiconductor layer 32 is a planar structure instead of the structure having the trenches 60.

In the manufacturing method of the junction barrier Schottky diode of the first and second embodiments, the ion implantation can be shortened by ion implantation of the N-type epitaxial semiconductor layer simultaneously in the active region and the termination region. The process steps of the Schottky diode are used to reduce production costs. Further, the implantation of the dopant into the active region by the ion implantation step is different from the conventional high-temperature diffusion process, and the problem of the conventional conduction width reduction caused by lateral diffusion can be avoided. The junction barrier Schottky diode fabricated by the invention has the advantage of higher efficiency.

The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent changes or modifications made by the spirit of the present invention should still be covered by the patent of the present invention.

20, 22, 24, 26, 28 ‧ ‧ steps

Claims (19)

A method for fabricating a junction barrier Schottky diode includes: forming an epitaxial semiconductor layer on a semiconductor substrate, the epitaxial semiconductor layer defining an active region and a termination region; forming a first dielectric layer in sequence An electric layer and a first patterned photoresist layer on the epitaxial semiconductor layer, wherein the first patterned photoresist layer comprises a plurality of first openings to expose a portion of the surface of the first dielectric layer; The patterned photoresist layer is a mask, and the epitaxial semiconductor layer including the active region and the termination region is ion implanted to implant a dopant into a portion of the surface of the epitaxial semiconductor layer; a first patterned photoresist layer; a second dielectric layer and a second patterned photoresist layer are sequentially formed on the first dielectric layer, wherein the second patterned photoresist layer comprises at least one second opening Corresponding to the active region; using the second patterned photoresist layer as a mask, removing the second dielectric layer and the first dielectric layer exposed through the second opening to expose the active region; The second patterned photoresist layer; forming a Schottky barrier metal layer covering at least the main Region; and forming a metal layer is joined, can be at least connected to the Schottky barrier metal layer. The method for fabricating a junction barrier Schottky diode according to claim 1, wherein the semiconductor substrate is an N-type semiconductor substrate, and the epitaxial semiconductor layer is a low concentration doped N-type epitaxial semiconductor layer. The dopant is a P-type dopant. The method of fabricating a junction barrier Schottky diode according to claim 1, wherein the first dielectric layer is an oxide layer. The method of fabricating a junction barrier Schottky diode according to claim 1, wherein the second dielectric layer is an oxide layer. The method for manufacturing a junction barrier Schottky diode according to claim 1, wherein the material of the Schottky barrier metal layer is silver, aluminum, gold, titanium or platinum. A method for manufacturing a junction barrier Schottky diode, comprising: Forming an epitaxial semiconductor layer on a semiconductor substrate, the epitaxial semiconductor layer defining an active region and a termination region; sequentially forming a first dielectric layer and a first patterned photoresist layer on the epitaxial semiconductor layer The first patterned photoresist layer includes a plurality of first openings to expose a portion of the surface of the first dielectric layer; the first patterned photoresist layer is used as a mask to remove a portion of the first dielectric And forming a plurality of trenches in the active region and the epitaxial semiconductor layer of the termination region; using the first patterned photoresist layer as a mask, simultaneously including the active region and the The epitaxial semiconductor layer of the termination region is ion implanted to implant a dopant into a portion of the surface of the epitaxial semiconductor layer; removing the first patterned photoresist layer; forming a second dielectric layer, covering Forming a second patterned photoresist layer on the first dielectric layer and covering at least the wall surface and the bottom surface of the trenches, and covering the second dielectric layer and the second portion of the trenches a dielectric layer, the second patterned photoresist layer comprising at least one second opening corresponding to The second patterned dielectric layer and the first dielectric layer are removed by the second patterned photoresist layer to expose the epitaxial semiconductor layer of the active region And the trenches on the active region; removing the second patterned photoresist layer; forming a Schottky barrier metal layer covering at least the epitaxial semiconductor layer of the active region and the active region a wall surface and a bottom surface of the trench; and forming a bonding metal layer connecting at least the Schottky barrier metal layer. The method for fabricating a junction barrier Schottky diode according to claim 6, wherein the semiconductor substrate is an N-type semiconductor substrate, and the epitaxial semiconductor layer is a low concentration doped N-type epitaxial semiconductor layer. The dopant is P+ doped. The method of fabricating a junction barrier Schottky diode according to claim 6, wherein the first dielectric layer is an oxide layer. The method of fabricating a junction barrier Schottky diode according to claim 6, wherein the second dielectric layer is an oxide layer. The method for manufacturing a junction barrier Schottky diode according to claim 6, wherein the material of the Schottky barrier metal layer is silver, aluminum, gold, titanium or platinum. A method for fabricating a junction barrier Schottky diode includes: forming an epitaxial semiconductor layer on a semiconductor substrate, the epitaxial semiconductor layer defining an active region and a termination region; and patterning the photoresist layer a masking layer is simultaneously ion implanted on the epitaxial semiconductor layer including the active region and the termination region to form an ion implantation region in a portion of the surface of the epitaxial semiconductor layer; forming a dielectric layer covering the The epitaxial semiconductor layer of the termination region; forming a Schottky barrier metal layer covering at least the active region; and forming a bonding metal layer connecting at least the Schottky barrier metal layer. The method for fabricating a junction barrier Schottky diode according to claim 11, wherein the semiconductor substrate is an N-type semiconductor substrate, and the epitaxial semiconductor layer is a low concentration doped N-type epitaxial semiconductor layer. The dopant is P+ doped. The method for fabricating a junction barrier Schottky diode according to claim 11, wherein a plurality of trenches are formed in the epitaxial semiconductor layer of the active region and the termination region before the ion implantation. The method of fabricating a junction barrier Schottky diode according to claim 13, wherein the dielectric layer covers the epitaxial semiconductor layer of the termination region and the trenches of the termination region. The method for fabricating a junction barrier Schottky diode according to claim 13, wherein the Schottky barrier metal layer covers at least the surface of the epitaxial semiconductor layer of the active region and the trenches of the active region The inner and bottom surfaces of the groove. A junction barrier Schottky diode comprising: a semiconductor substrate; an epitaxial semiconductor layer disposed on the semiconductor substrate, the epitaxial semiconductor layer defining An active region and a termination region, and the epitaxial semiconductor layer is formed with a plurality of trenches distributed in the active region and the termination region; a plurality of ion implantation regions, an epitaxial semiconductor layer formed in the active region and the termination region Internally, and the ion implantation regions correspond to the bottom surface positions of the trenches; a dielectric layer structure covering the surface of the epitaxial semiconductor layer of the termination region and the trenches of the termination region; The barrier metal layer covers at least the surface of the epitaxial semiconductor layer of the active region and the inner and bottom surfaces of the trenches of the active region; and a bonding metal layer connecting at least the Schottky barrier metal layer. The junction barrier Schottky diode according to claim 16, wherein the semiconductor substrate is an N-type semiconductor substrate, and the epitaxial semiconductor layer is a low concentration doped N-type epitaxial semiconductor layer, the doping The system is P+ doped. The junction barrier Schottky diode of claim 16 wherein the dielectric layer structure is an oxide layer. The junction barrier Schottky diode of claim 16, wherein the Schottky barrier metal layer is made of silver, aluminum, gold, titanium or platinum.