TW201517263A - Horizontal bipolar crystal crystal and manufacturing method thereof - Google Patents
Horizontal bipolar crystal crystal and manufacturing method thereof Download PDFInfo
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Abstract
本發明的課題是在於提供一種在可與微細CMOSFET，LDMOSFET混載的橫型雙極電晶體中，不易受製造偏差的影響，具有高增益的電晶體構造，製造方法。 被揭示的橫型雙極電晶體是以具有對於閘極電極藉由自我整合地雜質植入，擴散來形成基極及射極層的製造工程及構造的點作為特徴。而且，將閘極電極附加於基極，射極，集極，作為獨立的第4個的端子利用之下，藉由賦予的閘極電位，可控制提升hfe作為特徴。由以上可提供一種不易受製造偏差的影響，或，可藉由閘極端子修正之具有高增益的雙極電晶體。 An object of the present invention is to provide a transistor structure having a high gain and a manufacturing method in a horizontal bipolar transistor which can be mixed with a fine CMOSFET or an LDMOSFET, which is less susceptible to manufacturing variations. The disclosed lateral bipolar transistor is characterized by having a manufacturing process and structure for forming a base and an emitter layer by implanting and diffusing impurities into the gate electrode by self-integration. Further, by adding a gate electrode to the base, the emitter, and the collector, as an independent fourth terminal, the gate potential can be controlled to enhance the hfe. From the above, it is possible to provide a bipolar transistor having high gain which is not easily affected by manufacturing variations or which can be corrected by a gate terminal.
Description
本發明是有關橫型雙極電晶體及其製造方法，特別是有關橫型雙極電晶體的構造及其製造方法。 The present invention relates to a lateral bipolar transistor and a method of fabricating the same, and more particularly to a structure of a lateral bipolar transistor and a method of fabricating the same.
作為構成開關(switching)動作電路的元件，可舉雙極電晶體。 As an element constituting a switching operation circuit, a bipolar transistor can be cited.
在圖1顯示控制負荷的開關動作電路的例子。引進電流控制負荷時，是適用圖1(a)所示那樣的NPN雙極電晶體4，且流放電流控制負荷時，是如圖1(b)所示那樣適用PNP型雙極電晶體8。在此，作為適用雙極電晶體的優點，是在於可用小的輸入訊號Ib來流動大的集極電流Ic的點。近年來，可舉電動車等作為本電路應用，被要求驅動大的負荷之電晶體。並且，供給的電源亦為高電壓，所以也被要求高耐壓特性。而且，與輸出脈衝的位準位移器(level shifter)，邏輯電路的混載性也是在低成本化中為重要。 An example of a switching operation circuit for controlling a load is shown in FIG. When the current control load is introduced, the NPN bipolar transistor 4 as shown in Fig. 1(a) is applied, and when the current control load is applied, the PNP type bipolar transistor 8 is applied as shown in Fig. 1(b). Here, as an advantage of the application of the bipolar transistor, a point at which the large collector current Ic can flow with the small input signal Ib can be used. In recent years, an electric vehicle or the like has been proposed as a circuit for this circuit, and it is required to drive a large load of a transistor. Further, since the supplied power source is also a high voltage, high withstand voltage characteristics are also required. Moreover, with the level shifter of the output pulse, the hybridity of the logic circuit is also important in cost reduction.
對於該等的需求，半導體各公司開發一種以微細且可高速動作的CMOSFET製程為基礎，高耐壓 DMOSFET，而且可混載雙極電晶體的橫型構造元件，謀求低成本化。有關雙極電晶體也是以使集極，基極，射極端子取出於半導體基板表面上的方式形成，具有與其他元件混載性的構造發明。 For these needs, semiconductor companies have developed a high-withstand voltage based on a fine and high-speed CMOSFET process. The DMOSFET is also capable of mixing a lateral structure element of a bipolar transistor to achieve cost reduction. The bipolar transistor is also formed in such a manner that the collector, the base, and the emitter are taken out from the surface of the semiconductor substrate, and has a structure in which it is mixed with other elements.
在圖2顯示記載於專利文獻1的雙極電晶體剖面構造。在半導體基板表面，N型集極漂移層19的深的位置形成濃度高的N型集極層11，在此上空隔著低濃度的漂移層19來形成P型基極層10，且在其上空形成有N型射極層9。任一層皆被連接至各露出於基板表面的集極電極17，基極電極16，射極電極15，成為被形成於基板內部的NPN雙極電晶體20可經由形成於基板表面的電極來控制的構造。 The bipolar transistor cross-sectional structure described in Patent Document 1 is shown in Fig. 2 . On the surface of the semiconductor substrate, the N-type collector layer 11 having a high concentration is formed at a deep position of the N-type collector drift layer 19, and the P-type base layer 10 is formed by interposing a low-concentration drift layer 19 thereon. An N-type emitter layer 9 is formed over the sky. Any of the layers is connected to the collector electrode 17, the base electrode 16, and the emitter electrode 15 which are exposed on the surface of the substrate, and the NPN bipolar transistor 20 formed inside the substrate can be controlled via electrodes formed on the surface of the substrate. Construction.
但，在此構造中，相對於射極領域，具有深的分布之基極領域是利用與射極領域不同的光罩來形成，因此暗示光罩位置的偏差會波及形成於垂直方向的雙極電晶體的實效性的基極濃度的偏差。基極濃度與雙極電晶體的放大率hfe的關係是如數學式1所示般。 However, in this configuration, the base field having a deep distribution with respect to the field of the emitter is formed by using a mask different from the field of the emitter, and therefore it is suggested that the deviation of the position of the mask may affect the bipolar formed in the vertical direction. The deviation of the base concentration of the effectiveness of the transistor. The relationship between the base concentration and the magnification hfe of the bipolar transistor is as shown in Mathematical Formula 1.
在此，Wb：基極幅，Lb：基極之電子的擴散 長，Dp：電洞的擴散係數，Dn：電子的擴散係數，Nb：基極濃度，Ne：射極濃度。 Here, Wb: base width, Lb: diffusion of electrons at the base Long, Dp: diffusion coefficient of the hole, Dn: diffusion coefficient of electrons, Nb: base concentration, Ne: emitter concentration.
放大率hfe是依存於基極濃度，因此，本構造對於放大率hfe，在製造工程上具有稱光罩位置的偏差因子。 The magnification hfe is dependent on the base concentration. Therefore, the present configuration has a deviation factor of the reticle position in the manufacturing process for the magnification hfe.
[專利文獻1]日本特開2012-129297號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2012-129297
[專利文獻2]日本特開2010-251624號公報 [Patent Document 2] Japanese Patent Laid-Open Publication No. 2010-251624
在半導體表面，以安定的濃度，擴散長來形成雜質領域的方法，有以專利文獻2所記載的閘極電極自對準製造手法來植入雜質的手法。 A method of forming an impurity region by a diffusion concentration at a stable concentration on a semiconductor surface is a method of implanting impurities by a gate electrode self-alignment manufacturing method described in Patent Document 2.
在圖3顯示記載於文獻的製造工程的部分剖面。 A partial cross section of the manufacturing process described in the literature is shown in FIG.
對於閘極電極22，自對準地將P型雜質植入25，藉由熱負荷來使擴散後，同樣對於閘極電極22，自我整合地將N型雜質植入27。藉此，在閘極下形成的P型雜質領域26的擴散長及濃度是經常形成一定。在此發明中，應用是橫型LDMOSFET，以安定的Vth，低成本化作為發明效果，有關對雙極電晶體的適用以外的記載是未 見。可想像發明者們是藉由將此部分製造手法適用在雙極電晶體的射極-基極領域，特別是基極的形成部位，取得安定且高的hfe性能。 For the gate electrode 22, the P-type impurity is implanted 25 in a self-aligned manner, and after the diffusion by the thermal load, the N-type impurity is implanted 27 by self-integration also for the gate electrode 22. Thereby, the diffusion length and concentration of the P-type impurity region 26 formed under the gate are always formed constant. In this invention, the application is a horizontal LDMOSFET, and the cost is stabilized by Vth, which is an effect of the invention, and the description about the application to the bipolar transistor is not see. It is conceivable that the inventors have achieved a stable and high hfe performance by applying this part of the manufacturing method to the emitter-base field of the bipolar transistor, particularly the formation portion of the base.
本發明的目的是在於提供一種可與微細CMOSFET及LDMOSFET混載，且取得製造偏差小安定的hfe之橫型雙極電晶體及其製造方法。 It is an object of the present invention to provide a horizontal bipolar transistor which can be mixed with a fine CMOSFET and an LDMOSFET and which has a low variation in manufacturing variation and a method of manufacturing the same.
本發明之橫型雙極電晶體的特徵係具有：半導體基板；集極領域，其係具有設於半導體基板表面的閘極氧化膜，閘極電極，與前述閘極電極間隔距離而設，且具有第一導電型的給電領域；射極領域，其係與前述集極領域夾著閘極電極，在對極側設於閘極氧化膜附近，且具有第一導電型的給電領域；及第二導電型的基極領域，其係於前述閘極氧化膜之下，且以能夠包圍前述射極領域的方式設置，且具有接近射極給電領域的給電領域。 The horizontal bipolar transistor of the present invention has a semiconductor substrate and a collector field, and has a gate oxide film provided on a surface of the semiconductor substrate, and a gate electrode is disposed at a distance from the gate electrode, and The field of power supply having a first conductivity type; the field of emitters, which is provided with a gate electrode in the collector region, and is disposed near the gate oxide film on the opposite pole side, and has a first conductivity type of power supply field; The field of the base of the two-conductivity type is disposed under the gate oxide film and is provided in such a manner as to be able to surround the field of the emitter, and has a field of power supply close to the field of emitter power supply.
並且，最好前述集極領域，基極領域，射極領域的雜質濃度係形成：在閘極氧化膜下，前述半導體領域表面附近，依集極領域，基極領域，射極領域的順序變小。 Moreover, it is preferable that the impurity concentration in the field of the collector, the base field, and the emitter field is formed: in the vicinity of the surface of the semiconductor field under the gate oxide film, in the order of the collector field, the base field, and the emitter field. small.
若根據本發明，則可用能與微細CMOSFET及LDMOSFET混載的製程來實現安定具有高hfe的雙極電晶體。 According to the present invention, a bipolar transistor having a high hfe can be realized by a process capable of being mixed with a fine CMOSFET and an LDMOSFET.
並且，藉由對閘極電極供給電壓，賦予某一定的電壓，可控制hfe值，因此將雙極電晶體裝入反饋電路，在閘極電極控制之下，可實現具有安定的增益之電路，該安定的增益可修正製造起因的偏差。而且，可提供高品質的應用電路。 Further, by supplying a voltage to the gate electrode and giving a certain voltage, the hfe value can be controlled. Therefore, the bipolar transistor is incorporated in the feedback circuit, and a circuit having a stable gain can be realized under the control of the gate electrode. The stability gain can correct the deviation of the manufacturing cause. Moreover, high quality application circuits are available.
1‧‧‧低電壓電源VCC 1‧‧‧Low-voltage power supply VCC
2‧‧‧高電壓電源VH 2‧‧‧High voltage power supply VH
3‧‧‧負荷 3‧‧‧ load
4‧‧‧NPN雙極電晶體 4‧‧‧NPN bipolar transistor
5‧‧‧GND端子 5‧‧‧GND terminal
6‧‧‧基極電阻 6‧‧‧base resistance
7‧‧‧數位控制電路 7‧‧‧Digital Control Circuit
8‧‧‧PNP雙極電晶體 8‧‧‧PNP bipolar transistor
9‧‧‧N型射極層 9‧‧‧N-type emitter layer
10‧‧‧P型基極層 10‧‧‧P type base layer
11‧‧‧N型集極層 11‧‧‧N-type collector layer
12‧‧‧N型集極給電層 12‧‧‧N type collector power supply layer
13‧‧‧埋入氧化膜 13‧‧‧ buried oxide film
14‧‧‧氧化膜 14‧‧‧Oxide film
15‧‧‧射極電極 15‧‧ ‧ emitter electrode
16‧‧‧基極電極 16‧‧‧ base electrode
17‧‧‧集極電極 17‧‧‧ Collector electrode
18‧‧‧元件分離領域 18‧‧‧Parts of component separation
19‧‧‧N型集極漂移層 19‧‧‧N-type collector drift layer
20‧‧‧NPN雙極電晶體形成領域 20‧‧‧NPN bipolar transistor formation field
21‧‧‧閘極氧化膜 21‧‧‧ gate oxide film
22‧‧‧閘極電極 22‧‧‧gate electrode
23‧‧‧場氧化膜 23‧‧‧Field oxide film
24‧‧‧N型漂移層 24‧‧‧N type drift layer
25‧‧‧P型雜質的植入 25‧‧‧P-type impurity implantation
26‧‧‧P型阱層 26‧‧‧P-type well layer
27‧‧‧N型漂移層 27‧‧‧N type drift layer
28‧‧‧N型源極層 28‧‧‧N-type source layer
29‧‧‧N型射極給電層 29‧‧‧N type emitter power supply layer
30‧‧‧P型基極層 30‧‧‧P type base layer
31‧‧‧N型集極給電層 31‧‧‧N type collector power supply layer
32‧‧‧元件分離領域 32‧‧‧Parts of component separation
33‧‧‧閘極電極 33‧‧‧gate electrode
34‧‧‧閘極氧化膜 34‧‧‧Gate oxide film
35‧‧‧N型集極漂移層 35‧‧‧N-type collector drift layer
36‧‧‧P型基極給電層 36‧‧‧P type base power supply layer
37‧‧‧場氧化膜 37‧‧‧Field oxide film
38‧‧‧層間絕緣膜 38‧‧‧Interlayer insulating film
39‧‧‧基極柱塞 39‧‧‧Base plunger
40‧‧‧基極電極 40‧‧‧ base electrode
41‧‧‧射極柱塞 41‧‧ ‧ emitter plunger
42‧‧‧射極電極 42‧‧ ‧ emitter electrode
43‧‧‧集極柱塞 43‧‧‧ Collector Plunger
44‧‧‧集極電極 44‧‧‧ Collector electrode
45‧‧‧NPN雙極電晶體形成領域 45‧‧‧NPN bipolar transistor formation field
46‧‧‧P/N接合境界線 46‧‧‧P/N junction boundary
47‧‧‧基極長=250nm 47‧‧‧Base length = 250nm
48‧‧‧P型雜質植入(例如硼) 48‧‧‧P type impurity implantation (eg boron)
49‧‧‧N型雜質植入(例如砷) 49‧‧‧N type impurity implantation (eg arsenic)
50‧‧‧P型雜質植入(例如氟化硼) 50‧‧‧P type impurity implantation (eg boron fluoride)
51‧‧‧P型基極給電連接領域 51‧‧‧P type base power supply connection field
52‧‧‧基極長=100nm 52‧‧‧Base length = 100nm
53‧‧‧閘極柱塞 53‧‧‧Gate Plunger
54‧‧‧閘極電極 54‧‧‧gate electrode
55‧‧‧在基極層30形成有反轉層，集極-射極間洩漏電流會增大的領域 55‧‧‧In the reversed layer formed in the base layer 30, the leakage current between the collector and the emitter increases
56‧‧‧電子濃度檢驗處 56‧‧‧Electronic Concentration Inspection Office
56-2‧‧‧閘極電極，閘極氧化膜的領域 56-2‧‧‧ gate electrode, field of gate oxide film
56-3‧‧‧基極層的領域 56-3‧‧‧Fields of the base layer
57‧‧‧本發明的雙極電晶體 57‧‧‧Bipolar transistor of the invention
58‧‧‧射極端子 58‧‧‧shooting extremes
59‧‧‧集極端子 59‧‧‧Set extremes
60‧‧‧基極端子 60‧‧‧ base extremes
61‧‧‧閘極端子 61‧‧ ‧ gate terminal
62‧‧‧輸入端子 62‧‧‧Input terminal
63‧‧‧增益調整用負荷 63‧‧‧Gas adjustment load
64‧‧‧輸出端子 64‧‧‧Output terminal
圖1(a)是表示由雙極電晶體所構成的泛用電路的圖。 Fig. 1(a) is a view showing a general-purpose circuit composed of a bipolar transistor.
圖1(b)是表示有雙極電晶體所構成的泛用電路的圖。 Fig. 1(b) is a view showing a general-purpose circuit including a bipolar transistor.
圖2是表示含以往技術的雙極電晶體構造的圖。 Fig. 2 is a view showing the structure of a bipolar transistor including the prior art.
圖3(a)是表示含以往技術的閘極自對準製造手法的圖。 Fig. 3(a) is a view showing a method of manufacturing a gate self-alignment including the prior art.
圖3(b)是表示含以往技術的閘極自對準製造手法的圖。 Fig. 3(b) is a view showing a method of manufacturing a gate self-alignment including the prior art.
圖4是表示本發明的第1實施例的橫型雙極電晶體的元件構造的平面圖。 4 is a plan view showing an element structure of a lateral bipolar transistor according to a first embodiment of the present invention.
圖5是表示本發明的第1實施例的橫型雙極電晶體的元件構造的剖面圖。 Fig. 5 is a cross-sectional view showing an element structure of a lateral bipolar transistor according to a first embodiment of the present invention.
圖6是表示以製程模擬計算之本發明的第1實施例的橫型雙極電晶體的雜質輪廓的剖面圖。 Fig. 6 is a cross-sectional view showing an impurity profile of a lateral bipolar transistor according to a first embodiment of the present invention which is calculated by a process simulation.
圖7是表示以製程模擬計算之本發明的第1實施例的橫型雙極電晶體NPN接合部位的詳細濃度分布的圖。 Fig. 7 is a view showing a detailed concentration distribution of a lateral bipolar transistor NPN junction portion of the first embodiment of the present invention calculated by a process simulation.
圖8是表示以裝置模擬計算之本發明的第1實施例的橫型雙極電晶體的電子電流密度輪廓的剖面圖。 Fig. 8 is a cross-sectional view showing an electron current density profile of a lateral bipolar transistor according to a first embodiment of the present invention calculated by a device simulation.
圖9(a)是表示本發明的第2實施例的橫型雙極電晶體的製造方法的製程流程圖。 Fig. 9 (a) is a process flow diagram showing a method of manufacturing a lateral bipolar transistor according to a second embodiment of the present invention.
圖9(b)是表示本發明的第2實施例的橫型雙極電晶體的製造方法的製程流程圖。 Fig. 9 (b) is a process flow diagram showing a method of manufacturing a lateral bipolar transistor according to a second embodiment of the present invention.
圖10是表示本發明的第3實施例的橫型雙極電晶體的元件構造的平面圖。 Fig. 10 is a plan view showing an element structure of a lateral bipolar transistor according to a third embodiment of the present invention.
圖11是表示本發明的第3實施例的橫型雙極電晶體的元件構造的剖面圖。 Fig. 11 is a cross-sectional view showing the structure of an element of a lateral bipolar transistor according to a third embodiment of the present invention.
圖12是表示以製程模擬計算之本發明的第3實施例的橫型雙極電晶體的雜質輪廓的剖面圖。 Fig. 12 is a cross-sectional view showing an impurity profile of a lateral bipolar transistor of a third embodiment of the present invention which is calculated by a process simulation.
圖13是表示以製程模擬計算之本發明的第3實施例的橫型雙極電晶體NPN接合部位的詳細濃度分布的圖。 Fig. 13 is a view showing a detailed concentration distribution of a lateral bipolar transistor NPN junction portion of a third embodiment of the present invention which is calculated by a process simulation.
圖14是表示以裝置模擬計算之本發明的第3實施例的橫型雙極電晶體的電子電流密度輪廓的剖面圖。 Fig. 14 is a cross-sectional view showing an electron current density profile of a lateral bipolar transistor of a third embodiment of the present invention calculated by a device simulation.
圖15(a)是表示本發明的第4實施例的橫型雙極電晶體的製造方法的製程流程圖。 Fig. 15 (a) is a process flow diagram showing a method of manufacturing a lateral bipolar transistor according to a fourth embodiment of the present invention.
圖15(b)是表示本發明的第4實施例的橫型雙極電晶體的製造方法的製程流程圖。 Fig. 15 (b) is a process flow diagram showing a method of manufacturing a lateral bipolar transistor according to a fourth embodiment of the present invention.
圖15(c)是表示本發明的第4實施例的橫型雙極電晶體的製造方法的製程流程圖。 Fig. 15 (c) is a process flow diagram showing a method of manufacturing a lateral bipolar transistor according to a fourth embodiment of the present invention.
圖16是表示本發明的第5實施例的橫型雙極電晶體的製造方法的製程流程圖。 Fig. 16 is a process flow diagram showing a method of manufacturing a lateral bipolar transistor according to a fifth embodiment of the present invention.
圖17是表示以裝置模擬計算之本發明的第5實施例的橫型雙極電晶體的hfe-Vg依存性的圖。 Fig. 17 is a view showing the hfe-Vg dependency of the lateral bipolar transistor of the fifth embodiment of the present invention calculated by the device simulation.
圖18是表示以裝置模擬計算之隨本發明的第5實施例的橫型雙極電晶體的Vg施加之電子密度的變化的圖。 Fig. 18 is a graph showing changes in electron density of Vg applied by a lateral bipolar transistor according to a fifth embodiment of the present invention, which is calculated by a device simulation.
圖19是表示以裝置模擬計算之隨本發明的第5實施例的橫型雙極電晶體的Vg施加之電子密度的詳細變化的圖。 Fig. 19 is a view showing a detailed change in electron density of Vg applied by a lateral bipolar transistor according to a fifth embodiment of the present invention, which is calculated by the device simulation.
圖20是表示本發明的第5實施例的橫型雙極電晶體的應用電路的概略圖。 Fig. 20 is a schematic view showing an application circuit of a lateral bipolar transistor according to a fifth embodiment of the present invention.
以下，利用圖面來詳細說明有關本發明的實施例。以下的說明的導電型是其一例，即使分別將各實施例的N型，P型設為逆極性，還是可期待同樣的效果。 Hereinafter, embodiments of the present invention will be described in detail using the drawings. The conductivity type described below is an example, and the same effect can be expected even if the N type and the P type of each embodiment are respectively set to have opposite polarities.
圖4是表示本發明的第1實施例的橫型雙極電晶體的元件構造的平面圖，圖5是表示本發明的第1實施例的橫型雙極電晶體的元件構造的剖面圖(圖4的A-A‘部位的剖面圖)。 4 is a plan view showing an element structure of a lateral bipolar transistor according to a first embodiment of the present invention, and FIG. 5 is a cross-sectional view showing an element structure of a lateral bipolar transistor according to a first embodiment of the present invention. Sectional view of the AA' portion of 4).
在具有N型漂移層35的半導體基板的表面上選擇性地形成有場氧化膜37，閘極氧化膜34，閘極電極33，並且，隔著閘極電極33，藉由雜質植入，熱擴散來自我整合地形成基極領域30。而且，在比基極領域更半導體表面淺的領域中，同樣隔著閘極電極33，藉由雜質植入，熱擴散來自我整合地形成射極給電層29。在其接觸的位置形成有基極給電層36。而且，在隔著場氧化膜37而與本領域相反的側形成有集極給電層31。 On the surface of the semiconductor substrate having the N-type drift layer 35, a field oxide film 37, a gate oxide film 34, a gate electrode 33, and a gate electrode 33 are interposed by impurities, and heat is implanted. Diffusion comes from my integration to form the base field 30. Moreover, in the field where the semiconductor surface is shallower than the base field, the emitter electrode 13 is formed integrally by heat diffusion by the impurity implantation also via the gate electrode 33. A base power supply layer 36 is formed at a position where it contacts. Further, the collector power supply layer 31 is formed on the side opposite to the field in the field oxide film 37.
而且，在基極給電層36是經過基極柱塞(plug)39而形成有基極電極40，在射極給電層29是經過射極柱塞41而形成有射極電極42，而且，在集極給電層31是經過集極柱塞43而形成有集極電極44，顯示適用本發明的橫型雙極電晶體。 Further, in the base power supply layer 36, a base electrode 40 is formed through a base plug 39, and in the emitter power supply layer 29, an emitter electrode 42 is formed through an emitter plug 41, and The collector supply layer 31 is formed with a collector electrode 44 via a collector plug 43, and shows a lateral bipolar transistor to which the present invention is applied.
圖6是以製程模擬作成之適用本發明的橫型雙極電晶體剖面構造。在此，基極領域30是藉由對於閘極電極33自我整合地以加速能量30keV，雜質濃度5E13atom/cm2來將硼植入，熱擴散而形成。並且，射極領域29是對於閘極電極33自我整合地以60keV，雜質濃度2E15atom/cm2來將砷植入形成。算出形成有NPN接合的表面附近，B-B‘部位的雜質濃度分布者為圖7。 Fig. 6 is a cross-sectional view of a lateral bipolar transistor to which the present invention is applied by process simulation. Here, the base region 30 is formed by implanting boron and thermally diffusing the self-integration of the gate electrode 33 with an acceleration energy of 30 keV and an impurity concentration of 5E13 atom/cm 2 . Further, the emitter region 29 is formed by implanting arsenic at a bonding concentration of 2E15 atoms/cm 2 at a bonding temperature of the gate electrode 33 at a self-integration of 60 keV. The distribution of the impurity concentration in the vicinity of the surface where the NPN bonding was formed and the BB' portion was calculated as FIG.
本圖表是在縱軸取雜質濃度(/cm3)，在橫軸取距離(um)，可確認被調整以依射極，基極，集極的順序濃度降低，且基極長約250nm的NPN雙極電晶體存在的點。以裝置模擬計算此雙極電晶體性能之處，在 hfe=29，確認無問題放大動作的點。 In this graph, the impurity concentration (/cm 3 ) is taken on the vertical axis and the distance (um) is taken on the horizontal axis. It can be confirmed that the concentration is adjusted in order of the emitter, the base, and the collector, and the base length is about 250 nm. The point at which the NPN bipolar transistor exists. Where the performance of the bipolar transistor is calculated by the device simulation, at hfe=29, the point at which the problem-free amplification operation is confirmed is confirmed.
圖8是Vc=1V，Vb上昇動作時的電子電流輪廓(profile)，可確認電子從射極往集極流動，雙極放大動作的點。 8 is an electron current profile when Vc=1V and Vb rises, and it is possible to confirm the point at which electrons flow from the emitter to the collector and the bipolar amplification operation.
圖9是表示本發明的第2實施例的橫型雙極電晶體的製造工程的製程流程圖。 Fig. 9 is a flow chart showing the process of manufacturing a lateral bipolar transistor according to a second embodiment of the present invention.
首先，(a)在具有N型漂移層35的半導體基板表面上使閘極氧化膜34，閘極電極33圖案化，(b)對於閘極電極33自我整合地植入形成P型基極層的雜質硼48。(c)藉由施加熱負荷，形成P型基極層30。(d)對於閘極電極33自我整合地植入形成N型射極層及N型集極層的雜質砷49。(e)植入形成P型基極給電層的雜質氟化硼50。(f)施加熱負荷後，形成柱塞．電極，完成具有基極電極40，射極電極42，集極電極44的橫型雙極電晶體。 First, (a) the gate oxide film 34 and the gate electrode 33 are patterned on the surface of the semiconductor substrate having the N-type drift layer 35, and (b) the P-type base layer is formed by self-integration implantation for the gate electrode 33. Impurity of boron 48. (c) A P-type base layer 30 is formed by applying a heat load. (d) The impurity arsenic 49 forming the N-type emitter layer and the N-type collector layer is self-integrated for the gate electrode 33. (e) implanting an impurity boron fluoride 50 forming a P-type base power supply layer. (f) After applying a thermal load, a plunger is formed. The electrode completes a lateral bipolar transistor having a base electrode 40, an emitter electrode 42, and a collector electrode 44.
圖10是表示本發明的第3實施例的橫型雙極電晶體的元件構造的平面圖，圖11是表示本發明的第3實施例的橫型雙極電晶體的元件構造的剖面圖(圖4的A-A‘部位的剖面圖)。 FIG. 10 is a plan view showing an element structure of a lateral bipolar transistor according to a third embodiment of the present invention, and FIG. 11 is a cross-sectional view showing an element structure of a lateral bipolar transistor according to a third embodiment of the present invention. Sectional view of the AA' portion of 4).
在具有N型漂移層35的半導體基板表面上選 擇性地形成場氧化膜37，閘極氧化膜34，閘極電極33，且隔著閘極電極33，藉由雜質植入，熱擴散來自我整合地形成基極給電連接領域51。而且，在比基極給電連接領域51更淺的領域，隔著閘極電極33，藉由雜質植入，熱擴散來自我整合地形成基極領域30。同樣隔著閘極電極33，藉由雜質植入，熱擴散來自我整合地形成射極給電層29。在其連接的位置形成有基極給電層36。而且，而且，在隔著場氧化膜37而與本領域相反的側形成有集極給電層31。 Selecting on the surface of the semiconductor substrate having the N-type drift layer 35 The field oxide film 37, the gate oxide film 34, the gate electrode 33, and the gate electrode 33 are selectively interposed by impurity implantation, and thermal diffusion is formed integrally from the base to form the base connection region 51. Moreover, in the field shallower than the base power connection field 51, the thermal diffusion from the integrated formation of the base region 30 is by thermal implantation through the gate electrode 33. Also via the gate electrode 33, the thermal diffusion from the integrated formation of the emitter supply layer 29 is achieved by impurity implantation. A base power supply layer 36 is formed at a position where it is connected. Further, a collector power supply layer 31 is formed on the side opposite to the field in the field oxide film 37.
而且，在基極給電層36是經過基極柱塞(plug)39而形成有基極電極40，在射極給電層29是經過射極柱塞41而形成有射極電極42，而且，在集極給電層31是經過集極柱塞43而形成有集極電極44，顯示適用本發明的橫型雙極電晶體。 Further, in the base power supply layer 36, a base electrode 40 is formed through a base plug 39, and in the emitter power supply layer 29, an emitter electrode 42 is formed through an emitter plug 41, and The collector supply layer 31 is formed with a collector electrode 44 via a collector plug 43, and shows a lateral bipolar transistor to which the present invention is applied.
在此，藉由2次的雜質植入來形成基極，藉此相對於實施例1的構造，形成濃度濃，基極寬度短的基極領域30的點具有特徴。 Here, the base is formed by two times of impurity implantation, whereby the point of the base region 30 having a rich concentration and a short base width is formed with respect to the structure of the first embodiment.
圖12是以製程模擬作成之適用本發明的橫型雙極電晶體剖面構造。在此，基極連接領域51是對於閘極電極33自我整合地以加速能量300keV，雜質濃度1.5E13atom/cm2來將硼植入，熱擴散而形成。並且，基極領域30是對於閘極電極33自我整合地以加速能量30keV，雜質濃度1E13atom/cm2來將硼傾斜植入，熱擴散而形成。 Figure 12 is a cross-sectional view of a transverse bipolar transistor to which the present invention is applied in a process simulation. Here, the base connection region 51 is formed by self-integrating the gate electrode 33 with an acceleration energy of 300 keV and an impurity concentration of 1.5E13 atom/cm 2 to implant boron and thermally diffuse. Further, the base region 30 is formed by self-integrating the gate electrode 33 with an acceleration energy of 30 keV and an impurity concentration of 1E13 atom/cm 2 to obliquely implant boron and thermally diffuse.
並且，射極領域29是對於閘極電極33自我整合地以60keV，雜質濃度2E15atom/cm2來將砷植入形成。算出形成有NPN接合的表面附近，B-B‘部位的雜質濃度分布者為圖13。本圖表是在縱軸取雜質濃度(/cm3)，在橫軸取距離(um)，可確認被調整成以依射極，基極，集極的順序濃度降低，且基極長約100nm的NPN雙極電晶體存在的點。 Further, the emitter region 29 is formed by implanting arsenic at a bonding concentration of 2E15 atoms/cm 2 at a bonding temperature of the gate electrode 33 at a self-integration of 60 keV. The distribution of the impurity concentration in the vicinity of the surface where the NPN bonding was formed and the BB' portion was calculated as FIG. In this graph, the impurity concentration (/cm 3 ) is taken on the vertical axis and the distance (um) is taken on the horizontal axis. It can be confirmed that the concentration is adjusted in the order of the emitter, the base, and the collector, and the base length is about 100 nm. The point at which the NPN bipolar transistor exists.
以裝置模擬計算此雙極電晶體性能之處，在hfe=41，確認相對於實施例1以高的放大率動作的點。圖14是Vc=1V，Vb上昇動作時的電子電流輪廓，可確認電子從射極往集極流動，雙極放大動作的點。 At the point where the performance of the bipolar transistor was calculated by the device simulation, at hfe = 41, the point at which the operation was performed at a high magnification with respect to Example 1 was confirmed. Fig. 14 is an electron current profile when Vc = 1 V and Vb is raised, and it is possible to confirm the point at which electrons flow from the emitter to the collector and the bipolar amplification operation.
圖15是表示本發明的第4實施例的橫型雙極電晶體的製造工程的製程流程圖。 Fig. 15 is a flowchart showing the process of manufacturing a lateral bipolar transistor according to a fourth embodiment of the present invention.
首先，如圖15(a)的(a)所示般，在具有N型漂移層35的半導體基板表面上使閘極氧化膜34，閘極電極33圖案化，(b)對於閘極電極33自我整合地植入形成P型基極給電連接層的雜質硼48。(c)藉由施加熱負荷，形成P型基極給電連接層51。(d)對於閘極電極33自我整合地植入形成P型基極層的雜質硼48。在此也有時對於垂直線傾斜數十度植入使基極長最適化。(e)藉由施加熱負荷，形成P型基極層30。(f)對於閘極電極33自我整合地植入形成N型射極層及N型集極層 的雜質砷49。(g)植入形成P型基極層的雜質氟化硼50。(h)施加熱負荷後，形成柱塞．電極，完成具有基極電極40，射極電極42，集極領域44的橫型雙極電晶體。 First, as shown in (a) of FIG. 15 , the gate oxide film 34 and the gate electrode 33 are patterned on the surface of the semiconductor substrate having the N-type drift layer 35, and (b) for the gate electrode 33 The impurity boron 48 forming the P-type base to the electrical connection layer is self-integrated. (c) A P-type base is provided to the electrical connection layer 51 by applying a heat load. (d) The impurity boron 48 forming the P-type base layer is self-integrated for the gate electrode 33. Here too, it is sometimes necessary to tilt the vertical line by several tens of degrees to optimize the base length. (e) A P-type base layer 30 is formed by applying a heat load. (f) Self-integration implantation of the gate electrode 33 to form an N-type emitter layer and an N-type collector layer The impurity is arsenic 49. (g) implanting an impurity boron fluoride 50 forming a P-type base layer. (h) After applying a heat load, a plunger is formed. The electrode completes a lateral bipolar transistor having a base electrode 40, an emitter electrode 42, and a collector region 44.
圖16是表示本發明的第3實施例的橫型雙極電晶體的元件構造的剖面圖(與圖4，圖10A-A‘同樣位置的剖面圖)。 Fig. 16 is a cross-sectional view showing the structure of an element of a lateral bipolar transistor according to a third embodiment of the present invention (a cross-sectional view at the same position as Fig. 4 and Fig. 10A-A).
相對於前述實施例3的構造，將閘極電極33設為電壓控制端子，以基極電極40，射極電極42，集極電極44，閘極電極33的4端子所構成。 With respect to the structure of the above-described third embodiment, the gate electrode 33 is a voltage control terminal, and the base electrode 40, the emitter electrode 42, the collector electrode 44, and the four terminals of the gate electrode 33 are formed.
圖17是表示以裝置模擬計算之本元件的hfe的閘極電位(Vg)依存性。一旦使閘極電位從0V增加至0.2V，則hfe會增加，從41變化至52的值。在此，觀察使閘極電位變化時的元件剖面，電子濃度輪廓者為圖18。 Fig. 17 is a view showing the dependence of the gate potential (Vg) of hfe of the device which is calculated by the device simulation. Once the gate potential is increased from 0V to 0.2V, hfe will increase from 41 to 52. Here, the cross section of the element when the gate potential is changed is observed, and the electron concentration profile is shown in FIG.
並且，在C-C‘剖面之電子濃度與深度的相關是如圖19般。藉由閘極電位上昇，基極領域的電子濃度會上昇，這表示使閘極電位所製作的電場從射極往基極的電子注入效率提升的點。隨之，往集極的電子注入效率也提升，可想像hfe上昇。一旦使閘極電位上昇至0.2V以上，則如由圖17所知般，雖hfe更上昇，但基極領域成為反轉層，集極-射極間洩漏，喪失電晶體的控制性。 Moreover, the correlation between the electron concentration and the depth in the C-C' profile is as shown in FIG. As the gate potential rises, the electron concentration in the base region rises, which indicates the point at which the electron injection efficiency of the gate potential is increased from the emitter to the base. As a result, the efficiency of electron injection into the concentrator is also improved, and it is conceivable that hfe rises. When the gate potential is raised to 0.2 V or more, as is known from FIG. 17, although the hfe is further increased, the base region becomes an inversion layer, and the collector-emitter leaks, and the controllability of the transistor is lost.
以上，藉由追加閘極端子，可控制hfe，藉由 與圖20那樣的反饋電路組合，可取得抑制製造偏差之安定的增益。 Above, by adding a gate terminal, hfe can be controlled by In combination with the feedback circuit as shown in Fig. 20, it is possible to obtain a stable gain that suppresses manufacturing variations.
13‧‧‧埋入氧化膜 13‧‧‧ buried oxide film
29‧‧‧N型射極給電層 29‧‧‧N type emitter power supply layer
30‧‧‧P型基極層 30‧‧‧P type base layer
31‧‧‧N型集極給電層 31‧‧‧N type collector power supply layer
32‧‧‧元件分離領域 32‧‧‧Parts of component separation
33‧‧‧閘極電極 33‧‧‧gate electrode
34‧‧‧閘極氧化膜 34‧‧‧Gate oxide film
35‧‧‧N型集極漂移層 35‧‧‧N-type collector drift layer
36‧‧‧P型基極給電層 36‧‧‧P type base power supply layer
37‧‧‧場氧化膜 37‧‧‧Field oxide film
38‧‧‧層間絕緣膜 38‧‧‧Interlayer insulating film
39‧‧‧基極柱塞 39‧‧‧Base plunger
40‧‧‧基極電極 40‧‧‧ base electrode
41‧‧‧射極柱塞 41‧‧ ‧ emitter plunger
42‧‧‧射極電極 42‧‧ ‧ emitter electrode
43‧‧‧集極柱塞 43‧‧‧ Collector Plunger
44‧‧‧集極電極 44‧‧‧ Collector electrode
45‧‧‧NPN雙極電晶體形成領域 45‧‧‧NPN bipolar transistor formation field
51‧‧‧P型基極給電連接領域 51‧‧‧P type base power supply connection field
53‧‧‧閘極柱塞 53‧‧‧Gate Plunger
54‧‧‧閘極電極 54‧‧‧gate electrode
Claims (12)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013156250A JP2015026751A (en) | 2013-07-29 | 2013-07-29 | Lateral bipolar transistor and method for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201517263A true TW201517263A (en) | 2015-05-01 |
Family
ID=52389763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103121352A TW201517263A (en) | 2013-07-29 | 2014-06-20 | Horizontal bipolar crystal crystal and manufacturing method thereof |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20150028385A1 (en) |
| JP (1) | JP2015026751A (en) |
| KR (1) | KR20150014360A (en) |
| TW (1) | TW201517263A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11978733B2 (en) | 2021-08-05 | 2024-05-07 | Globalfoundries Singapore Pte. Ltd. | High-voltage electrostatic discharge devices |
| US11942472B2 (en) | 2021-09-15 | 2024-03-26 | Globalfoundries Singapore Pte. Ltd. | High-voltage electrostatic discharge devices |
| US11990466B2 (en) * | 2021-10-14 | 2024-05-21 | Globalfoundries Singapore Pte. Ltd. | High voltage electrostatic devices |
| CN115911117B (en) * | 2023-02-22 | 2023-06-06 | 微龛(广州)半导体有限公司 | Bipolar transistor structure and manufacturing method thereof |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4319932A (en) * | 1980-03-24 | 1982-03-16 | International Business Machines Corporation | Method of making high performance bipolar transistor with polysilicon base contacts |
| US5294558A (en) * | 1993-06-01 | 1994-03-15 | International Business Machines Corporation | Method of making double-self-aligned bipolar transistor structure |
| US5455188A (en) * | 1995-01-31 | 1995-10-03 | United Microelectronics Corp. | Process for fabricating a lateral bipolar junction transistor |
| US6191453B1 (en) * | 1999-12-13 | 2001-02-20 | Philips Electronics North America Corporation | Lateral insulated-gate bipolar transistor (LIGBT) device in silicon-on-insulator (SOI) technology |
| JP5261927B2 (en) * | 2006-12-11 | 2013-08-14 | パナソニック株式会社 | Semiconductor device |
| US7968936B2 (en) * | 2007-12-31 | 2011-06-28 | Texas Instruments Incorporated | Quasi-vertical gated NPN-PNP ESD protection device |
| JP5272410B2 (en) * | 2008-01-11 | 2013-08-28 | 富士電機株式会社 | Semiconductor device and manufacturing method thereof |
| US8415712B2 (en) * | 2009-12-29 | 2013-04-09 | Cambridge Semiconductor Limited | Lateral insulated gate bipolar transistor (LIGBT) |
| US8253164B2 (en) * | 2010-12-23 | 2012-08-28 | Force Mos Technology Co., Ltd. | Fast switching lateral insulated gate bipolar transistor (LIGBT) with trenched contacts |
| US8735937B2 (en) * | 2012-05-31 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fully isolated LIGBT and methods for forming the same |
| US9076837B2 (en) * | 2012-07-06 | 2015-07-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage |
| US8912569B2 (en) * | 2012-07-27 | 2014-12-16 | Freescale Semiconductor, Inc. | Hybrid transistor |
-
2013
- 2013-07-29 JP JP2013156250A patent/JP2015026751A/en not_active Abandoned
-
2014
- 2014-06-13 KR KR1020140071961A patent/KR20150014360A/en not_active Ceased
- 2014-06-20 TW TW103121352A patent/TW201517263A/en unknown
- 2014-07-29 US US14/445,576 patent/US20150028385A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| US20150028385A1 (en) | 2015-01-29 |
| KR20150014360A (en) | 2015-02-06 |
| JP2015026751A (en) | 2015-02-05 |
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