TW201516611A - Power supply circuit for central processing unit - Google Patents
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Abstract
Description
本發明係關於一種CPU供電電路。The present invention relates to a CPU power supply circuit.
目前,電腦主機板上透過設置多相供電電路,如兩相供電電路來給CPU提供電壓,然而,該等多相供電電路在電腦主機板正常工作狀態下均工作,在電腦主機板待機狀態下僅有一相供電電路工作,由於在電腦處於不同狀態時給CPU供電的供電電路不同,這將使得CPU接收到的電壓不穩定,可能造成CPU損壞。At present, the computer motherboard provides a multi-phase power supply circuit, such as a two-phase power supply circuit, to supply voltage to the CPU. However, the multi-phase power supply circuit works under normal working conditions of the computer motherboard, and is in a standby state of the computer motherboard. Only one phase power supply circuit works. Because the power supply circuit that supplies power to the CPU is different when the computer is in different states, this will make the voltage received by the CPU unstable and may cause CPU damage.
有鑒於此,有必要提供一種能夠為CPU提供穩定電壓的CPU供電電路,以防止CPU由於電壓不穩定而損壞。In view of this, it is necessary to provide a CPU power supply circuit capable of providing a stable voltage to the CPU to prevent the CPU from being damaged due to voltage instability.
一種CPU供電電路,包括一比較電路、一第一開關電路、一第二開關電路、一第三開關電路、一第一補償電路、一第二補償電路、一脈寬調製控制器、一連接該脈寬調製控制器第一輸出引腳的第一相供電電路及一連接該脈寬調製控制器第二輸出引腳的第二相供電電路,該比較電路包括第一及第二電阻以及一比較器,該比較器的同相輸入端透過該第一電阻連接於一電源,該比較器的同相輸入端還透過該第二電阻接地,該比較器的反相輸入端連接一參考電壓,該比較器的輸出端連接該第一及第三開關電路以控制該第一及第三開關電路的通斷,該第二開關電路與該第三開關電路連接,該第三開關電路控制第二開關電路的通斷;該第一電阻為一熱敏電阻,設置於該第二相供電電路的電感附近;當該電腦主機板正常工作時,該第一及第二相供電電路均工作,該比較器根據其同相輸入端的電壓輸出一第一控制訊號給該第一及第三開關電路,該第一及第三開關電路導通,進而該第三開關電路控制該第二開關電路截止,該第一補償電路透過該第一開關電路為該脈寬調製控制器提供補償訊號,以使脈寬調製控制器調整輸出給該第一及第二相供電電路的脈衝訊號,以提供穩定的電壓給該CPU;當該電腦主機板待機時,該第一相供電電路工作而第二相供電電路不工作,該比較器根據其同相輸入端的電壓輸出一第二控制訊號給該第一及第三開關電路,該第一及第三開關電路截止,進而該第三開關電路控制該第二開關電路導通,該第二補償電路透過該第二開關電路為該脈寬調製控制器提供補償訊號,以使脈寬調製控制器調整輸出給該第一相供電電路的脈衝訊號,以提供穩定的電壓給該CPU。A CPU power supply circuit includes a comparison circuit, a first switch circuit, a second switch circuit, a third switch circuit, a first compensation circuit, a second compensation circuit, a pulse width modulation controller, and a connection a first phase power supply circuit of the first output pin of the pulse width modulation controller and a second phase power supply circuit connected to the second output pin of the pulse width modulation controller, the comparison circuit including first and second resistors and a comparison The non-inverting input terminal of the comparator is connected to a power source through the first resistor, the non-inverting input terminal of the comparator is also grounded through the second resistor, and the inverting input terminal of the comparator is connected to a reference voltage, the comparator The output end is connected to the first and third switch circuits to control the on and off of the first and third switch circuits, the second switch circuit is connected to the third switch circuit, and the third switch circuit controls the second switch circuit The first resistor is a thermistor disposed near the inductor of the second phase power supply circuit; when the computer motherboard is working normally, the first and second phase power supply circuits are all working, The comparator outputs a first control signal to the first and third switch circuits according to the voltage of the non-inverting input terminal, the first and third switch circuits are turned on, and the third switch circuit controls the second switch circuit to be turned off. a compensation circuit provides a compensation signal to the pulse width modulation controller through the first switching circuit, so that the pulse width modulation controller adjusts the pulse signals outputted to the first and second phase power supply circuits to provide a stable voltage to the CPU; when the computer motherboard is in standby, the first phase power supply circuit operates and the second phase power supply circuit does not work, the comparator outputs a second control signal to the first and third switch circuits according to the voltage of the non-inverting input terminal thereof The first and third switch circuits are turned off, and the third switch circuit controls the second switch circuit to be turned on, and the second compensation circuit provides a compensation signal to the pulse width modulation controller through the second switch circuit to enable the pulse The wide modulation controller adjusts the pulse signal output to the first phase power supply circuit to provide a stable voltage to the CPU.
該CPU供電電路在該電腦主機板處於工作狀態時透過該第一補償電路提供補償訊號以提供穩定電壓給CPU及在該電腦主機板處於待機狀態時透過該第二補償電路提供補償訊號以提供穩定電壓給CPU。該CPU供電電路為該CPU提供穩定的電壓,從而防止CPU由於電壓不穩定而損壞。The CPU power supply circuit provides a compensation signal through the first compensation circuit to provide a stable voltage to the CPU when the computer motherboard is in an operating state, and provides a compensation signal through the second compensation circuit to provide stability when the computer motherboard is in a standby state. Voltage is given to the CPU. The CPU power supply circuit provides a stable voltage to the CPU, thereby preventing the CPU from being damaged due to voltage instability.
100‧‧‧CPU供電電路100‧‧‧CPU power supply circuit
10‧‧‧比較電路10‧‧‧Comparative circuit
20‧‧‧第一開關電路20‧‧‧First switch circuit
30‧‧‧第二開關電路30‧‧‧Second switch circuit
40‧‧‧第三開關電路40‧‧‧ Third switch circuit
50‧‧‧第一補償電路50‧‧‧First compensation circuit
60‧‧‧第二補償電路60‧‧‧Second compensation circuit
70‧‧‧PWM控制器70‧‧‧PWM controller
80‧‧‧第一相供電電路80‧‧‧First phase power supply circuit
90‧‧‧第二相供電電路90‧‧‧Second phase power supply circuit
200‧‧‧CPU200‧‧‧CPU
R0-R8‧‧‧電阻R0-R8‧‧‧ resistance
C3-C8‧‧‧電容C3-C8‧‧‧ capacitor
U1‧‧‧比較器U1‧‧‧ comparator
Q1-Q5‧‧‧場效應電晶體Q1-Q5‧‧‧ Field Effect Transistor
圖1是本發明CPU供電電路的較佳實施方式的電路圖。1 is a circuit diagram of a preferred embodiment of a CPU power supply circuit of the present invention.
請參考圖1,本發明CPU供電電路100設置在一電腦主機板上以為一中央處理器(central processing unit,CPU)200提供電壓,本實施方式中以兩相供電電路為例進行說明。該CPU供電電路100的較佳實施方式包括一比較電路10、一第一開關電路20、一第二開關電路30、一第三開關電路40、一第一補償電路50、一第二補償電路60、一脈寬調製(pulse width modulation,PWM)控制器70、一第一相供電電路80及一第二相供電電路90。該比較電路10設置於該第二相供電電路90附近。Referring to FIG. 1, the CPU power supply circuit 100 of the present invention is disposed on a computer motherboard to provide a voltage for a central processing unit (CPU) 200. In this embodiment, a two-phase power supply circuit is taken as an example for description. The preferred embodiment of the CPU power supply circuit 100 includes a comparison circuit 10, a first switch circuit 20, a second switch circuit 30, a third switch circuit 40, a first compensation circuit 50, and a second compensation circuit 60. A pulse width modulation (PWM) controller 70, a first phase power supply circuit 80, and a second phase power supply circuit 90. The comparison circuit 10 is disposed adjacent to the second phase power supply circuit 90.
當該電腦主機板正常工作時,即該第一及第二相供電電路80及90均工作,此時,該比較電路10輸出一第一控制訊號給該第一及第三開關電路20及40,該第一及第三開關電路20及40導通,該第二開關電路30截止,該第一補償電路50透過該第一開關電路20為該PWM控制器70提供補償訊號,以使PWM控制器70調整輸出給該第一及第二相供電電路80及90的脈衝訊號,以提供穩定的電壓給該CPU 200。當該電腦主機板待機時,即該第一相供電電路80工作而第二相供電電路90不工作,此時,該比較電路10輸出一第二控制訊號給該第一及第三開關電路20及40,該第一及第三開關電路20及40截止,該第二開關電路30導通,該第二補償電路60透過該第二開關電路30為該PWM控制器70提供補償訊號,以使PWM控制器70調整輸出給該第一相供電電路80的脈衝訊號,以提供穩定的電壓給該CPU 200。其中,該第一及第二相供電電路80及90的電子元件連接關係及工作原理為習知技術,在此不再贅述。When the computer motherboard is working normally, that is, the first and second phase power supply circuits 80 and 90 are both working, at this time, the comparison circuit 10 outputs a first control signal to the first and third switch circuits 20 and 40. The first and third switch circuits 20 and 40 are turned on, and the second switch circuit 30 is turned off. The first compensation circuit 50 provides a compensation signal to the PWM controller 70 through the first switch circuit 20 to enable the PWM controller. The pulse signals output to the first and second phase power supply circuits 80 and 90 are adjusted to provide a stable voltage to the CPU 200. When the computer motherboard is in standby, that is, the first phase power supply circuit 80 is in operation and the second phase power supply circuit 90 is inactive, the comparison circuit 10 outputs a second control signal to the first and third switch circuits 20 And the first and third switch circuits 20 and 40 are turned off, the second switch circuit 30 is turned on, and the second compensation circuit 60 provides the PWM controller 70 with a compensation signal through the second switch circuit 30 to enable the PWM. The controller 70 adjusts the pulse signal output to the first phase power supply circuit 80 to provide a stable voltage to the CPU 200. The electronic component connection relationship and the working principle of the first and second phase power supply circuits 80 and 90 are conventional technologies, and are not described herein again.
該比較電路10包括電阻R1、R2及一比較器U1。該比較器U1的同相輸入端透過該電阻R1與一電源Vcc連接,該比較器U1的同相輸入端還透過該電阻R2接地,該比較器U1的反相輸入端連接一參考電壓Vcc1,該比較器的電源端連接於該電源Vcc,該比較器U1的接地端接地。該比較器U1的輸出端連接該第一及第三開關電路20及40。本實施方式中,設定該電源Vcc經該電阻R1、R2分壓之後的電壓略低於該參考電壓Vcc1,即該比較器U1同相輸入端的電壓略小於該比較器U1的反相輸入端的電壓。The comparison circuit 10 includes resistors R1, R2 and a comparator U1. The non-inverting input terminal of the comparator U1 is connected to a power source Vcc through the resistor R1. The non-inverting input terminal of the comparator U1 is also grounded through the resistor R2. The inverting input terminal of the comparator U1 is connected to a reference voltage Vcc1. The power terminal of the device is connected to the power source Vcc, and the ground terminal of the comparator U1 is grounded. The output of the comparator U1 is connected to the first and third switching circuits 20 and 40. In this embodiment, the voltage after the power supply Vcc is divided by the resistors R1 and R2 is slightly lower than the reference voltage Vcc1, that is, the voltage of the non-inverting input terminal of the comparator U1 is slightly smaller than the voltage of the inverting input terminal of the comparator U1.
該第一開關電路20包括兩電子開關(在本實施方式中為N溝道場效應電晶體Q1及Q2)。該場效應電晶體Q1的閘極連接該場效應電晶體Q2的閘極及該比較器U1的輸出端,該場效應電晶體Q1的源極連接該PWM控制器70的輸入輸出(input/output,I/O)引腳COMP,該場效應電晶體Q1的汲極連接該第一補償電路50。該場效應電晶體Q2的源極連接該PWM控制器70的I/O引腳Vout,該場效應電晶體Q2的汲極連接該第一補償電路50。The first switching circuit 20 includes two electronic switches (N-channel field effect transistors Q1 and Q2 in this embodiment). The gate of the field effect transistor Q1 is connected to the gate of the field effect transistor Q2 and the output end of the comparator U1. The source of the field effect transistor Q1 is connected to the input and output of the PWM controller 70 (input/output) , I/O) pin COMP, the drain of the field effect transistor Q1 is connected to the first compensation circuit 50. The source of the field effect transistor Q2 is connected to the I/O pin Vout of the PWM controller 70, and the drain of the field effect transistor Q2 is connected to the first compensation circuit 50.
該PWM控制器70的輸出引腳PHASE1經該第一相供電電路80連接該CPU 200,該PWM控制器70的輸出引腳PHASE2經該第二相供電電路90連接該第一相供電電路80及該CPU 200。The output pin PHASE1 of the PWM controller 70 is connected to the CPU 200 via the first phase power supply circuit 80. The output pin PHASE2 of the PWM controller 70 is connected to the first phase power supply circuit 80 via the second phase power supply circuit 90. The CPU 200.
該第二開關電路30包括兩電子開關(在本實施方式中為N溝道場效應電晶體Q3及Q4)。該場效應電晶體Q3的閘極連接該場效應電晶體Q4的閘極及該第三開關電路40,該場效應電晶體Q3的源極連接該PWM控制器70的I/O引腳COMP,該場效應電晶體Q3的汲極連接該第二補償電路60。該場效應電晶體Q4的源極連接該PWM控制器70的I/O引腳Vout,該場效應電晶體Q4的汲極連接該第二補償電路60。The second switching circuit 30 includes two electronic switches (N-channel field effect transistors Q3 and Q4 in this embodiment). The gate of the field effect transistor Q3 is connected to the gate of the field effect transistor Q4 and the third switch circuit 40. The source of the field effect transistor Q3 is connected to the I/O pin COMP of the PWM controller 70. The drain of the field effect transistor Q3 is connected to the second compensation circuit 60. The source of the field effect transistor Q4 is coupled to the I/O pin Vout of the PWM controller 70, and the drain of the field effect transistor Q4 is coupled to the second compensation circuit 60.
該第三開關電路40包括一電子開關(在本實施方式中為一N溝道場效應電晶體Q5)及一電阻R0。該場效應電晶體Q5的閘極連接該比較器U1的輸出端,該場效應電晶體Q5的源極接地,其汲極連接該場效應電晶體Q3及Q4的閘極及經該電阻R0連接該電壓源VCC。The third switching circuit 40 includes an electronic switch (in the present embodiment, an N-channel field effect transistor Q5) and a resistor R0. The gate of the field effect transistor Q5 is connected to the output end of the comparator U1, the source of the field effect transistor Q5 is grounded, and the drain of the field effect transistor Q3 is connected to the gate of the field effect transistors Q3 and Q4 and connected via the resistor R0. This voltage source is VCC.
該第一補償電路50包括電阻R3-R5及電容C3-C5。該電容C3的第一端連接該場效應電晶體Q1的汲極,該電容C3的第二端依次經該電阻R3及R4及該電容C5連接該場效應電晶體Q2的汲極,該電容C4的第一端連接該場效應電晶體Q1的汲極,該電容C4的第二端連接於該電阻R3與R4之間的節點。該電阻R5的第一端連接該場效應電晶體Q2的汲極,該電阻R5的第二端連接於該電阻R3與R4之間的節點。該PWM控制器70的回饋引腳FB連接於該電阻R3與R4之間的節點。The first compensation circuit 50 includes resistors R3-R5 and capacitors C3-C5. The first end of the capacitor C3 is connected to the drain of the field effect transistor Q1, and the second end of the capacitor C3 is connected to the drain of the field effect transistor Q2 via the resistors R3 and R4 and the capacitor C5. The capacitor C4 The first end is connected to the drain of the field effect transistor Q1, and the second end of the capacitor C4 is connected to the node between the resistors R3 and R4. The first end of the resistor R5 is connected to the drain of the field effect transistor Q2, and the second end of the resistor R5 is connected to the node between the resistors R3 and R4. The feedback pin FB of the PWM controller 70 is connected to a node between the resistors R3 and R4.
該第二補償電路60包括電阻R6-R8及電容C6-C8。該電容C6的第一端連接該場效應電晶體Q3的汲極,該電容C6的第二端依次經該電阻R6及R7及該電容C8連接該場效應電晶體Q4的汲極,該電容C7的第一端連接該場效應電晶體Q3的汲極,該電容C7的第二端連接於該電阻R6與R7之間的節點。該電阻R8的第一端連接該場效應電晶體Q4的汲極,該電阻R8的第二端連接於該電阻R6與R7之間的節點。該PWM控制器70的回饋引腳FB連接於該電阻R6與R7之間的節點。The second compensation circuit 60 includes resistors R6-R8 and capacitors C6-C8. The first end of the capacitor C6 is connected to the drain of the field effect transistor Q3, and the second end of the capacitor C6 is connected to the drain of the field effect transistor Q4 via the resistors R6 and R7 and the capacitor C8. The capacitor C7 The first end is connected to the drain of the field effect transistor Q3, and the second end of the capacitor C7 is connected to the node between the resistors R6 and R7. The first end of the resistor R8 is connected to the drain of the field effect transistor Q4, and the second end of the resistor R8 is connected to the node between the resistors R6 and R7. The feedback pin FB of the PWM controller 70 is connected to a node between the resistors R6 and R7.
本實施方式中,該電阻R1為一負溫度係數熱敏電阻,當該電阻R1的溫度升高時,該電阻R1的電阻值變小。佈線時,將該電阻R1設置於該第二相供電電路90內的電感的附近。另外,本實施方式中該電阻R6-R8的電阻值與該電阻R3-R5的電阻值不同,該電容C6-C8的電容值與該電容C3-C5的電容值不同,以使該第一及第二補償電路50及60輸出給該PWM控制器70的補償訊號不同。In the present embodiment, the resistor R1 is a negative temperature coefficient thermistor, and when the temperature of the resistor R1 increases, the resistance value of the resistor R1 becomes small. At the time of wiring, the resistor R1 is provided in the vicinity of the inductance in the second phase power supply circuit 90. In addition, in the present embodiment, the resistance values of the resistors R6-R8 are different from the resistance values of the resistors R3-R5, and the capacitance values of the capacitors C6-C8 are different from the capacitance values of the capacitors C3-C5, so that the first The compensation signals outputted to the PWM controller 70 by the second compensation circuits 50 and 60 are different.
使用時,當該電腦主機板正常工作時,該第一及第二相供電電路80及90均工作,該第二相供電電路90內的電感工作並產生熱量,位於該第二相供電電路90內的電感附近的電阻R1溫度變高,電阻值變小,進而使得該比較器U1同相輸入端電壓大於該比較器U1反相輸入端電壓,該比較器U1輸出一高電平訊號,該場效應電晶體Q1、Q2及Q5導通,該場效應電晶體Q3及Q4從該場效應電晶體Q5的汲極接收一低電平訊號而截止,此時該第一補償電路50透過該場效應電晶體Q1及Q2為該PWM控制器70提供補償訊號,以使PWM控制器70根據接收到的補償訊號調整輸出給該第一及第二相供電電路80及90的脈衝訊號的任務循環,並透過控制該第一及第二相供電電路80及90中的兩場效應電晶體的交替導通或截止來使得該第一及第二相供電電路80及90中的電感進行充放電,以此提供穩定的電壓給該CPU 200。In use, when the computer motherboard is working normally, the first and second phase power supply circuits 80 and 90 are both operated, and the inductance in the second phase power supply circuit 90 works and generates heat. The second phase power supply circuit 90 is located. The temperature of the resistor R1 near the inductor becomes higher, and the resistance value becomes smaller, so that the voltage of the non-inverting input terminal of the comparator U1 is greater than the voltage of the inverting input terminal of the comparator U1, and the comparator U1 outputs a high level signal, the field The effect transistors Q1, Q2 and Q5 are turned on, and the field effect transistors Q3 and Q4 receive a low level signal from the drain of the field effect transistor Q5 and are turned off. At this time, the first compensation circuit 50 transmits the field effect electricity. The crystals Q1 and Q2 provide a compensation signal for the PWM controller 70, so that the PWM controller 70 adjusts the task cycle of the pulse signals output to the first and second phase power supply circuits 80 and 90 according to the received compensation signal, and transmits Controlling alternate turn-on or turn-off of the two field effect transistors in the first and second phase power supply circuits 80 and 90 to charge and discharge the inductors in the first and second phase power supply circuits 80 and 90, thereby providing stability Voltage to the CPU 200
當該電腦主機板待機時,該第二相供電電路90不工作,即該PWM控制器70僅輸出脈衝訊號給該第一相供電電路80,而不輸出脈衝訊號給該第二相供電電路90,該第二相供電電路90內的電感溫度恢復常溫,位於該第二相供電電路90附近的電阻R1溫度也恢復常溫,進而使得該比較器U1同相輸入端電壓小於該比較器U1反相輸入端電壓,該比較器的輸出端輸出一低電平訊號,該場效應電晶體Q1、Q2及Q5截止,該場效應電晶體Q3及Q4從該電壓源Vcc接收一高電平訊號而導通,此時該第二補償電路60透過該場效應電晶體Q3及Q4為該PWM控制器70提供補償訊號,以使該PWM控制器70根據接收到的補償訊號調整輸出給該第一相供電電路80的脈衝訊號的任務循環,並透過控制該第一相供電電路80中的兩場效應電晶體的交替導通或截止來使得該第一相供電電路80中的電感進行充放電,以此提供穩定的電壓給該CPU 200,從而使得該CPU200在電腦主機板正常工作或者待機時均接收到穩定的電壓,避免了CPU200由於電壓不穩定而損壞。When the computer motherboard is in standby, the second phase power supply circuit 90 does not work, that is, the PWM controller 70 only outputs a pulse signal to the first phase power supply circuit 80, and does not output a pulse signal to the second phase power supply circuit 90. The temperature of the inductor in the second phase power supply circuit 90 returns to normal temperature, and the temperature of the resistor R1 located near the second phase power supply circuit 90 also returns to normal temperature, so that the voltage of the non-inverting input terminal of the comparator U1 is smaller than the inverting input of the comparator U1. The output voltage of the comparator outputs a low level signal, and the field effect transistors Q1, Q2 and Q5 are turned off, and the field effect transistors Q3 and Q4 receive a high level signal from the voltage source Vcc to be turned on. At this time, the second compensation circuit 60 provides a compensation signal to the PWM controller 70 through the field effect transistors Q3 and Q4, so that the PWM controller 70 adjusts the output to the first phase power supply circuit 80 according to the received compensation signal. The task of the pulse signal is cycled, and the inductance of the first phase power supply circuit 80 is charged and discharged by controlling the alternate turn-on or turn-off of the two field effect transistors in the first phase power supply circuit 80. A predetermined voltage to the CPU 200, so that the CPU200 work in both or computer motherboard to receive stable standby voltage, voltage instability due CPU200 avoid damage.
本方案發明電路具有兩個補償電路,在電腦處於不同狀態時採用不同的補償電路,該CPU供電電路100在該電腦主機板處於工作狀態時透過該第一補償電路50提供補償訊號以提供穩定電壓給CPU 200及在該電腦主機板處於待機狀態時透過該第二補償電路60提供補償訊號以提供穩定電壓給CPU 200。該CPU供電電路100在節省電能的同時保證CPU 200的穩定電壓從而防止CPU 200由於電壓不穩定而損壞。The circuit of the present invention has two compensation circuits, and different compensation circuits are used when the computer is in different states. The CPU power supply circuit 100 provides a compensation signal through the first compensation circuit 50 to provide a stable voltage when the computer motherboard is in an active state. The CPU 200 is provided with a compensation signal through the second compensation circuit 60 to provide a stable voltage to the CPU 200 when the computer motherboard is in the standby state. The CPU power supply circuit 100 ensures a stable voltage of the CPU 200 while saving power to prevent the CPU 200 from being damaged due to voltage instability.
綜上所述,本發明確已符合發明專利的要件,爰依法提出專利申請。惟,以上所述者僅為本發明的較佳實施方式,本發明的範圍並不以上述實施方式為限,舉凡熟悉本案技藝的人士援依本發明的精神所作的等效修飾或變化,皆應涵蓋於以下申請專利範圍內。In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make equivalent modifications or variations in accordance with the spirit of the present invention. It should be covered by the following patent application.
無no
100‧‧‧CPU供電電路 100‧‧‧CPU power supply circuit
10‧‧‧比較電路 10‧‧‧Comparative circuit
20‧‧‧第一開關電路 20‧‧‧First switch circuit
30‧‧‧第二開關電路 30‧‧‧Second switch circuit
40‧‧‧第三開關電路 40‧‧‧ Third switch circuit
50‧‧‧第一補償電路 50‧‧‧First compensation circuit
60‧‧‧第二補償電路 60‧‧‧Second compensation circuit
70‧‧‧PWM控制器 70‧‧‧PWM controller
80‧‧‧第一相供電電路 80‧‧‧First phase power supply circuit
90‧‧‧第二相供電電路 90‧‧‧Second phase power supply circuit
200‧‧‧CPU 200‧‧‧CPU
R0-R8‧‧‧電阻 R0-R8‧‧‧ resistance
C3-C8‧‧‧電容 C3-C8‧‧‧ capacitor
U1‧‧‧比較器 U1‧‧‧ comparator
Q1-Q5‧‧‧場效應電晶體 Q1-Q5‧‧‧ Field Effect Transistor
Claims (10)
The CPU power supply circuit of claim 9, wherein the first to fifth electronic switches are N-channel field effect transistors, and the first to third ends of the first to fifth electronic switches are respectively The gate, source and drain of the field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102126545A TW201516611A (en) | 2013-07-24 | 2013-07-24 | Power supply circuit for central processing unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102126545A TW201516611A (en) | 2013-07-24 | 2013-07-24 | Power supply circuit for central processing unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201516611A true TW201516611A (en) | 2015-05-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW102126545A TW201516611A (en) | 2013-07-24 | 2013-07-24 | Power supply circuit for central processing unit |
Country Status (1)
| Country | Link |
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| TW (1) | TW201516611A (en) |
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2013
- 2013-07-24 TW TW102126545A patent/TW201516611A/en unknown
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