TW201503159A - Memory cell array - Google Patents

Abstract

A memory cell array includes a bit line, a complementary bit line, a first operation voltage supply circuit, a second operation voltage supply circuit, a first memory cell and a second memory cell. The first operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a first operation voltage. The second operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a second operation voltage. The first memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the first operation voltage. The second memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the second operation voltage. The first memory cell and the second memory cell are located in a same column in the memory cell array.

Description

Memory cell array

The present invention relates to the field of memory technologies, and more particularly to a memory cell array.

A general memory device is mainly composed of a memory cell array and an operating voltage supply circuit. In the above main components, all the memory cells of the same column in the memory cell array are electrically coupled to the corresponding write word lines, and all the memory cells of the same row in the memory cell array are electrically coupled correspondingly. Bit line. The operating voltage supply circuit is used to supply the operating voltages of all the cells of the same row in the memory cell array.

However, since all the memory cells of the same row in the memory cell array are electrically coupled to each other, when the operating voltage is supplied to all the memory cells of the same row in the memory cell array, the bits of the same row in the memory cell array are The load on the line increases, so there is a voltage drop (IR-Drop), which in turn causes the memory noise (Static Noise Margin, SNM) of the memory cell to be inferior during writing.

The invention provides a memory cell array which can improve the anti-noise ability of a memory cell.

The memory cell array provided by the present invention includes bit lines and mutual The complement bit line, the first working voltage supply circuit, the second working voltage supply circuit, the first memory cell, and the second memory cell. The first working voltage supply circuit is electrically coupled to the bit line and the complementary bit line, and is configured to supply the first working voltage. The second working voltage supply circuit is electrically coupled to the bit line and the complementary bit line, and is configured to supply a second operating voltage. The first memory cell is electrically coupled to the bit line and the complementary bit line, and is configured to receive the first operating voltage. The second memory is electrically coupled to the bit line and the complementary bit line, and is configured to receive a second operating voltage. Wherein, the second memory cell and the first memory cell are located in the same row in the memory cell array.

The present invention solves the aforementioned problems in that all memory cells in the same row in the memory cell array are divided into at least two groups of memory cells. One set of memory cells is configured to receive an operating voltage supplied by one of at least two sets of operating voltage supply circuits in the array of memory cells. Another set of memory cells is for receiving an operating voltage supplied by the other of the at least two sets of operating voltage supply circuits in the array of memory cells. Therefore, after adopting the circuit structure of the memory cell array of the present invention, not only the influence of the voltage drop on the memory cell can be improved, but also the anti-noise capability of the memory cell during the writing period can be improved.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

100‧‧‧ memory cell array

101, 105, 201, 301, 401, 501, 601, 701 ‧ ‧ working voltage supply circuit

103, 107, 203, 303, 403, 503, 603, 703‧‧‧ memory cells

111, 113‧‧‧ Array gap

BL‧‧‧ bit line

BLB‧‧‧complementary bit line

WWL‧‧‧Write word line

RBL‧‧‧Read bit line

RWL‧‧‧Read word line

V1, V2, Vcell‧‧‧ working voltage

P1, P2, P3, P4, P5, P6, P7‧‧‧P type transistors

N1, N2, N3, N4, N5, N6, N7, N8, N9, N10‧‧‧N type transistors

INV1, INV2‧‧‧ inverter

VDD, VSS‧‧‧ power supply voltage

502‧‧‧ bias supply circuit

Vbias‧‧‧ bias

1 is a schematic diagram of a memory cell array in accordance with an embodiment of the present invention.

2 is a circuit diagram of an operating voltage supply circuit and a memory cell in accordance with an embodiment of the invention.

3 is a diagram showing an operating voltage supply circuit according to another embodiment of the present invention. Schematic diagram of the circuit with the memory cell.

4 is a circuit diagram of an operating voltage supply circuit and a memory cell in accordance with another embodiment of the present invention.

FIG. 5 is a schematic circuit diagram of an operating voltage supply circuit and a memory cell according to another embodiment of the present invention.

6 is a circuit diagram of an operating voltage supply circuit and a memory cell in accordance with another embodiment of the present invention.

FIG. 7 is a circuit diagram showing an operating voltage supply circuit and a memory cell according to another embodiment of the present invention.

1 is a schematic diagram of a memory cell array in accordance with an embodiment of the present invention. Referring to FIG. 1, the memory cell array 100 is mainly composed of at least one bit line, at least one complementary bit line, at least two sets of operating voltage supply circuits, at least two sets of memory cells, and at least one write word line. In each component of the memory cell array 100, a set of operating voltage supply circuits (shown by reference numeral 101) and a memory cell (shown by reference numeral 103) are electrically coupled to the bit line (shown by reference numeral BL). The memory cell 103 is for receiving the operating voltage V1 supplied from the operating voltage supply circuit 101, and the complementary bit line (as indicated by reference numeral BLB). The other set of operating voltage supply circuits (shown by reference numeral 105) and the memory cells (shown by reference numeral 107) are electrically coupled to the bit line BL and the complementary bit line BLB, and the memory cell 107 is used for receiving. The operating voltage V2 supplied from the operating voltage supply circuit 105. The memory cell 103 and the memory cell 107 are each electrically coupled to a corresponding write word line (as indicated by reference numeral WWL). In this embodiment, the memory cell 103 and the memory cell 107 are both located in the same row in the memory cell array 100. In addition, in this embodiment, one of the working voltage supply circuits 101 is configured in the memory. The array gaps in the cell array 100 (as indicated by reference numeral 111) and the other set of operating voltage supply circuits 105 are disposed in the array gaps (shown by reference numeral 113) in the memory cell array 100.

The following is a description of one of the operating voltage supply circuits 101 and the memory cells 103. As for the other circuit voltage supply circuit 105 and the internal circuit structure of the memory cell 107 and the internal circuit structure and operation of the operating voltage supply circuit 101 and the memory cell 103 are very similar, in order to simplify the space, the following will not be repeated.

2 is a circuit diagram of an operating voltage supply circuit and a memory cell in accordance with an embodiment of the invention. In FIG. 2, the same reference numerals as those in FIG. 1 are denoted as the same items. Further, reference numeral 201 is denoted as an operating voltage supply circuit, and reference numeral 203 is denoted as a memory cell. Specifically, the operating voltage supply circuit 201 mainly includes two N-type transistors N1 and N2, two P-type transistors P1 and P2, and two inverters INV1 and INV2. One source/drain of the two N-type transistors N1 and N2 is electrically coupled to the power supply voltage VDD, and the other source/drain is electrically coupled to a node to generate the operating voltage Vcell. One source/drain of the P-type transistor P1 is electrically coupled to the node, and the gate is electrically coupled to the gate of the N-type transistor N2. One source/drain of the P-type transistor P2 is electrically coupled to another source/drain of the P-type transistor P1, and the other source/drain is electrically coupled to the power supply voltage VDD, and the gate is electrically coupled. Connect the gate of the N-type transistor N1. The input end of the inverter INV1 is electrically coupled to the bit line BL, and the output end is electrically coupled to the gate of the P-type transistor P2. The input end of the inverter INV2 is electrically coupled to the complementary bit line BLB, and the output end is electrically coupled to the gate of the P-type transistor P1. In this embodiment, the N-type transistors N1 and N2 can be implemented by using a general threshold voltage transistor, a high threshold voltage transistor or a low threshold voltage transistor.

The memory cell 203 mainly includes two P-type transistors P3 and P4 and four N-type transistors N3, N4, N5 and N6. One source/drain of the P-type transistors P3 and P4 is electrically coupled to a node in the operating voltage supply circuit 201 to receive the operating voltage Vcell. One source/drain of the N-type transistor N3 is electrically coupled to another source/drain of the P-type transistor P3, and the other source/drain is electrically coupled to the power supply voltage VSS, and the gate is electrically The gate of the P-type transistor P3 is coupled. One source/drain of the N-type transistor N4 is electrically coupled to another source/drain of the P-type transistor P4, and the other source/drain is electrically coupled to the power supply voltage VSS, and the gate is electrically coupled. Connect the gate of P-type transistor P4. One source/drain of the N-type transistor N5 is electrically coupled to the bit line BL, and the other source/drain is electrically coupled to one source/drain of the N-type transistor N3 and the N-type transistor N4. The gate is electrically connected to the write word line WWL. One source/drain of the N-type transistor N6 is electrically coupled to the complementary bit line BLB, and the other source/drain is electrically coupled to one source/drain of the N-type transistor N4 and the N-type transistor N3. The gate is electrically coupled to the write word line WWL. In this embodiment, the power supply voltage VDD is greater than the operating voltage Vcell and the power supply voltage VSS, and the operating voltage Vcell is greater than the power supply voltage VSS.

In detail, if the N-type transistors N1 and N2 in the operating voltage supply circuit 201 are implemented by a general threshold voltage transistor, when the memory cell 203 enters the data writing period, the memory cell 203 receives about VDD-0.7. The operating voltage value of V. If the N-type transistors N1 and N2 in the working voltage supply circuit 201 are implemented by a high threshold voltage transistor, when the memory cell 203 enters the data writing period, the memory cell 203 receives an operating voltage less than VDD-0.7V. value. If the N-type transistors N1 and N2 in the working voltage supply circuit 201 are implemented by using a low threshold voltage transistor, when the memory cell 203 enters the data writing period, the memory cell 203 receives approximately greater than VDD-0.7V operating voltage value. That is, the operating voltage Vcell received by the memory cell 203 will vary with the different threshold voltage transistors of the N-type transistors N1 and N2.

3 is a circuit diagram of an operating voltage supply circuit and a memory cell in accordance with another embodiment of the present invention. The embodiment shown in FIG. 3 is substantially equivalent to the embodiment shown in FIG. 2, except that the operating voltage supply circuit 201 shown in FIG. 2 is composed of two N-type transistors, two P-type transistors, and The two inverters are composed, and the operating voltage supply circuit 301 shown in FIG. 3 is composed of an N-type transistor, two P-type transistors, and two inverters. Specifically, in each component of the operating voltage supply circuit 301, one source/drain and the gate of the N-type transistor N1 are electrically coupled to the power supply voltage VDD, and the other source/drain is electrically. A node is coupled to generate a working voltage Vcell. One source/drain of the P-type transistor P1 is electrically coupled to the above node. One source/drain of the P-type transistor P2 is electrically coupled to another source/drain of the P-type transistor P1, and the other source/drain is electrically coupled to the power supply voltage VDD. The input end of the inverter INV1 is electrically coupled to the bit line BL, and the output end is electrically coupled to the gate of the P-type transistor P2. The input end of the inverter INV2 is electrically coupled to the complementary bit line BLB, and the output end is electrically coupled to the gate of the P-type transistor P1. In this embodiment, the power supply voltage VDD is greater than the operating voltage Vcell.

As for the memory cell 303, the circuit structure is substantially similar to the memory cell 203 shown in FIG. 2. The memory cell 303 is also composed of two P-type transistors P3 and P4 and four N-type transistors N2, N3, N4 and N5. The circuit coupling relationship and operation are also described in detail in the embodiment shown in FIG. 2, and will not be further described herein. It should be noted that, in this embodiment, the N-type transistor N1 can also be implemented by using a general threshold voltage transistor, a high threshold voltage transistor, or a low threshold voltage transistor.

4 is a circuit diagram of an operating voltage supply circuit and a memory cell in accordance with another embodiment of the present invention. The embodiment shown in FIG. 4 is substantially equivalent to the embodiment shown in FIG. 3, except that the operating voltage supply circuit 301 shown in FIG. 3 is composed of an N-type transistor, two P-type transistors, and two. The inverter is composed of an inverter, and the operating voltage supply circuit 401 shown in FIG. 4 is composed of three P-type transistors and two inverters. Specifically, in each component of the operating voltage supply circuit 401, one source/drain of the P-type transistor P1 is electrically coupled to the power supply voltage VDD, and the other source/drain and the gate are electrically coupled. A node is connected to generate a working voltage Vcell. One source/drain of the P-type transistor P2 is electrically coupled to the above node. One source/drain of the P-type transistor P3 is electrically coupled to another source/drain of the P-type transistor P2, and the other source/drain is electrically coupled to the power supply voltage VDD. The input end of the inverter INV1 is electrically coupled to the bit line BL, and the output end is electrically coupled to the gate of the P-type transistor P3. The input end of the inverter INV2 is electrically coupled to the complementary bit line BLB, and the output end is electrically coupled to the gate of the P-type transistor P2.

As for the memory cell 403, the circuit structure is substantially similar to the memory cell 203 shown in FIG. 2. The memory cell 403 is also composed of two P-type transistors P4 and P5 and four N-type transistors N1, N2, N3 and N4. The coupling and operation between the components are also described in detail in the embodiment shown in FIG. 2, and will not be further described herein. It should be noted that, in this embodiment, the P-type transistor P1 can also be implemented by using a general threshold voltage transistor, a high threshold voltage transistor, or a low threshold voltage transistor. In this embodiment, the power supply voltage VDD is greater than the operating voltage Vcell and the power supply voltage VSS, and the operating voltage Vcell is greater than the power supply voltage VSS.

FIG. 5 is a schematic circuit diagram of an operating voltage supply circuit and a memory cell according to another embodiment of the present invention. In FIG. 5, reference numeral 501 is represented as Operating voltage supply circuit, reference numeral 502 is shown as a bias supply circuit, and reference numeral 503 is shown as a memory cell. The embodiment shown in FIG. 5 differs from the embodiment shown in FIG. 2 in that the operating voltage supply circuit 501 shown in FIG. 5 receives the bias voltage Vbias generated from the bias supply circuit 502 (about 0.8*). The voltage value of VDD is supplied to the memory cell 503 when the memory cell 503 is selected.

Specifically, the operating voltage supply circuit 501 mainly includes four P-type transistors P1, P2, P3, and P4 and two inverters INV1 and INV2. One source/drain of the P-type transistors P1 and P2 is electrically coupled to the bias voltage Vbias, and the other source/drain is electrically coupled to the node in the operating voltage supply circuit 501 to generate the operating voltage Vcell. One source/drain of the P-type transistor P3 is electrically coupled to the above node. One source/drain of the P-type transistor P4 is electrically coupled to another source/drain of the P-type transistor P3, and the other source/drain is electrically coupled to the power supply voltage VDD. The input end of the inverter INV1 is electrically coupled to the bit line BL, and the output end is electrically coupled to the gate of the P-type transistor P4. The input end of the inverter INV2 is electrically coupled to the complementary bit line BLB, and the output end is electrically coupled to the gate of the P-type transistor P3.

The bias supply circuit 502 mainly includes a P-type transistor P5 and three N-type transistors N1, N2 and N3. One source/drain of the P-type transistor P5 is electrically coupled to the power supply voltage VDD, and the other source/drain and the gate are electrically coupled to the node in the bias supply circuit 502 to generate the above bias voltage. Vbias. A source/drain and a gate of the N-type transistor N1 are electrically coupled to nodes in the bias supply circuit 502. One source/drain and the gate of the N-type transistor N2 are electrically coupled to another source/drain of the N-type transistor N1. One source/drain and the gate of the N-type transistor N3 are electrically coupled to another source/drain of the N-type transistor N2, and the other source/drain is electrically coupled to the power supply voltage VSS. The substrates of the N-type transistors N1, N2, and N3 are electrically coupled to the power supply voltage VSS.

As for the memory cell 503, there are mainly two P-type transistors P6 and P7 and six N-type transistors N4, N5, N6, N7, N8 and N9. One of the source/drain electrodes of the P-type transistors P6 and P7 is electrically coupled to a node in the operating voltage supply circuit 501 to receive the operating voltage Vcell. One source/drain of the N-type transistor N4 is electrically coupled to another source/drain of the P-type transistor P6, and the other source/drain is electrically coupled to the power supply voltage VSS, and the gate is electrically The gate of the P-type transistor P6 is coupled. One source/drain of the N-type transistor N5 is electrically coupled to another source/drain of the P-type transistor P7, and the other source/drain is electrically coupled to the power supply voltage VSS, and the gate is electrically coupled. Connect the gate of P-type transistor P7. One source/drain of the N-type transistor N6 is electrically coupled to the bit line BL, and the other source/drain is electrically coupled to one source/drain of the N-type transistor N4 and the N-type transistor N5. The gate is electrically connected to the write word line WWL. One source/drain of the N-type transistor N7 is electrically coupled to the complementary bit line BLB, and the other source/drain is electrically coupled to one source/drain of the N-type transistor N5 and the N-type transistor N4. The gate is electrically coupled to the write word line WWL. One source/drain of the N-type transistor N8 is electrically coupled to the read bit line RBL, and the gate is electrically coupled to a read word line RWL. One source/drain of the N-type transistor N9 is electrically coupled to another source/drain of the N-type transistor N8, and the other source/drain is electrically coupled to the power supply voltage VSS, and the gate is electrically coupled. Connect the gate of the N-type transistor N4. In this embodiment, the power supply voltage VDD is greater than the bias voltage Vbias, the operating voltage Vcell, and the power supply voltage VSS. The bias voltage Vbias is equal to the operating voltage Vcell, and the bias voltage Vbias and the operating voltage Vcell are both greater than the power supply voltage VSS.

6 is a circuit diagram of an operating voltage supply circuit and a memory cell in accordance with another embodiment of the present invention. In Fig. 6, reference numeral 601 is denoted as an operating voltage supply circuit, and reference numeral 603 is denoted as a memory cell. Specifically, the working voltage supply circuit 601 mainly includes three N-type transistors N1 and N2. With N3. The source/drain and the gate of the N-type transistor N1 are electrically coupled to one node to generate the operating voltage Vcell, and the other source/drain is electrically coupled to the power supply voltage VSS. One source/drain of the N-type transistor N2 is electrically coupled to the node, and the gate is electrically coupled to the complementary bit line BLB. One source/drain of the N-type transistor N3 is electrically coupled to another source/drain of the N-type transistor N2, and the other source/drain is electrically coupled to the power supply voltage VSS, and the gate is electrically The bit line BL is coupled.

As for the memory cell 603, there are mainly two P-type transistors P1 and P2 and six N-type transistors N4, N5, N6, N7, N8 and N9. One source/drain of the P-type transistors P1 and P2 is electrically coupled to the power supply voltage VDD. One source/drain of the N-type transistor N4 is electrically coupled to another source/drain of the P-type transistor P1, and the other source/drain is electrically coupled to a node in the operating voltage supply circuit 601 to receive the operation. The voltage is Vcell, and the gate is electrically coupled to the gate of the P-type transistor P1. One source/drain of the N-type transistor N5 is electrically coupled to another source/drain of the P-type transistor P2, and the other source/drain is electrically coupled to a node in the operating voltage supply circuit 601 to receive the operation. The voltage is Vcell, and the gate is electrically coupled to the gate of the P-type transistor P2. One source/drain of the N-type transistor N6 is electrically coupled to the bit line BL, and the other source/drain is electrically coupled to one source/drain of the N-type transistor N4 and the N-type transistor N5. The gate is electrically connected to the write word line WWL1. One source/drain of the N-type transistor N7 is electrically coupled to the complementary bit line BLB, and the other source/drain is electrically coupled to one source/drain of the N-type transistor N5 and the N-type transistor N4. The gate is electrically coupled to the write word line WWL1. One source/drain of the N-type transistor N8 is electrically coupled to the read bit line RBL, and the gate is electrically coupled to the read word line RWL. One source/drain of the N-type transistor N9 is electrically coupled to another source/drain of the N-type transistor N8, and the other source/drain is electrically coupled to the power supply voltage VSS, and the gate is electrically The gate of the N-type transistor N4 is coupled. In this embodiment, the power supply voltage VDD is large. The operating voltage Vcell and the power supply voltage VSS, and the operating voltage Vcell is greater than the power supply voltage VSS.

In addition, although in the above description, the memory cell 603 is implemented by eight transistors, the memory cell 603 may be implemented by six transistors, that is, the memory cell 603 includes only two P-type transistors P1 and P2 and four N-type transistors N4, N5, N6 and N7.

FIG. 7 is a circuit diagram showing an operating voltage supply circuit and a memory cell according to another embodiment of the present invention. The embodiment shown in FIG. 7 is substantially equivalent to the embodiment shown in FIG. 6, except that the operating voltage supply circuit 601 shown in FIG. 6 is composed of three N-type transistors, and FIG. The working voltage supply circuit 701 is composed of two P-type transistors and four N-type transistors. One source/drain of the P-type transistor P1 and the substrate are electrically coupled to the power supply voltage VDD, and the gate is electrically coupled to the complementary bit line BLB. One source/drain of the P-type transistor P2 and the substrate are electrically coupled to the power supply voltage VDD, and the other source/drain is electrically coupled to the other source/drain of the P-type transistor P1, and the gate Then electrically connected to the bit line BL. One source/drain and the gate of the N-type transistor N1 are electrically coupled to another source/drain of the P-type transistors P1 and P2. One source/drain and the gate of the N-type transistor N2 are electrically coupled to another source/drain of the N-type transistor N1, and the other source/drain is electrically coupled to a node to generate a work. Voltage Vcell. One source/drain of the N-type transistor N3 is electrically coupled to the node, and the gate is electrically coupled to the complementary bit line BLB. One source/drain of the N-type transistor N4 is electrically coupled to another source/drain of the N-type transistor N3, and the other source/drain is electrically coupled to the power supply voltage VSS, and the gate is electrically coupled. The bit line BL is connected.

The circuit structure of the memory cell 703 is substantially similar to that of the memory cell 603 shown in FIG. 6. The memory cell 703 is also composed of two P-type transistors P3 and P4 and six N-type transistors N5, N6, N7, N8, N9. Group with N10 The circuit coupling relationship and operation are also described in detail in the embodiment shown in FIG. 6, and are not described here. It should be noted that, in this embodiment, the power supply voltage VDD is greater than the operating voltage Vcell and the power supply voltage VSS, and the operating voltage Vcell is greater than the power supply voltage VSS.

In addition, although in the above description, the memory cell 703 is implemented by eight transistors, the memory cell 703 may be implemented by six transistors, that is, the memory cell 703 includes only two P-type transistors P3 and P4 and four N-type transistors N5, N6, N7 and N8.

In summary, the present invention solves the aforementioned problem in that all memory cells in the same row in the memory cell array are divided into at least two groups of memory cells. One set of memory cells is configured to receive an operating voltage supplied by one of at least two sets of operating voltage supply circuits in the array of memory cells. The other set of memory cells is for receiving the operating voltage supplied by the other of the at least two sets of operating voltage supply circuits in the memory cell array. Therefore, after adopting the circuit structure of the memory cell array of the present invention, not only the influence of the voltage drop on the memory cell can be improved, but also the anti-noise capability of the memory cell during the writing period can be improved.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧ memory cell array

101, 105‧‧‧ working voltage supply circuit

103, 107‧‧‧ memory cells

111, 113‧‧‧ Array gap

BL‧‧‧ bit line

BLB‧‧‧complementary bit line

WWL‧‧‧Write word line

V1, V2‧‧‧ working voltage

Claims (23)

A memory cell array comprising: a bit line; a complementary bit line; a first working voltage supply circuit electrically coupled to the bit line and the complementary bit line and configured to supply a first operating voltage; a second operating voltage supply circuit electrically coupled to the bit line and the complementary bit line for supplying a second operating voltage; a first memory cell electrically coupled to the bit line and the complementary bit a second line for receiving the first operating voltage; and a second memory cell electrically coupled to the bit line and the complementary bit line for receiving the second operating voltage, wherein the second memory cell And the first memory cell is located in the same row in the memory cell array. The memory cell array of claim 1, wherein the first operating voltage supply circuit and the second operating voltage supply circuit each include: a node for generating the first operating voltage or the second operating voltage a first N-type transistor, one source/drain is electrically coupled to a power supply voltage, and the other source/drain is electrically coupled to the node; and a second N-type transistor is a source/汲The pole is electrically coupled to the power supply voltage, and the other source/drain is electrically coupled to the node; a first P-type transistor has a source/drain electrically coupled to the node, and the gate is electrically a gate coupled to the second N-type transistor; a second P-type transistor, wherein a source/drain is electrically coupled to the first P-type Another source/drain of the crystal, the other source/drain is electrically coupled to the power supply voltage, and the gate is electrically coupled to the gate of the first N-type transistor; a first inverter, The input end is electrically coupled to the bit line, and the output end is electrically coupled to the gate of the second P-type transistor; and a second inverter is electrically coupled to the complementary bit line. The output terminal is electrically coupled to the gate of the first P-type transistor, wherein the first operating voltage or the second operating voltage on the node is equal to or less than the power supply voltage. The memory cell array of claim 2, wherein the first N-type transistor and the second N-type transistor are both low threshold voltage transistors. The memory cell array of claim 2, wherein the first N-type transistor and the second N-type transistor are both high threshold voltage transistors. The memory cell array of claim 2, wherein the first N-type transistor and the second N-type transistor are both general threshold voltage transistors. The memory cell array of claim 1, wherein the first operating voltage supply circuit and the second operating voltage supply circuit each include: a node for generating the first operating voltage or the second operating voltage a first N-type transistor, wherein one source/drain and the gate are electrically coupled to a power supply voltage, and the other source/drain is electrically coupled to the node; a first P-type transistor a source/drain is electrically coupled to the node; a second P-type transistor, one source/drain is electrically coupled to another source/drain of the first P-type transistor, and the other The source/drain is electrically coupled to the power supply voltage; a first inverter having an input electrically coupled to the bit line, and an output electrically coupled to the gate of the second P-type transistor; and a second inverter having an input terminal The complementary bit line is coupled to the gate, and the output is electrically coupled to the gate of the first P-type transistor, wherein the first operating voltage or the second operating voltage on the node is less than or equal to the voltage. The memory cell array of claim 6, wherein the first N-type transistor is a low threshold voltage transistor. The memory cell array of claim 6, wherein the first N-type transistor is a high threshold voltage transistor. The memory cell array of claim 6, wherein the first N-type transistor is a general threshold voltage transistor. The memory cell array of claim 1, wherein the first operating voltage supply circuit and the second operating voltage supply circuit each include: a node for generating the first operating voltage or the second operating voltage a first P-type transistor, one source/drain is electrically coupled to a power supply voltage, and the other source/drain and the gate are electrically coupled to the node; a second P-type transistor, One source/drain is electrically coupled to the node; a third P-type transistor, one source/drain is electrically coupled to another source/drain of the second P-type transistor, and the other source The first pole is electrically coupled to the bit line, and the output end is electrically coupled to the gate of the third P-type transistor; as well as a second inverter having an input terminal electrically coupled to the complementary bit line, and an output terminal electrically coupled to the gate of the second P-type transistor, wherein the first operating voltage on the node Or the second operating voltage is less than or equal to the power voltage. The memory cell array of claim 10, wherein the first P-type transistor is a low threshold voltage transistor. The memory cell array of claim 10, wherein the first P-type transistor is a high threshold voltage transistor. The memory cell array of claim 10, wherein the first P-type transistor is a general threshold voltage transistor. The memory cell array of claim 1, wherein the first operating voltage supply circuit and the second operating voltage supply circuit each include: a first node for generating the first operating voltage or the second Operating voltage; a first P-type transistor, one source/drain is electrically coupled to a bias voltage, another source/drain is electrically coupled to the first node; and a second P-type transistor is One source/drain is electrically coupled to the bias, and another source/drain is electrically coupled to the first node; a third P-type transistor is electrically coupled to the first source/drain a fourth P-type transistor, wherein one source/drain is electrically coupled to another source/drain of the third P-type transistor, and the other source/drain is electrically coupled to the first a power supply voltage; a first inverter having an input terminal electrically coupled to the bit line, and an output terminal electrically coupled to the gate of the fourth P-type transistor; and a second inverter having an input terminal electrical property The complementary bit line is coupled, and the output end is electrically coupled to the gate of the third P-type transistor. The memory cell array of claim 14, further comprising a bias supply circuit, the bias supply circuit comprising: a second node for generating the bias voltage; a fifth P-type transistor, One source/drain is electrically coupled to the first power supply voltage, and the other source/drain and the gate are electrically coupled to the second node; a first N-type transistor, a source/汲The pole and the gate are electrically coupled to the second node; a second N-type transistor, wherein a source/drain and a gate are electrically coupled to another source of the first N-type transistor And a third N-type transistor, wherein one source/drain and the gate are electrically coupled to another source/drain of the second N-type transistor, and the other source/drain is electrically coupled Connected to a second power supply voltage, wherein the first N-type transistor, the second N-type transistor, and the base of the third N-type transistor are electrically coupled to the second power supply voltage. The memory cell array of claim 15, wherein the bias voltage is less than the first power supply voltage and greater than the second power supply voltage, and the second power supply voltage is less than the first power supply voltage. The memory cell array of claim 1, wherein the first working voltage supply circuit and the second working voltage supply circuit both comprise: a node for generating the first working voltage or the second working voltage; a first N-type transistor, wherein a source/drain and a gate are electrically coupled to the node, and another source/汲The pole is electrically coupled to a power supply voltage; a second N-type transistor has a source/drain electrically coupled to the node, and the gate is electrically coupled to the complementary bit line; The three N-type transistor has one source/drain electrically coupled to the other source/drain of the second N-type transistor, the other source/drain is electrically coupled to the supply voltage, and the gate is The bit line is electrically coupled, wherein the first working voltage or the second working voltage on the node is greater than or equal to the power voltage. The memory cell array of claim 1, wherein the first operating voltage supply circuit and the second operating voltage supply circuit each include: a node for generating the first operating voltage or the second operating voltage a first P-type transistor, wherein a source/drain and a substrate are electrically coupled to a first supply voltage, and a gate is electrically coupled to the complementary bit line; a second P-type transistor One source/drain and the substrate are electrically coupled to the first power supply voltage, and the other source/drain is electrically coupled to another source/drain of the first P-type transistor, and the gate is Electrically coupling the bit line; a first N-type transistor, wherein a source/drain and a gate are electrically coupled to another source/drain of the second P-type transistor; a second N a type of transistor, wherein one source/drain and the gate are electrically coupled to another source/drain of the first N-type transistor, and the other source/drain is electrically coupled to the node; a three-N type transistor, wherein a source/drain is electrically coupled to the node, and a gate is electrically coupled to the complementary bit line; a fourth N-type transistor, wherein one source/drain is electrically coupled to another source/drain of the third N-type transistor, and the other source/drain is electrically coupled to a second supply voltage, and The gate is electrically coupled to the bit line, wherein the first operating voltage or the second operating voltage on the node is less than the first power voltage and greater than the second power voltage, and the second power voltage is It is less than or equal to the first power voltage. The memory cell array of claim 1, wherein the first memory cell and the second memory cell comprise: a node for receiving the first working voltage or the second working voltage; a P-type transistor, wherein a source/drain is electrically coupled to the node; a second P-type transistor has a source/drain electrically coupled to the node; and a first N-type transistor, a source thereof The second source/drain is electrically coupled to the other source/drain of the first P-type transistor, the other source/drain is electrically coupled to a power supply voltage, and the gate is electrically coupled to the first P-type a gate of the transistor; a second N-type transistor, wherein one source/drain is electrically coupled to another source/drain of the second P-type transistor, and the other source/drain is electrically coupled to the gate a power supply voltage, and the gate is electrically coupled to the gate of the second P-type transistor; a third N-type transistor, one source/drain is electrically coupled to the bit line, and the other source/汲Electropolarly coupling a source/drain of the first N-type transistor to a gate of the second N-type transistor, and the gate is electrically coupled to a write word line; and a fourth N-type transistor, one source/drain is electrically coupled to the a complementary source line, the other source/drain is electrically coupled to a source/drain of the second N-type transistor and a gate of the first N-type transistor, and the gate is electrically coupled to the gate Writing a word line, wherein the first working voltage or the second working voltage is greater than or equal to the voltage. The memory cell array of claim 1, wherein the first memory cell and the second memory cell comprise: a node for receiving the first working voltage or the second working voltage; a P-type transistor, wherein a source/drain is electrically coupled to the node; a second P-type transistor has a source/drain electrically coupled to the node; and a first N-type transistor, a source thereof The second source/drain is electrically coupled to the other source/drain of the first P-type transistor, the other source/drain is electrically coupled to a power supply voltage, and the gate is electrically coupled to the first P-type a gate of the transistor; a second N-type transistor, wherein one source/drain is electrically coupled to another source/drain of the second P-type transistor, and the other source/drain is electrically coupled to the gate a power supply voltage, and the gate is electrically coupled to the gate of the second P-type transistor; a third N-type transistor, one source/drain is electrically coupled to the bit line, and the other source/汲Electropolarly coupling a source/drain of the first N-type transistor to a gate of the second N-type transistor, and the gate is electrically coupled to a write word line; a fourth N Type of transistor, one source/drain is electrically coupled to the complementary Writing a bit line, the other source/drain is electrically coupled to a source/drain of the second N-type transistor and a gate of the first N-type transistor, and the gate is electrically coupled The write word line; a fifth N-type transistor, wherein a source/drain is electrically coupled to a read bit line, and the gate is electrically coupled to a read word line; and a first A six-N transistor, one source/drain is electrically coupled to another source/drain of the fifth N-type transistor, the other source/drain is electrically coupled to the power supply voltage, and the gate is electrically The gate of the first N-type transistor is coupled to the gate of the first N-type transistor, wherein the first operating voltage or the second operating voltage is greater than or equal to voltage. The memory cell array of claim 1, wherein the first memory cell and the second memory cell comprise: a node for receiving the first working voltage or the second working voltage; a P-type transistor, wherein a source/drain is electrically coupled to a first supply voltage; and a second P-type transistor is electrically coupled to the first supply voltage; An N-type transistor, wherein one source/drain is electrically coupled to another source/drain of the first P-type transistor, another source/drain is electrically coupled to the node, and the gate is electrically coupled Connected to the gate of the first P-type transistor; a second N-type transistor, one source/drain is electrically coupled to another source/drain of the second P-type transistor, and another source/汲The gate is electrically coupled to the gate of the second P-type transistor; and the third N-type transistor is electrically coupled to the bit line by a source/drain. The other source/drain is electrically coupled to one source/drain of the first N-type transistor and the gate of the second N-type transistor, and the gate is electrically coupled to a write word line. And a fourth N-type transistor, one source/dip Electrically coupling the complementary bit line, the other source/drain is electrically coupled to one source/drain of the second N-type transistor and the gate of the first N-type transistor, and the gate is Electrically coupling the write word line, wherein the first power voltage is greater than the first operating voltage or the second operating voltage. The memory cell array of claim 21, wherein the first memory cell and the second memory cell further comprise: a fifth N-type transistor, wherein a source/drain is electrically coupled to a read a bit line, wherein the gate is electrically coupled to a read word line; and a sixth N-type transistor, wherein a source/drain is electrically coupled to another source of the fifth N-type transistor/ The first source/drain is electrically coupled to a second power supply voltage, and the gate is electrically coupled to the gate of the first N-type transistor, wherein the first operating voltage or the second The operating voltage is greater than or equal to the second supply voltage. The memory cell array of claim 1, further comprising at least one write word line electrically coupled to the first memory cell or the second memory cell.