TW201503157A - Semiconductor chip - Google Patents

Abstract

Provided is a semiconductor chip comprising: an input/output circuit; first and second power supply lines that supply operating voltage to the input/output circuit; and a capacitance element and a resistor that are provided in series between the first power supply line and the second power supply line.

Description

Semiconductor wafer

The present invention relates to semiconductor wafers.

In general, a semiconductor wafer such as a semiconductor memory is provided with an input/output circuit for inputting and outputting signals between the external and external signals. Such an input/output circuit is disposed between the power supply wiring and the ground (GND) wiring, and is supplied with power through the wiring, and is capable of receiving signals from the outside of the semiconductor wafer or for the semiconductor wafer. The signal of the external signal. Such an input/output circuit is constituted by an input circuit and an output circuit, and when a plurality of pieces of data are simultaneously output as in a semiconductor memory, for example, an output buffer system constituting an output circuit of the input/output circuit Since the operation is performed in plural, there is a case where the potential difference between the power supply wiring and the GND wiring fluctuates due to noise or the like caused by the operation of the output buffer.

Therefore, in the patent document 1 (JP-A-2011-233765), the patent document 2 (JP-A-2010-67661), and the patent document 3 (JP-A-2006-253393), A technique for suppressing the potential change operation between wirings by arranging a compensation capacity between the power supply wiring and the GND wiring is shown.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2011-233765

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2010-67661

[Patent Document 3] Japanese Patent Laid-Open Publication No. 2006-253393

In general, a semiconductor wafer is sealed in a package made of a sealing material such as resin or ceramics and a wiring for connecting a semiconductor wafer to the outside (encapsulated).

Here, as a method of encapsulating a semiconductor wafer, there is a method of connecting terminals corresponding to one semiconductor wafer to one terminal of the package, and a plurality of semiconductor wafers are connected to one terminal of the package. Various packaging methods such as the method of the terminal (DDP: Dual Die Package).

After performing various simulations, the inventors have found that the optimum compensation capacity for reducing the noise included in the output signal can be sufficiently reduced even when the same semiconductor wafer is used. The value will also vary depending on the packaging method or the wiring pattern.

That is, it is caused by the general reasoning of the package as described above. The variation of the optimum value of the compensation capacity that occurs in the method or the wiring pattern is performed on the compensation capacity of the semiconductor wafer in a manner that can sufficiently suppress the noise of the output signal at the stage before the encapsulation. In the adjustment stage, when the semiconductor wafer is packaged, there is still a case where noise of the output signal is not sufficiently suppressed, which causes a problem.

The semiconductor wafer of the present invention includes: an input/output circuit; and first and second power supply lines for supplying an operating voltage to the input/output circuit; and between the first power supply line and the second power supply line The capacitance element and the resistance portion which are provided in series, and the resistance portion can change the resistance value.

According to the present invention, the noise contained in the output signal can be reduced.

100‧‧‧Semiconductor wafer

101‧‧‧ memory cell array

102‧‧‧ memory cells

103‧‧‧Internal voltage generation circuit

104‧‧‧X decoder

105‧‧‧Y decoder

106‧‧‧X control circuit

107‧‧‧Y control circuit

108‧‧‧Sensing amplifier circuit

109‧‧‧Input and output

110‧‧‧Compensation capacity

201‧‧‧VSSQ PAD

202‧‧‧VDDQ PAD

203‧‧‧DQ PAD

204‧‧‧Input and output circuits

204A‧‧‧Output circuit

204B‧‧‧Input circuit

205‧‧‧Compensation capacity

206‧‧‧Input and output blocks

207‧‧‧Input and output blocks

301‧‧‧protective components

302‧‧‧ wiring

303‧‧‧ wiring

304‧‧‧Compensation capacity

305‧‧‧Compensation capacity

400‧‧‧Semiconductor wafer

400A‧‧‧Semiconductor wafer

401‧‧‧Resistor

501‧‧‧ Circuit

600‧‧‧Semiconductor wafer

601‧‧‧Variable resistance components

700‧‧‧Semiconductor wafer

701‧‧‧resistive components

701A‧‧‧resistive components

701B‧‧‧resistive components

701C‧‧‧resistive components

701D‧‧‧resistive components

801‧‧‧ connection point

802‧‧‧ connection point

803‧‧‧ Connection point

804‧‧‧ connection point

805‧‧‧ connection point

900‧‧‧Semiconductor wafer

901‧‧‧Resistive components

902‧‧‧MOS switch

903‧‧‧Control block

VCC‧‧‧ power terminal

GND‧‧‧Power terminal

BL‧‧‧ bit wiring

WL‧‧‧ character wiring

VDDQ‧‧‧Power cord

VSSQ‧‧‧Power cord

FIG. 1 is a view showing a schematic configuration of a general semiconductor wafer.

Fig. 2 is a schematic configuration diagram of an input/output block constituting the input/output unit shown in Fig. 1.

FIG. 3A is a diagram showing an example of the layout of the input/output section shown in FIG. 1.

FIG. 3B is a diagram showing another example of the layout of the input/output section shown in FIG. 1.

FIG. 3C is a diagram showing another example of the layout of the input/output section shown in FIG. 1.

FIG. 4A is a schematic configuration diagram of a general semiconductor wafer.

Fig. 4B is a schematic configuration diagram of a semiconductor wafer in one embodiment of the present invention.

FIG. 5 is a view showing an example of the layout on the substrate of the semiconductor wafer shown in FIG. 4B.

Fig. 6 is a schematic configuration diagram of a semiconductor wafer in a first embodiment of the present invention.

Fig. 7 is a schematic configuration diagram of a semiconductor wafer in a second embodiment of the present invention.

FIG. 8 is a view showing an example of the configuration of the resistor portion in the semiconductor wafer shown in FIG. 7.

Fig. 9 is a schematic configuration diagram of a semiconductor wafer in a third embodiment of the present invention.

(embodiment)

FIG. 1 is a schematic configuration of a general semiconductor wafer 100. A picture of the show. In addition, in FIG. 1, it is assumed that the semiconductor wafer 100 is a semiconductor memory.

The semiconductor wafer 100 is provided with a memory cell array 101, an internal voltage generating circuit 103, an X decoder 104, a Y decoder 105, an X control circuit 106, a Y control circuit 107, and an input/output unit 109, And a compensation capacity of 110.

The memory cell array 101 is provided with a plurality of word lines WL and a plurality of bit lines BL. Further, at the intersection between each of the word line wiring WL and the bit line BL, the memory cell 102 is formed.

The internal voltage generating circuit 103 converts the voltage supplied from the power supply terminals (VCC, GND), and supplies the operating voltage to the X decoder 104, the Y decoder 105, and the input/output unit 109.

The X decoder 104 is configured to input an address signal representing the address of the read memory cell 102 for reading the memory, and decode the input address signal, and decode the decoded address signal. The address signal is output to the X control circuit 106.

The Y decoder 105 is configured to input an address signal representing the address of the memory cell 102 read, and decode the input address signal, and decode the decoded address signal. The address signal is output to the Y control circuit 107.

The X control circuit 106 selects the word line WL in response to the address signal decoded by the X decoder 104. Further, the Y control circuit 107 selects the bit line BL in response to the address signal decoded by the Y decoder 105. By selecting the word wiring WL and the bit The meta-wire BL, the memory cell 102 corresponding to the address signal is selected.

The signal recorded in the selected memory cell 102 is read via the bit line BL and amplified by the sense amplifier circuit 108 provided in the Y control circuit 107.

The input/output unit 109 outputs a signal amplified by the sense amplifier circuit 108 to the outside of the semiconductor wafer 100. Further, the input/output unit 109 is configured by a plurality of input/output blocks which are described as functional units connected to the input and output, which will be described later.

The compensation capacity 110 is disposed between the power supply wiring and the GND terminal that supply the operating voltage from the internal voltage generating circuit 103 to the X decoder 104, the Y decoder 105, and the input/output unit 109. By the compensation capacity 110, the fluctuation of the operating voltage supplied to the X decoder 104, the Y decoder 105, and the input/output unit 109 is suppressed.

Fig. 2 is a view showing a schematic configuration of an input/output block constituting the input/output unit 109.

The input/output unit 109 is configured by the input/output block 206 and the input/output block 207, and the input/output block 206 and the input/output block 207 are evenly arranged repeatedly.

The input and output block 206 is constructed by the VSSQ PAD 201, and the DQ PAD 203, and the input and output circuit 204, and the compensation capacity 205. The input and output block 207 is constructed by VDDQ PAD 202, and DQ PAD 203, and input and output circuit 204, and compensation capacity 205.

The VSSQ PAD 201 is connected to an internal voltage generating circuit 103 (not shown) in FIG. 2, and is supplied with a potential VSSQ. Further, the VSSQ PAD 201 is connected to the power supply line VSSQ which is the first power supply line. Therefore, the potential of the power supply line VSSQ is the potential VSSQ. Further, the potential VSSQ is, for example, a ground potential.

The VDDQ PAD 202 is connected to an internal voltage generating circuit 103 (not shown) in FIG. 2, and is supplied with a potential VDDQ. Further, the VDDQ PAD 202 is connected to the power supply line VDDQ which is the second power supply line. Therefore, the potential of the power supply line VDDQ is the potential VDDQ.

The input/output circuit 204 is connected to the power supply line VDDQ and the power supply line VSSQ, and is supplied with an operating voltage via the power supply lines. Further, the input/output circuit 204 is connected to the DQ PAD 203, and the signal input and output between the external and external signals of the semiconductor wafer 100 (not shown) in FIG. 2 are performed via the DQ PAD 203.

The compensation capacity 205 is disposed between the power supply line VSSQ and the power supply line VDDQ. That is, the compensation capacity 205, one of which is connected to the power supply line VSSQ, and the other end is connected to the power supply line VDDQ.

Next, the layout of the input/output unit 109 will be described.

As described above, at the input/output portion 109, the input/output block 206 and the input/output block 207 are repeatedly arranged. Therefore, the following is for one input and output circuit 204 and its corresponding VSSQ PAD201, VDDQ PAD202, DQ PAD203 and compensation The layout of the capacity 205 is described with reference to FIGS. 3A to 3C. In FIGS. 3A to 3C, the same components as those in FIG. 2 are denoted by the same reference numerals, and their description will be omitted.

FIG. 3A is a diagram showing an example of the layout of the input/output unit 109.

In FIG. 3A, the input/output circuit 204 is connected to each of the power supplies PAD (VSSQ PAD201 and VDDQ PAD202) via the power supply line VSSQ and the power supply line VDDQ.

The compensation capacity 205 is disposed between the power supply line VSSQ and the power supply line VDDQ.

Further, between the VSSQ PAD 201 and the power supply line VDDQ, between the VDDQ PAD 202 and the power supply line VSSQ, between the DQ PAD 203 and the power supply line VSSQ, and between the DQ PAD 203 and the power supply line VDDQ, protection elements for absorbing current are respectively disposed. 301.

In general, in a semiconductor wafer, since the wiring system is highly refined, depending on the layout of the circuit, there is a possibility of occurrence of damage (ESD destruction) due to electrostatic discharge (ESD: Electro Static Discharge). Sex. Therefore, it is necessary to determine the layout of the circuit in consideration of ESD damage.

In FIG. 3A, when the input/output circuit 204 outputs a signal, a current equal to or higher than a rated current is input from the respective power sources PAD to the input/output circuit 204, and the input/output circuit 204 is subject to ESD destruction.

Here, as above, in VSSQ PAD201 and electricity A protection element 301 is disposed between the source line VDDQ, between the VDDQ PAD 202 and the power line VSSQ, between the DQ PAD 203 and the power line VSSQ, and between the DQ PAD 203 and the power line VDDQ. Therefore, with the protective element 301 thus, since the current of the rated current or more flowing from the respective power sources PAD to the input/output circuit 204 is absorbed, the possibility of occurrence of ESD destruction of the input/output circuit 204 is lowered.

However, there is a case where the current flowing from the respective power sources PAD to the input/output circuit 204 cannot be completely absorbed by the protection element 301. In this case, the current that cannot be completely absorbed by the protection element 301 flows into the input/output circuit 204, and the ESD destruction of the input/output circuit 204 may occur.

FIG. 3B is a diagram showing another example of the layout of the input/output unit 109.

If the layout shown in FIG. 3B is compared with the layout shown in FIG. 3A, the input/output circuit 204 is further connected to each power source PAD via the wirings 302 and 303, and the compensation capacity 205 is The connection to each power source PAD is not made via the power line VSSQ and the power line VDDQ, and is different.

In FIG. 3B, the wiring length between each power source PAD and the input/output circuit 204 is longer than the wiring length between each of the power source PAD and the input/output circuit 204 shown in FIG. 3A. Therefore, the parasitic resistance of the wiring between the respective power source PADs and the input/output circuit 204 is large. Therefore, the current that cannot be completely absorbed by the protection element 301 is attenuated by the parasitic resistance, and the ESD damage of the input/output circuit 204 occurs. The possibility is reduced.

On the other hand, if the layout shown in FIG. 3B is compared with the layout shown in FIG. 3A, the compensation capacity 205 is not connected to each power source PAD via the power supply line VSSQ and the power supply line VDDQ. The parasitic resistance of the wiring between the compensation capacity 205 and each power source PAD is small. Therefore, the current that is completely absorbed by the protection element 301 flows into the compensation capacity 205 in a state that is not sufficiently attenuated by the parasitic resistance of the wiring between the compensation capacitor 205 and each power source PAD, and thus the compensation capacity The possibility of ESD damage occurring in 205 is high.

FIG. 3C is a diagram showing another example of the layout of the input/output unit 109.

The input/output circuit 204 is connected to each power source PAD via wirings 302 and 303, similarly to FIG. 3B. Therefore, the wiring length between each of the power source PAD and the input/output circuit 204 is long, and the parasitic resistance of the wiring between the power source PAD and the input/output circuit 204 is large. Therefore, as generally illustrated in FIG. 3B, the possibility of occurrence of ESD destruction of the input-output circuit 204 is reduced.

The compensation capacities 304 and 305 are disposed between the wiring 302 and the wiring 303. Here, the wiring 302 is connected to the power supply line VDDQ, and the wiring 303 is connected to the power supply line VSSQ. Therefore, the compensation capacities 304 and 305 are equivalent to being connected to the respective power sources PAD via the power supply line VSSQ and the power supply line VDDQ.

Compensation capacity 304, using each PAD (VSSQ A region under the PAD 201, VDDQ PAD 202, and DQ PAD 203) (the direction of the semiconductor wafer 100 opposite to the stacking direction) is arranged. On the other hand, the compensation capacity 305 is disposed in the vicinity of the input/output circuit 104.

In FIG. 3C, the wiring length between the compensation capacities 304, 305 and the respective power sources PAD is longer than the wiring length between the compensation capacity 205 and the respective power sources PAD shown in FIGS. 3A and 3B. Therefore, the parasitic resistance of the wiring between the compensation capacities 304, 305 and the respective power sources PAD is large. Therefore, the current that cannot be completely absorbed by the protection element 301 is attenuated by the parasitic resistance, and the inflow of the compensation capacities 304 and 305 is suppressed, and the possibility of the ESD destruction of the compensation capacities 304 and 305 is lowered. .

Next, a schematic configuration of a semiconductor wafer in the present embodiment will be described.

First, for comparison, a schematic configuration of a general semiconductor wafer is shown in Fig. 4A. Further, the present invention is mainly for reducing the noise included in the signal output from the input/output circuit, and therefore, it is only for the configuration of the vicinity of the input/output circuit, and the configuration of the other portion is omitted. Description.

Fig. 4A is a view showing a configuration of an important portion of a semiconductor wafer having an input/output portion having a layout shown in Fig. 3C.

In the semiconductor wafer 400A shown in FIG. 4A, the compensation capacity 304 as the first compensation capacity and the compensation as the second compensation capacity The capacity 305 is disposed between the power supply line VSSQ and the power supply line VDDQ, respectively. That is, the compensation capacities 304 and 305 are respectively connected to one end of the power supply line VSSQ and the other end to the power supply line VDDQ. Here, the compensation capacity 304 is arranged such that the wiring length between the compensation capacity 305 and the input/output circuit 204 becomes longer than the compensation capacity 305.

Fig. 4B is a view showing a configuration of an important part of a semiconductor wafer of one embodiment of the present invention. In addition, in FIG. 4B, the same components as those in FIG. 4A are denoted by the same reference numerals, and their description will be omitted.

The semiconductor wafer 400 shown in FIG. 4B is different from the semiconductor wafer 400A shown in FIG. 4A in that the resistance portion 401 is added.

The resistor unit 401 is capable of changing the resistance value, one of which is connected to the power supply line VDDQ, and the other end is connected to the other end of the compensation capacity 304.

The inventors of the present invention found that if the capacity value of the compensation capacity is larger, the effect of reducing the noise is larger, but if the capacity value of the compensation capacity exceeds a predetermined value, , the effect of the noise reduction will be saturated. Therefore, it is not possible to sufficiently reduce the noise by merely changing the capacity values of the compensation capacities 304 and 305.

Further, the inventors of the present invention have found that, in general, the resistance value between the compensation capacity and the input/output circuit 204 is higher. Small, the noise reduction effect in the output signal is higher. As described above, the compensation capacity 305 is shorter than the compensation capacity 304 and the length of the wiring between the input and output circuits 204. Therefore, compared with the parasitic resistance of the wiring between the compensation capacity 304 and the input/output circuit 204, the parasitic resistance of the wiring between the compensation capacity 305 and the input/output circuit 204 is small. Therefore, in the present embodiment, at the compensation capacity 305, the noise reduction effect is maintained high by maintaining the low resistance without adding the resistance portion, and the compensation capacity 304 is added. There is a resistor portion 401.

Further, the inventors of the present invention found that there is a combination in which the noise reduction effect is high between the resistance value of the resistance portion and the capacitance value of the compensation capacity, and this combination is adapted to the package. The method and the wiring pattern and the driving frequency of the semiconductor wafer are different. Therefore, in the present embodiment, by setting the resistance value of the resistor portion 401 to be variable, it is possible to configure the output on the semiconductor wafer 400 for various package methods, wiring patterns, and driving frequencies of semiconductor wafers. The noise in the signal is reduced.

Further, by arranging the resistance elements of various capacitance values and the resistance elements of various resistance values, and selectively connecting these, it is possible to make a combination in which the noise reduction effect is high.

Fig. 5 is a view showing an example of the layout on the substrate of the semiconductor wafer shown in Fig. 4B. In addition, in FIG. 5, the same components as those in FIG. 4B are denoted by the same reference numerals, and their description will be omitted. In addition, in FIG. 5, it is only for the connection related to the present invention. The description of the lines and the wiring or other configurations that are not directly related to the present invention will be omitted.

The circuit 501 is a circuit other than the input/output circuit constituting the semiconductor wafer 400.

As described above, VSSQ PAD201, VDDQ PAD202, and DQ PAD203 are repeatedly arranged on the substrate. In addition, in FIG. 5, the description of VSSQ PAD201 is abbreviate|omitted.

The input/output circuit 204 is divided into an output circuit 204A and an input circuit 204B to be disposed on a substrate. In addition, in FIG. 5, only the wiring which is connected to the output circuit 204A is described, and the wiring which is connected to the input circuit 204B is abbreviate|omitted.

The protection circuit 301 is disposed near VDDQ PAD 202 and DQ PAD 203.

The compensation capacity 304 is configured using the VDDQ PAD 202 and the area under the DQ PAD 203. The compensation capacity 305 is disposed in the vicinity of the output circuit 204B. Therefore, the compensation capacity 304 is arranged such that the wiring length between the compensation capacity 305 and the input/output circuit 204 becomes longer than the compensation capacity 305.

The resistor portion 401 is provided on the wiring between the power source line VDDQ and the compensation capacitor 304 connected to the output circuit 204A.

As described above, according to the present embodiment, the semiconductor wafer 400 includes the capacity element 304 provided between the power supply line VSSQ and the power supply line VDDQ for supplying the operating voltage to the input/output circuit, and the capacity element 304. Connected in series and can change the resistance value Further, the resistor portion 401.

Therefore, the noise in the output signal of the semiconductor wafer 400 can be reduced.

(First embodiment)

Fig. 6 is a schematic configuration diagram of a semiconductor wafer 600 in the first embodiment of the present invention. In addition, in FIG. 6, the same components as those in FIG. 4A are denoted by the same reference numerals, and their description will be omitted.

In the semiconductor wafer 600 shown in FIG. 6, a variable resistance element 601 capable of changing a resistance value is provided as the resistance portion 401.

By changing the resistance value of the variable resistance element 601 in accordance with the method of packaging and the wiring pattern and the driving frequency of the semiconductor wafer to change the resistance value of the resistance portion 401, it is possible to mix the impurity signal in the output signal of the semiconductor wafer 600. The news is lowered. The value of the resistance value of the variable resistance element 601 can be stored in a register in the semiconductor wafer in a volatile or non-volatile manner, or can be supplied from the outside of the semiconductor wafer.

(Second embodiment)

Fig. 7 is a schematic block diagram showing a semiconductor wafer in a second embodiment of the present invention. In addition, in FIG. 7, the same components as those in FIG. 4A are denoted by the same reference numerals, and their description will be omitted.

In the semiconductor wafer 700 shown in FIG. 7, as a resistor The portion 401 is provided with a plurality of resistive elements 701.

The plurality of resistive elements 701 are connected in series. Here, the wiring pattern between the plurality of resistive elements 701 can be changed by the master slice method. The resistance value of the resistance portion 401 can be changed by changing the wiring pattern between the plurality of resistance elements 701.

Further, by changing the resistance value of the plurality of resistance elements 701 to a value different by the power of 2 (1, 2, 4, 8), the resistance to the resistance portion 401 can be obtained. The value is changed subtly.

Fig. 8 is a view for explaining a method of changing the resistance value of the resistor portion 401 constituted by the plurality of resistive elements 701 shown in Fig. 7.

The resistor portion 401 is composed of a resistor element 701A having a resistance value of 1 ohm, 701B having a resistance value of 2 ohms, 701C having a resistance value of 4 ohms, and 701D having a resistance value of 8 ohms.

The resistance elements 701A to 701D are formed using the same tungsten wiring as the wiring constituting the gate electrode of the memory cell. In the use of a metal wiring layer such as copper or aluminum which is connected to the resistive elements 701A to 701D in contact with each other, each of the resistive elements is connected. Therefore, the resistance value can be changed by changing the wiring pattern of the metal wiring layer.

The resistive element 701A is such that one end thereof and the other end of the compensation capacity 304 not shown in FIG. 8 are connected to each other at the connection point 801, and the other end is connected to one end of the resistive element 701B at the connection point 802. Connected to each other.

The resistive element 701B is such that one end thereof and the other end of the resistive element 701A are connected to each other at a connection point 802, and the other end is connected to one end of the resistive element 701C at a connection point 803.

The resistive element 701C is such that one end thereof and the other end of the resistive element 701B are connected to each other at a connection point 803, and the other end is connected to one end of the resistive element 701D at a connection point 804.

The resistive element 701D has one end and the other end of the resistive element 701C connected to each other at a connection point 804, and the other end is connected to a power supply line VDDQ (not shown in FIG. 8) at a connection point 805.

In this manner, the respective resistance elements of the resistance element 701A to the resistor element 701D are connected in series. Therefore, when all of the resistance elements of the resistance element 701A to the resistor element 701D are connected, the resistance value of the resistance portion 401 is 15 ohms. Here, for example, if the connection point 802 and the connection point 803 are short-circuited to each other, the resistance value of the resistance portion 401 is 13 ohms. In this manner, by short-circuiting the connection points of the respective resistance elements, the resistance value of the resistance portion 401 becomes a specific value.

In this manner, by changing the resistance value of the resistor portion 401 by the main surface method in response to the package method and the wiring pattern and the driving frequency of the semiconductor wafer, the noise in the output signal of the semiconductor wafer 700 can be reduce.

(Third embodiment)

Fig. 9 is a schematic configuration diagram of a semiconductor wafer in a third embodiment of the present invention. In addition, in FIG. 9, the same components as those in FIG. 4A are denoted by the same reference numerals, and their description will be omitted.

In the semiconductor wafer 900 shown in FIG. 7, the resistor unit 401 is provided with a plurality of resistor elements 901 and a plurality of MOSs (Metal Oxide) respectively provided corresponding to each of the plurality of resistor elements 901. Semiconductor) switch 902, and control block 903.

The plurality of resistive elements 901 are connected in series.

The plurality of MOS switches 902 are respectively connected in parallel with the corresponding resistive element 901. When the MOS switch 902 is turned on, the resistance element 901 corresponding to the MOS switch 902 is short-circuited, and the resistance value of the resistance portion 401 is changed.

Further, the MOS switch 902 is operated by changing the voltage applied to the MOS switch 902 by using a fuse (FUSE) or a bonding option (BOP). The control block 903 can be configured to generate a control signal for operating the MOS switch 902 in response to an external input, or can be configured to generate a control signal based on a non-volatile memory value.

In this manner, by controlling the ON and OFF of the MOS switch 902 and changing the resistance value of the resistor portion 401 in response to the package method, the wiring pattern, and the driving frequency of the semiconductor wafer, it is possible to change the resistance value of the resistor portion 401. The noise in the output signal of the semiconductor wafer 900 is reduced.

Further, the present invention can obtain the same effect by applying an input/output block in which the same circuit is plurally configured and the High signal and the Low signal are randomly outputted. Therefore, it is also possible to apply to a Clock input unit from the outside, a buffer unit having a large number of simultaneous operations, a logic unit for generating an internal block, and the like.

Moreover, the present invention can achieve the same effect even when applied to a plurality of semiconductors such as a DRAM (Dynamic Random Access Memory), a flash memory, and a logic circuit.

201‧‧‧VSSQ PAD

202‧‧‧VDDQ PAD

203‧‧‧DQ PAD

204‧‧‧Input and output circuits

301‧‧‧protective components

304‧‧‧Compensation capacity

305‧‧‧Compensation capacity

400‧‧‧Semiconductor wafer

401‧‧‧Resistor

VDDQ‧‧‧Power cord

VSSQ‧‧‧Power cord

Claims (11)

A semiconductor wafer comprising: an input/output circuit; and first and second power supply lines for supplying an operating voltage to the input/output circuit; and between the first power supply line and the second power supply line The first capacity element and the resistance portion are provided in series, and the resistance portion can change the resistance value. The semiconductor wafer according to the first aspect of the invention, further comprising: between the first power supply line and the second power supply line, and being provided in comparison with the first capacity element A second capacity element at a region close to the aforementioned input/output circuit. The semiconductor wafer according to the first or second aspect of the invention, wherein the resistor portion is a variable resistance element. The semiconductor wafer according to the first or second aspect of the invention, wherein the resistor portion is formed by a plurality of resistor elements connected in series, and at least one of the plurality of resistor elements can be short-circuited. . The semiconductor wafer according to the first or second aspect of the invention, wherein the resistor portion is provided by a plurality of resistor elements connected in series and each of the plurality of resistor elements It is formed by a plurality of MOS switches connected in parallel with the corresponding resistive elements. Such as the semiconductor described in the fourth or fifth patent scope In the wafer, the resistance value of the plurality of resistive elements is a mutually different value that varies by a power ratio of two. A semiconductor device comprising: a first power supply line; and a second power supply line; and an input/output circuit provided between the first and second power supply lines and connected to the input/output pad And a first capacity element and a resistance element connected in series between the first power supply line and the second power supply line. The semiconductor device according to claim 7, further comprising a second capacity element connected between the first power supply line and the second power supply line. The semiconductor device according to claim 7, wherein the resistive element is a variable resistive element capable of changing a resistance value. The semiconductor device according to claim 7, wherein the resistor element is formed by a tungsten wiring. The semiconductor device according to claim 7, wherein the resistance element is a method of changing a resistance value by a connection pattern of a wiring layer formed on an upper layer of the tungsten wiring for a plurality of tungsten wirings. To form it.