TW201507152A - Lateral insulated gate bipolar transistor and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 description 13
- 230000008569 process Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 238000000137 annealing Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
Description
本發明是有關於一種橫向式絕緣閘雙極電晶體(Lateral Insulated Gate Bipolar Transistor，LIGBT)，特別是有關於一種具有雙倍減少表面電場(Double RESURF)結構及短路陽極(Shorted Anode)結構之橫向式絕緣閘雙極電晶體。
The present invention relates to a Lateral Insulated Gate Bipolar Transistor (LIGBT), and more particularly to a lateral structure having a double reduction surface electric field (Double RESURF) structure and a shorted anode (Shorted Anode) structure. Insulated gate bipolar transistor.
近年來，隨著消費性電子產品的發展，功率半導體元件及其封裝技術便顯得相當重要。功率半導體元件常應用於開關元件，其種類包含絕緣閘雙極電晶體(insulated gate bipolar transistor，IGBT)及功率金氧半導體場效電晶體(metal-oxide-semiconductor field effect transistor，MOSFET)。其中，絕緣閘雙極電晶體是由雙極性接面電晶體(Bipolar Junction Transistor，BJT)和金氧半場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)組成的電力電子元件，兼有金氧半場效電晶體的高輸入阻抗和雙極性接面電晶體的低導通電阻兩方面優點。
In recent years, with the development of consumer electronics, power semiconductor components and their packaging technology have become very important. Power semiconductor components are commonly used in switching devices, and their types include insulated gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field effect transistors (MOSFETs). Among them, the insulated gate bipolar transistor is a power electronic component composed of a Bipolar Junction Transistor (BJT) and a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). There are advantages of both the high input impedance of the MOS half-effect transistor and the low on-resistance of the bipolar junction transistor.
絕緣閘雙極電晶體可分為兩種不同的結構：垂直(Vertical)結構及橫向(Lateral)結構。垂直結構由於較難和現行的積體電路整合，故大多做成單顆元件。而橫向結構可與互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor，CMOS) 製程整合在一起，故在功率積體電路上扮演相當重要的角色。
Insulated gate bipolar transistors can be divided into two different structures: a vertical structure and a lateral structure. The vertical structure is mostly made into a single component because it is difficult to integrate with the current integrated circuit. The lateral structure can be integrated with the Complementary Metal-Oxide-Semiconductor (CMOS) process, so it plays a very important role in the power integrated circuit.
近年來，更發展出絕緣層上矽(Silicon on Insulator，SOI)結構，其係將矽磊晶層成長於絕緣體上，使得功率半導體元件可以有效地降低基板的寄生電容效應與元件本身的漏電流，並降低元件的功率損耗。然而，隨著平價消費性電子產品的出現，成本上的考量便成為絕緣閘雙極電晶體結構設計上的一大難題。
In recent years, a silicon-on-insulator (SOI) structure has been developed, which is to grow a germanium epitaxial layer on an insulator, so that the power semiconductor device can effectively reduce the parasitic capacitance effect of the substrate and the leakage current of the device itself. And reduce the power loss of the component. However, with the advent of affordable consumer electronics, cost considerations have become a major challenge in the design of insulated gate bipolar transistors.
有鑑於上述習知技藝之問題，本發明之其中之一目的在於提供一種橫向式絕緣閘雙極電晶體，主要目的除了中和電極下方所累積的載子以減少漏電流之外，更能夠降低順向電壓(Forward Voltage)及縮短關閉時間(Turn-off time)，使得功率耗損降低。
In view of the above problems of the prior art, it is an object of the present invention to provide a lateral insulated gate bipolar transistor, the main purpose of which is to reduce the leakage current in addition to the carrier accumulated under the neutralization electrode, thereby reducing the leakage current. Forward voltage and Turn-off time reduce power consumption.
此橫向式絕緣閘雙極電晶體至少包含具有第一導電類型之基板；具有第二導電類型之第一離子井，位於基板中；具有第一導電類型之第二離子井，位於基板中且鄰接第一離子井；具有第二導電類型之緩衝層，位於第一離子井中；具有第一導電類型之第一摻雜區，位於緩衝層中；具有第一導電類型之第二摻雜區，位於緩衝層中且鄰接第一摻雜區；以及具有第二導電類型之第三摻雜區，位於緩衝層中，其中第三摻雜區之下方鄰接第一摻雜區，且第三摻雜區之一側鄰接第二摻雜區。
The lateral insulated gate bipolar transistor includes at least a substrate having a first conductivity type; a first ion well having a second conductivity type located in the substrate; and a second ion well having a first conductivity type located in the substrate and adjacent a first ion well; a buffer layer having a second conductivity type, located in the first ion well; a first doped region having a first conductivity type, located in the buffer layer; and a second doped region having a first conductivity type, located And adjacent to the first doped region in the buffer layer; and a third doped region having a second conductivity type, located in the buffer layer, wherein the third doped region is adjacent to the first doped region and the third doped region One side abuts the second doped region.
根據本發明之另一目的，提出一種橫向式絕緣閘雙極電晶體之製造方法，至少包含提供具有第一導電類型之基板；形成具有第二導電類型之第一離子井於基板中；形成具有第一導電類型之第二離子井於基板中，且第二離子井鄰接第一離子井；形成具有第二導電類型之緩衝層於第一離子井中；形成具有第一導電類型之第一摻雜區於緩衝層中；形成具有第一導電類型之第二摻雜區於緩衝層中，且第二摻雜區鄰接第一摻雜區；以及形成具有第二導電類型之第三摻雜區於緩衝層中，其中第三摻雜區之下方鄰接第一摻雜區，且第三摻雜區之一側鄰接第二摻雜區。
According to another object of the present invention, a method for fabricating a lateral insulated gate bipolar transistor includes at least providing a substrate having a first conductivity type; forming a first ion well having a second conductivity type in the substrate; forming a second ion type first ion well is in the substrate, and the second ion well is adjacent to the first ion well; forming a buffer layer having a second conductivity type in the first ion well; forming a first doping having the first conductivity type Forming in the buffer layer; forming a second doped region having a first conductivity type in the buffer layer, and the second doped region adjoins the first doped region; and forming a third doped region having the second conductivity type In the buffer layer, a third doped region is adjacent to the first doped region, and one side of the third doped region is adjacent to the second doped region.
前述之此橫向式絕緣閘雙極電晶體更包含具有第一導電類型之第四摻雜區位於第一離子井中，且第四摻雜區位於緩衝層之一側。其中第四摻雜區中更包含具有第一導電類型之第五摻雜區。
The lateral insulating gate bipolar transistor further comprises a fourth doping region having a first conductivity type located in the first ion well, and a fourth doping region being located on one side of the buffer layer. The fourth doped region further includes a fifth doped region having a first conductivity type.
其中，此橫向式絕緣閘雙極電晶體更包含氧化層位於第四摻雜區上。
Wherein, the lateral insulating gate bipolar transistor further comprises an oxide layer on the fourth doping region.
前述之橫向式絕緣閘雙極電晶體更包含相互鄰接之具有第一導電類型之第六摻雜區及具有第二導電類型之第七摻雜區位於第二離子井中。
The lateral insulating gate bipolar transistor further includes a sixth doped region having a first conductivity type adjacent to each other and a seventh doping region having a second conductivity type in the second ion well.
前述之橫向式絕緣閘雙極電晶體更包含閘極電極位於第一離子井及第二離子井上；陽極電極位於第二摻雜區、第三摻雜區及部分氧化層上；以及陰極電極，位於第五摻雜區、第六摻雜區及第七摻雜區上。
The lateral insulated gate bipolar transistor further includes a gate electrode located on the first ion well and the second ion well; the anode electrode is located on the second doped region, the third doped region and the partial oxide layer; and the cathode electrode, Located on the fifth doping region, the sixth doping region, and the seventh doping region.
承上所述，依據本發明之橫向式絕緣閘雙極電晶體，其可具有一或多個下述優點：
In view of the above, a lateral insulated gate bipolar transistor according to the present invention may have one or more of the following advantages:
(1) 本發明之橫向式絕緣閘雙極電晶體藉由形成第一摻雜區、第二摻雜區及第三摻雜區之短路陽極結構，以中和電極下方所累積的載子並減少漏電流，進而降低順向電壓及縮短關閉時間，使得功率耗損降低。
(1) The lateral insulating gate bipolar transistor of the present invention forms a short-circuited anode structure of the first doping region, the second doping region, and the third doping region to neutralize carriers accumulated under the electrodes and Reduce leakage current, which in turn reduces forward voltage and shortens turn-off time, resulting in reduced power consumption.
(2) 本發明之橫向式絕緣閘雙極電晶體藉由基板、第一離子井、第二離子井及第四摻雜區所形成的雙倍減少表面電場(Double RESURF)結構，以提高此橫向式絕緣閘雙極電晶體之擊穿電壓(Breakdown Voltage)。
(2) The lateral insulated gate bipolar transistor of the present invention has a double reduction surface electric field (Double RESURF) structure formed by a substrate, a first ion well, a second ion well, and a fourth doped region to enhance this The breakdown voltage of the lateral insulated gate bipolar transistor.
(3) 本發明之橫向式絕緣閘雙極電晶體係以非磊晶方式製造，因此製造成本較習知之絕緣層上矽絕緣閘雙極電晶體(Silicon-on-Insulator Insulated Gate Bipolar Transistor，SOI-IGBT)還要低，以符合平價消費性電子產品之成本考量。
(3) The lateral insulating gate bipolar electro-crystal system of the present invention is fabricated in a non-elevation mode, so that the manufacturing cost is higher than that of a conventional silicon-on-insulator Insulated Gate Bipolar Transistor (SOI). - IGBT) is also low to meet the cost considerations of affordable consumer electronics.
茲為使 貴審查委員對本發明之技術特徵及所達到之功效有更進一步之瞭解與認識，謹佐以較佳之實施例及配合詳細之說明如後。
For a better understanding and understanding of the technical features and the efficacies of the present invention, the preferred embodiments and the detailed description are as follows.
10‧‧‧基板
11‧‧‧離子佈植
12‧‧‧遮罩
20‧‧‧第一離子井
21‧‧‧離子佈植
22‧‧‧遮罩
30‧‧‧第二離子井
31‧‧‧離子佈植
32‧‧‧遮罩
40‧‧‧緩衝層
41‧‧‧離子佈植
42‧‧‧遮罩
50‧‧‧第一摻雜區
51‧‧‧離子佈植
52‧‧‧遮罩
60‧‧‧第四摻雜區
61‧‧‧離子佈植
62‧‧‧遮罩
70‧‧‧第二摻雜區
80‧‧‧第五摻雜區
90‧‧‧第六摻雜區
100‧‧‧氧化層
110‧‧‧第三摻雜區
120‧‧‧第七摻雜區
130‧‧‧陽極電極
140‧‧‧陰極電極
150‧‧‧閘極電極
151‧‧‧閘極氧化層
10‧‧‧Substrate
11‧‧‧Ion implantation
12‧‧‧ mask
20‧‧‧First Ion Well
21‧‧‧Ion implantation
22‧‧‧ mask
30‧‧‧Second ion well
31‧‧‧Ion implantation
32‧‧‧ mask
40‧‧‧buffer layer
41‧‧‧Ion implantation
42‧‧‧ mask
50‧‧‧First doped area
51‧‧‧Ion implantation
52‧‧‧ mask
60‧‧‧fourth doping zone
61‧‧‧Ion implantation
62‧‧‧ mask
70‧‧‧Second doped area
80‧‧‧ fifth doping area
90‧‧‧ sixth doping area
100‧‧‧Oxide layer
110‧‧‧ third doping zone
120‧‧‧ seventh doped area
130‧‧‧Anode electrode
140‧‧‧Cathode electrode
150‧‧‧gate electrode
151‧‧‧ gate oxide layer
第1圖至第7圖為本發明之橫向式絕緣閘雙極電晶體之較佳實施例之製程剖面示意圖。
1 to 7 are schematic cross-sectional views showing a process of a preferred embodiment of a lateral insulated gate bipolar transistor of the present invention.
以下將參照相關圖式，說明依本發明之橫向式絕緣閘雙極電晶體之實施例，為使便於理解，下述實施例中之相同元件係以相同之符號標示來說明。
The embodiments of the transverse insulating gate bipolar transistor according to the present invention will be described below with reference to the related drawings. For ease of understanding, the same components in the following embodiments are denoted by the same reference numerals.
請參閱第1圖至第7圖，第1圖至第7圖為本發明之橫向式絕緣閘雙極電晶體之較佳實施例之製程剖面示意圖。本發明之較佳實施例中之第一導電類型及第二導電類型係分別以P型及N型作舉例，惟本發明不限於此。
Please refer to FIG. 1 to FIG. 7 . FIG. 1 to FIG. 7 are schematic cross-sectional views showing a process of a preferred embodiment of a lateral insulated gate bipolar transistor of the present invention. The first conductivity type and the second conductivity type in the preferred embodiment of the present invention are exemplified by P type and N type, respectively, but the invention is not limited thereto.
首先，如第1圖及第2圖所示，提供具有第一導電類型之基板10，在本發明之較佳實施例中，基板10為P-型摻雜矽基板。接著，基板10可例如利用氧化層作為遮罩12，並且經微影及蝕刻定義出離子佈植區域。接著可例如以V族元素(如砷)對基板10進行離子佈植11，並且進行熱趨入(drive-in)，以使得摻質擴散至基板10中而形成具有第二導電類型之第一離子井20，其中此第一離子井20較佳為N-型井(N-well)。
First, as shown in Figures 1 and 2, a substrate 10 having a first conductivity type is provided. In a preferred embodiment of the invention, the substrate 10 is a P-type doped germanium substrate. Next, the substrate 10 can utilize, for example, an oxide layer as the mask 12, and the ion implantation regions are defined by lithography and etching. The substrate 10 can then be ion implanted 11 with, for example, a group V element such as arsenic, and thermally driven-in to diffuse the dopant into the substrate 10 to form a first having the second conductivity type. The ion well 20, wherein the first ion well 20 is preferably an N-well.
接著，利用遮罩22對基板10進行離子佈植21，以形成如第3圖所示之具有第一導電類型之第二離子井30，且第二離子井30係鄰接第一離子井20。其中，第二離子井30較佳為P型井(P well)，離子佈植21之元素則可例如為III族元素(如硼)。
Next, the substrate 10 is ion implanted 21 using a mask 22 to form a second ion well 30 having a first conductivity type as shown in FIG. 3, and the second ion well 30 is adjacent to the first ion well 20. The second ion well 30 is preferably a P-type well, and the element of the ion implant 21 may be, for example, a group III element such as boron.
接著，如第3圖及第4圖所示，利用遮罩32對第一離子井20進行離子佈植31，以形成具有第二導電類型之緩衝層40於第一離子井20中。其中，緩衝層40較佳為N型緩衝層。
Next, as shown in FIGS. 3 and 4, the first ion well 20 is ion implanted 31 using a mask 32 to form a buffer layer 40 having a second conductivity type in the first ion well 20. The buffer layer 40 is preferably an N-type buffer layer.
接著，利用遮罩42對第一離子井20及緩衝層40進行離子佈植41，以分別形成如第5圖所示之具有第一導電類型之第四摻雜區60及具有第一導電類型之第一摻雜區50。其中，第四摻雜區60較佳為P型摻雜區；第一摻雜區50較佳為P型摻雜區，且離子佈植能量大約介於80KeV至100KeV，離子佈植劑量大約介於3×1012
atom/cm2
至6×1012
atom/cm2
，並且進行大約1200℃、60分鐘至80分鐘於氮氣(N2
)環境下的熱退火(anneal)。
Next, the first ion well 20 and the buffer layer 40 are ion implanted 41 by using the mask 42 to form a fourth doping region 60 having the first conductivity type and having the first conductivity type as shown in FIG. 5, respectively. The first doped region 50. The fourth doped region 60 is preferably a P-type doped region; the first doped region 50 is preferably a P-type doped region, and the ion implantation energy is about 80 KeV to 100 KeV, and the ion implantation dose is approximately The temperature was anneal at a temperature of about 1200 ° C for 60 minutes to 80 minutes in a nitrogen (N 2 ) atmosphere at 3 × 10 12 atoms/cm 2 to 6 × 10 12 atoms/cm 2 .
如第5圖及第6圖所示，接著利用遮罩52對第二離子井30、第四雜區60及緩衝層40進行離子佈植51，以各別形成具有第一導電類型之第六摻雜區90、具有第一導電類型之第五摻雜區80及具有第一導電類型之第二摻雜區70。其中，第六摻雜區90較佳為P+型摻雜區；第五摻雜區80較佳為P+型摻雜區；第二摻雜區70較佳為P+型摻雜區，且離子佈植能量大約介於60KeV至100KeV，離子佈植劑量大約介於1×1015
atom/cm2
至3×1015
atom/cm2
，並且進行大約950℃、15分鐘至30分鐘於氮氣環境下的熱退火，且其中第二摻雜區70係鄰接第一摻雜區50。
As shown in FIG. 5 and FIG. 6, the second ion well 30, the fourth impurity region 60, and the buffer layer 40 are then ion implanted 51 by using the mask 52 to form a sixth type having the first conductivity type. A doped region 90, a fifth doped region 80 having a first conductivity type, and a second doped region 70 having a first conductivity type. The sixth doped region 90 is preferably a P+ doped region; the fifth doped region 80 is preferably a P+ doped region; the second doped region 70 is preferably a P+ doped region, and the ion cloth The planting energy is approximately between 60 KeV and 100 KeV, the ion implantation dose is approximately 1×10 15 atoms/cm 2 to 3×10 15 atoms/cm 2 , and is performed at approximately 950 ° C for 15 minutes to 30 minutes under a nitrogen atmosphere. Thermal annealing, and wherein the second doped region 70 is adjacent to the first doped region 50.
此外，此橫向式絕緣閘雙極電晶體之製造方法更進一步以局部矽氧化物(Local Oxidation of Silicon，LOCOS)製程形成氧化層100於第四摻雜區60上。
In addition, the manufacturing method of the lateral insulating gate bipolar transistor further forms the oxide layer 100 on the fourth doping region 60 by a local Oxidation of Silicon (LOCOS) process.
接著，如第6圖及第7圖所示，利用遮罩62對第二離子井30及緩衝層40中之第一摻雜區50進行離子佈植61，以分別形成具有第二導電類型之第七摻雜區120及具有第二導電類型之第三摻雜區110。其中，第七摻雜區120較佳為N+型摻雜區；第三摻雜區110較佳為N+型摻雜區，且離子佈植能量大約介於60KeV至100KeV，離子佈植劑量大約介於1×1015
atom/cm2
至3×1015
atom/cm2
，並且進行大約900℃、60分鐘至90分鐘於氮氣環境下的熱退火。
Next, as shown in FIGS. 6 and 7, the first ion doping region 50 of the second ion well 30 and the buffer layer 40 is ion implanted 61 by using a mask 62 to form a second conductivity type, respectively. The seventh doping region 120 and the third doping region 110 having the second conductivity type. The seventh doped region 120 is preferably an N+ doped region; the third doped region 110 is preferably an N+ doped region, and the ion implantation energy is about 60 KeV to 100 KeV, and the ion implantation dose is approximately The thermal annealing was performed at a temperature of about 900 ° C for 60 minutes to 90 minutes under a nitrogen atmosphere at 1 × 10 15 atoms/cm 2 to 3 × 10 15 atoms/cm 2 .
其中，第七摻雜區120係鄰接第六摻雜區90；第三摻雜區110之下方鄰接第一摻雜區50，且第三摻雜區110之一側鄰接第二摻雜區70。
The seventh doped region 120 is adjacent to the sixth doped region 90; the third doped region 110 is adjacent to the first doped region 50, and one side of the third doped region 110 is adjacent to the second doped region 70. .
最後，形成閘極電極150及閘極氧化層151於第一離子井20及第二離子井30上；形成陽極電極130於第二摻雜區70、第三摻雜區110及部分氧化層100上；以及形成陰極電極140於第五摻雜區80、第六摻雜區90及第七摻雜區120上。
Finally, the gate electrode 150 and the gate oxide layer 151 are formed on the first ion well 20 and the second ion well 30; the anode electrode 130 is formed in the second doping region 70, the third doping region 110 and the partial oxide layer 100. And forming a cathode electrode 140 on the fifth doping region 80, the sixth doping region 90, and the seventh doping region 120.
因此，本發明利用橫向第二離子井30/第一離子井20接面，以及縱向第四摻雜區60/第一離子井20接面與第一離子井20/基板10接面之相互作用，使得第一離子井20(即漂移區Drift Region)同時由橫向及縱向進行空乏(Depletion)，以降低表面電場，進而提高此橫向式絕緣閘雙極電晶體之擊穿電壓(Breakdown Voltage)。
Therefore, the present invention utilizes the lateral second ion well 30/first ion well 20 junction, and the longitudinal fourth dopant region 60/first ion well 20 junction to interact with the first ion well 20/substrate 10 junction The first ion well 20 (ie, the drift zone Drift Region) is simultaneously depleted by lateral and longitudinal directions to reduce the surface electric field, thereby increasing the breakdown voltage of the lateral insulated gate bipolar transistor.
此外，當施加於閘極電極150之電壓超出臨界電壓(Threshold Voltage)且施加於陽極電極16之電壓增加時，電場會使得電子注入第一離子井20而漂移至第三摻雜區110，使得當此橫向式絕緣閘雙極電晶體關閉(Turn-off)時，電子便會累積在陽極電極130下方。因此本發明更利用第一摻雜區50、第二摻雜區70及第三摻雜區110所形成之短路陽極結構，以P+型之第二摻雜區70中和累積在陽極電極130下方的電子並減少漏電流，進而降低順向電壓(Forward Voltage)及縮短關閉時間(Turn-off time)，使得功率耗損降低。
In addition, when the voltage applied to the gate electrode 150 exceeds a threshold voltage and the voltage applied to the anode electrode 16 increases, the electric field causes electrons to be injected into the first ion well 20 to drift to the third doping region 110, such that When the lateral insulating gate bipolar transistor turns off, electrons accumulate below the anode electrode 130. Therefore, the present invention further utilizes the short-circuited anode structure formed by the first doping region 50, the second doping region 70, and the third doping region 110, and the second doping region 70 of the P+ type is accumulated under the anode electrode 130. The electrons reduce the leakage current, which in turn reduces the Forward Voltage and shortens the Turn-off time, resulting in reduced power consumption.
由於本發明係以離子佈植製程(Ion Implantation Process)形成各個離子井及摻雜區，因此相較於習知之絕緣層上矽絕緣閘雙極電晶體(Silicon-on-Insulator Insulated Gate Bipolar Transistor，SOI-IGBT)所使用之磊晶製程，更能夠節省製造成本。
Since the present invention forms each ion well and doped region by an Ion Implantation Process, it is compared to the conventional Silicon-on-Insulator Insulated Gate Bipolar Transistor (Silicon-on-Insulator Insulated Gate Bipolar Transistor). The epitaxial process used in SOI-IGBT) can save manufacturing costs.
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。
The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.
無no
10‧‧‧基板 10‧‧‧Substrate
20‧‧‧第一離子井 20‧‧‧First Ion Well
30‧‧‧第二離子井 30‧‧‧Second ion well
40‧‧‧緩衝層 40‧‧‧buffer layer
50‧‧‧第一摻雜區 50‧‧‧First doped area
60‧‧‧第四摻雜區 60‧‧‧fourth doping zone
70‧‧‧第二摻雜區 70‧‧‧Second doped area
80‧‧‧第五摻雜區 80‧‧‧ fifth doping area
90‧‧‧第六摻雜區 90‧‧‧ sixth doping area
100‧‧‧氧化層 100‧‧‧Oxide layer
110‧‧‧第三摻雜區 110‧‧‧ third doping zone
120‧‧‧第七摻雜區 120‧‧‧ seventh doped area
130‧‧‧陽極電極 130‧‧‧Anode electrode
140‧‧‧陰極電極 140‧‧‧Cathode electrode
150‧‧‧閘極電極 150‧‧‧gate electrode
151‧‧‧閘極氧化層 151‧‧‧ gate oxide layer
Claims (10)
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| TWI587505B (en) * | 2015-11-27 | 2017-06-11 | 世界先進積體電路股份有限公司 | High voltage semiconductor structure |
| US9768283B1 (en) | 2016-03-21 | 2017-09-19 | Vanguard International Semiconductor Corporation | High-voltage semiconductor structure |
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| US7999296B2 (en) * | 2008-04-14 | 2011-08-16 | Macronix International Co., Ltd. | Single gate nonvolatile memory cell with transistor and capacitor |
| US8253164B2 (en) * | 2010-12-23 | 2012-08-28 | Force Mos Technology Co., Ltd. | Fast switching lateral insulated gate bipolar transistor (LIGBT) with trenched contacts |
| CN102790048B (en) * | 2011-05-17 | 2015-03-25 | 旺宏电子股份有限公司 | BJT Semiconductor Structure with Embedded Schottky Diode |
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| TWI587505B (en) * | 2015-11-27 | 2017-06-11 | 世界先進積體電路股份有限公司 | High voltage semiconductor structure |
| US9768283B1 (en) | 2016-03-21 | 2017-09-19 | Vanguard International Semiconductor Corporation | High-voltage semiconductor structure |
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