TW201505142A - Wafer stack package and method of manufacturing same - Google Patents

Abstract

The invention discloses a wafer stack package comprising a device substrate having an upper surface, a lower surface and a side wall. The device substrate includes a sensing region or component region adjacent to the upper surface and a signal pad region. A shallow groove structure extends from the upper surface toward the lower surface along the sidewall of the device substrate. A heavy wiring layer is electrically connected to the signal pad region and extends into the shallow groove structure. A first substrate is disposed below the lower surface of the device substrate and between the device substrate and a second substrate. A first end of the wire is disposed in the shallow groove structure and electrically connected to the redistribution layer, and the second end is electrically connected to the first substrate and/or the second substrate. The invention also discloses a method of manufacturing a wafer stack package.

Description

Wafer stack package and method of manufacturing same

The present invention relates to a wafer packaging technique, and more particularly to a wafer stack package and a method of fabricating the same.

The wafer packaging process is an important step in the process of forming electronic products. In addition to protecting the wafer from the external environment, the chip package also provides an electrical connection path between the electronic components inside the wafer and the outside.

A conventional chip package having a sensing function, such as the fingerprint identification chip package disclosed in FIG. 1 , includes a fingerprint recognition wafer 520 disposed on a printed circuit board 510. The signal pad region of the fingerprint recognition chip 520 is electrically connected to the printed circuit board 510 through a plurality of wires 530. The encapsulation layer 540 covers the fingerprint recognition wafer 520 and the wiring 530. Since the wiring 530 protruding from the upper surface of the fingerprint recognition wafer 520 is protected by the encapsulation layer 540, the thickness of the encapsulation layer 540 is limited by the height of the wiring 530. In order to avoid the sensitivity of the sensing region 523 located in the center of the fingerprint identification wafer 520 due to the encapsulation layer 540 being too thick, the encapsulation layer 540 only covers the periphery of the fingerprint recognition wafer 520 to expose the sensing region 523. As a result, the chip package cannot form a flat surface on the fingerprint recognition wafer 520, and the size of the wafer stack package cannot be further reduced. In addition, since the wiring 530 is adjacent to the edge of the fingerprint recognition wafer 520, it is easy to cause a short circuit or a disconnection due to touching the edge of the wafer during the soldering process, resulting in a decrease in yield.

Therefore, it is necessary to find a novel chip package and a manufacturing method thereof to reduce the thickness of the package layer, thereby improving the sensing sensitivity of the chip package, and providing a chip package having a flat contact surface and a small size.

Embodiments of the present invention provide a wafer stack package including a device substrate having a first upper surface, a first lower surface, and a sidewall. The device substrate includes a shallow groove structure and a sensing region or component region and a signal pad region adjacent to the first upper surface. The shallow groove structure extends from the first upper surface toward the first lower surface along a sidewall of the device substrate. A heavy wiring layer is electrically connected to the signal pad region and extends into the shallow groove structure. A first substrate and a second substrate are disposed under the first lower surface, wherein the first substrate is located between the device substrate and the second substrate. A wire has a first end point and a second end point, wherein the first end point is disposed in the shallow groove structure and electrically connected to the redistribution layer, and the second end point is opposite to the first substrate and/or the second substrate Electrical connection.

Another embodiment of the present invention provides another wafer stack package including an upper substrate having a first upper surface, a first lower surface, and a first sidewall. The upper substrate includes a first shallow groove structure and a first signal pad region. The first shallow groove structure extends from the first upper surface toward the first lower surface along the first sidewall of the upper substrate. The lower substrate has a second upper surface, a second lower surface, and a second sidewall. The lower substrate includes a second shallow recess structure and a second signal pad region. The second shallow groove structure extends from the second upper surface toward the second lower surface along the second side wall of the lower substrate. A first redistribution layer is electrically connected to the first signal pad region and extends into the first shallow groove structure. a second redistribution layer is electrically connected to the second signal connection The pad region extends into the second shallow groove structure. A first wiring is disposed in the first shallow recess structure and electrically connected to the first redistribution layer and the lower substrate or a circuit board. A second wiring is disposed in the second shallow recess structure and electrically connected to the second redistribution layer and the upper substrate or the circuit board.

Embodiments of the present invention provide a method of fabricating a wafer stack package, including providing a device substrate having a first upper surface, a first lower surface, and a sidewall. The device substrate includes a shallow groove structure and a sensing region or component region and a signal pad region adjacent to the first upper surface. The shallow groove structure extends from the first upper surface toward the first lower surface along the sidewall of the device substrate, and has at least a first recess and a second recess, and the second recess is located below the first recess. A redistribution layer is formed which extends into the shallow recess structure and is electrically connected to the signal pad region. A first substrate and a second substrate are disposed under the first lower surface, wherein the first substrate is located between the device substrate and the second substrate. Forming a wire having a first end point and a second end point, wherein the first end point is disposed in the shallow groove structure and electrically connected to the redistribution layer, and the second end point is disposed on the first substrate or the first On the two substrates, and electrically connected thereto. The wiring, the first upper surface, the first substrate, and the second substrate are covered by an encapsulation layer to form a flattened contact surface.

100‧‧‧Device base/upper substrate

100a‧‧‧ first upper surface

100b‧‧‧ first lower surface

120‧‧‧ wafer area

140, 140', 260, 260' ‧ ‧ insulation

150, 150’ ‧ ‧ base

160, 160'‧‧‧ signal pad area

180, 180’, 320, 320’, 340, 340’ ‧ ‧ openings

200‧‧‧Sensor or component area

220, 220’‧‧‧ first notch

220a, 220a’‧‧‧ first side wall

220b, 220b’‧‧‧ first bottom

230, 230’‧‧‧ second notch

230a, 230a’‧‧‧ second side wall

230b, 230b’‧‧‧ second bottom

240, 240’‧‧‧ third notch

240a, 240a’‧‧‧ third side wall

240b, 240b’‧‧‧ third bottom

280, 280', 281, 282, 283‧‧‧ redistribution layers

300, 300’ ‧ ‧ protective layer

360, 580‧‧‧ adhesive layer

380‧‧‧Second substrate

400, 400', 400" ‧ ‧ conductive pads

440, 450, 451, 452, 453 ‧ ‧ wiring

440a, 450a, 451a, 452a, 453a‧‧‧ first endpoint

440b, 450b, 451b, 452b, 453b‧‧‧ second endpoint

The highest part of 440c, 450c‧‧

460, 540‧‧ ‧ encapsulation layer

510‧‧‧Printed circuit board

520‧‧‧Fingerprinting chip

523‧‧‧Sensing area

600‧‧‧First substrate/lower substrate

600a‧‧‧Second upper surface

600b‧‧‧second lower surface

D1, D2, D3‧‧‧ Depth

H1‧‧‧ thickness

H2‧‧‧ distance

Figure 1 is a schematic cross-sectional view showing a conventional chip package.

2A to 2B, 2C-1, 2D to 2F are schematic cross-sectional views showing a method of manufacturing a wafer stack package according to an embodiment of the present invention.

2C-2 and 2C-3 are schematic cross-sectional views showing a chip package in accordance with various embodiments of the present invention.

3 and 4 are schematic cross-sectional views showing a wafer stack package in accordance with various embodiments of the present invention.

5 and 6 are partial plan views showing a wafer stack package in accordance with various embodiments of the present invention.

The manner of making and using the embodiments of the present invention will be described in detail below. It should be noted, however, that the present invention provides many inventive concepts that can be applied in various specific forms. The specific embodiments discussed herein are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the invention and are not to be construed as a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is referred to or on a second material layer, the first material layer is in direct contact with or separated from the second material layer by one or more other material layers.

The chip package of one embodiment of the present invention can be used to package a sensing wafer, such as a biometric wafer such as a fingerprint reader. However, the application is not limited thereto. For example, in the embodiment of the chip package of the present invention, it can be applied to various active or passive elements, digital circuits or analog circuits. The electronic components of the integrated circuit are, for example, related to opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, or utilizing heat, light, A physical sensor that measures physical quantities such as capacitance and pressure to measure. In particular, you can choose to use wafer level packaging (wafer scale) Package, WSP) Part or all of the process for image sensing components, light-emitting diodes (LEDs), solar cells, RF circuits, accelerators, gyroscopes Semiconductor wafers such as (gyroscopes), micro actuators, surface acoustic wave devices, process sensors, or ink printer heads are packaged.

The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above wafer level packaging process is also applicable to a chip package in which a plurality of wafers having integrated circuits are arranged by a stack to form multi-layer integrated circuit devices.

Please refer to FIG. 2F, which illustrates a cross-sectional view of a wafer stack package according to an embodiment of the invention. To simplify the drawing, only a portion of the wafer stack package is shown here. In this embodiment, the wafer stack package includes a device substrate/upper substrate 100, a redistribution layer (RDL) 280, a first substrate 600, a second substrate 380, and a wire 440. The device substrate 100 has a first upper surface 100a and a first lower surface 100b. In one embodiment, the device substrate 100 includes an insulating layer 140 adjacent to the first upper surface 100a and a lower layer substrate 150 adjacent to the first lower surface 100b. In general, the insulating layer 140 may be an interlayer dielectric layer (interlayer) Dielectric, ILD), inter-metal dielectric (IMD) and covered passivation. In this embodiment, the insulating layer 140 Inorganic materials may be included, such as cerium oxide, cerium nitride, cerium oxynitride, metal oxides or combinations of the foregoing or other suitable insulating materials. In this embodiment, the underlying substrate 150 can comprise germanium or other semiconductor material.

In the present embodiment, the device substrate 100 includes a signal pad region 160 and a sensing region or component region 200 that is adjacent to the first upper surface 100a. In one embodiment, the signal pad region 160 includes a plurality of conductive pads, which may be a single conductive layer or a conductive layer structure having multiple layers. To simplify the drawing, only a single conductive layer is exemplified herein, and only one conductive pad in the insulating layer 140 is illustrated as an example. In this embodiment, one or more openings 180 may be included in the insulating layer 140 to expose corresponding conductive pads.

In one embodiment, the device area or sensing area 200 of the device substrate 100 includes a sensing element that can be used to sense biological features, that is, the device substrate 100 is a biosensing wafer (eg, a fingerprint identification wafer). . In another embodiment, the device substrate 100 is used to sense environmental features. For example, the device substrate 100 may include a temperature sensing component, a humidity sensing component, a pressure sensing component, a capacitive sensing component, or other suitable Sensing element. In yet another embodiment, device substrate 100 can include an image sensing element. In one embodiment, the sensing component in the device substrate 100 can be electrically connected to the signal pad region 160 through an interconnect structure (not shown) in the insulating layer 140.

In the embodiment, the device substrate 100 further includes a shallow groove structure, which is composed of a first notch 220, a second notch 230 and a third notch 240. The first recess 220 extends from the first upper surface 100a toward the first lower surface 100b along the sidewall of the device substrate 100 to expose the lower substrate 150. The first recess 220 includes a first sidewall 220a and a first bottom 220b. In an embodiment, the first The first sidewall 220a of the recess 220 abuts the insulating layer 140 (ie, the first sidewall 220a is an edge of the insulating layer 140). In other embodiments, the first sidewall 220a can extend further into the underlying substrate 150. In the present embodiment, the depth D1 of the first recess 220 is no more than 15 micrometers. In an embodiment, the first sidewall 220a may be substantially perpendicular to the first upper surface 100a. For example, the angle between the first sidewall 220a of the first recess 220 and the first upper surface 100a may be approximately 84°. To the range of 90°. In other embodiments, the first sidewall 220a can be substantially inclined to the first upper surface 100a. For example, the angle between the first sidewall 220a of the first recess 220 and the first upper surface 100a can be approximately 55°. To the range of 90°.

The second recess 230 extends from the first bottom portion 220b of the first recess 220 toward the first lower surface 100b along the sidewall of the device substrate 100, and includes a second sidewall 230a and a second bottom portion 230b. In an embodiment, the second sidewall 230a can be substantially perpendicular to the first upper surface 100a. In other embodiments, the second sidewall 230a can be substantially oblique to the first upper surface 100a. In an embodiment, the second sidewall 230a of the second recess 230 abuts the substrate 150. In an embodiment, the depth D2 of the second recess 230 (indicated in FIG. 2B) is less than the depth D1 of the first recess 220. In an embodiment, the width of the second bottom portion 230b is less than the width of the first bottom portion 220b.

The third recess 240 extends from the second bottom portion 230b of the second recess 230 toward the first lower surface 100b along the sidewall of the device substrate 100, and includes a third sidewall 240a and a third bottom portion 240b. In an embodiment, the third sidewall 240a can be substantially perpendicular to the first upper surface 100a. In other embodiments, the third sidewall 240a can be substantially oblique to the first upper surface 100a. In an embodiment, the depth D3 of the third recess 240 (indicated in FIG. 2B) is equal to the depth D2 of the second recess 230. In other embodiments, the depth D3 can be less than or greater than the depth D2. In an embodiment, The width of the third bottom portion 240b is equal to the width of the second bottom portion 230b. In other embodiments, the width of the third bottom portion 240b can be less than or greater than the width of the second bottom portion 230b.

In an embodiment, an insulating layer 260 may be optionally disposed to be compliant with the first upper surface 100a of the device substrate 100. The insulating layer 260 extends to the third sidewall 240a and the third bottom portion 240b via the first recess 220 and the second recess 230, and exposes a portion of the signal pad region 160. In the present embodiment, the insulating layer 260 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination thereof, or other suitable insulating materials.

A patterned redistribution layer 280 is compliantly disposed on the insulating layer 260. The redistribution layer 280 extends into the opening 180 and the first sidewall 220a and the first bottom 220b of the first recess 220. The redistribution layer 280 can be electrically connected to the signal pad region 160 via the opening 180. In other embodiments, the redistribution layer 280 can further extend onto the second bottom 230b or the third bottom 240b. In an embodiment, when the substrate 150 includes a semiconductor material, the redistribution layer 280 can be electrically insulated from the semiconductor material through the insulating layer 260. In an embodiment, the redistribution layer 280 may include copper, aluminum, gold, platinum, nickel, tin, a combination of the foregoing, a conductive polymer material, a conductive ceramic material (eg, indium tin oxide or indium zinc oxide) or other suitable Conductive material.

A protection layer 300 is disposed on the redistribution layer 280 and the insulating layer 260 and extends into the first recess 220, the second recess 230, and the third recess 240. The protective layer 300 includes one or more openings therein to expose a portion of the redistribution layer 280. In the present embodiment, the protective layer 300 includes openings 320 and 340 that expose the redistribution layer 280 on the signal pad region 160 and the first recess 220, respectively. In another embodiment, the protective layer 300 may include only the opening 340. For example, the redistribution layer 280 on the signal pad region 160 is completely covered by the protective layer 300. cover. In other embodiments, the protective layer 300 can include a plurality of openings 340 that expose portions of the redistribution layer 280 within the first recess 220, the second recess 230, and the third recess 240, respectively. In the present embodiment, the protective layer 300 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination thereof, or other suitable insulating materials.

The first substrate/lower substrate 600 has a second upper surface 600a and a second lower surface 600b, and is attached to the first lower surface 100b of the device substrate 100 through an adhesive layer (eg, glue) 580. . In an embodiment, the first substrate 600 is a wafer (eg, a processor) or an interposer. Moreover, the size of the first substrate 600 is larger than the size of the device substrate 100. In an embodiment, the first substrate 600 has the same structure as the device substrate 100. For example, the first substrate 600 includes an insulating layer 140' adjacent to the second upper surface 600a and adjacent to the second lower surface 600b. The lower layer substrate 150'. Furthermore, the first substrate 600 further includes a signal pad region 160' adjacent to the second upper surface 600a and a shallow groove structure along the sidewall of the first substrate 600 from the second upper surface 600a. The second lower surface 600b extends. The shallow groove structure is composed of a first recess 220', a second recess 230' and a third recess 240'. In other embodiments, the structure of the first substrate 600 can be different from the structure of the device substrate 100.

In addition, when the structure of the first substrate 600 is the same as that of the device substrate 100, an insulating layer 260', a redistribution layer 280', and a protective layer 300' are sequentially disposed on the second upper surface 600a, and are located at the first The substrate 600 is between the device substrate 100. Components 140', 150', 160', 180', 220', 220a', 220b', 230', 230a', 230b', 240', 240a', 240b', 260 located on or in the first substrate 600 ', 280', 300', 320', 340' are the same as the device The components 140, 150, 160, 180, 220, 220a, 220b, 230, 230a, 230b, 240, 240a, 240b, 260, 280, 300, 320, 340 on or in the substrate 100 are omitted herein.

The second substrate 380 is attached to the second lower surface 600b through an adhesive layer (eg, glue) 360. In this embodiment, the second substrate 380 can be a wafer, an interposer or a circuit board. Taking a circuit board as an example, the circuit board can have one or more conductive pads 400 adjacent to its upper surface. Similarly, in an embodiment, the conductive pad 400 can be a single conductive layer or a conductive layer structure having multiple layers. To simplify the drawing, only two conductive pads 400 composed of a single conductive layer are illustrated here as an example.

Wiring 440 has a first end point 440a and a second end point 440b. The first end point 440a is disposed in the shallow groove structure of the device substrate 100, and is electrically connected to the redistribution layer 280 of the first bottom portion 220b through the opening 340. The second end point 440b is disposed on one of the conductive pads 400 of the second substrate 380 and electrically connected thereto. In an embodiment, one of the highest portions 440c of the wire 440 protrudes from the first upper surface 100a. In other embodiments, the highest portion 440c of the wire 440 can be lower than the first upper surface 100a. In the present embodiment, the second end 440b of the wire 440 is the starting point of the weld. Again, wiring 440 can include gold or other suitable electrically conductive material.

In another embodiment, when the redistribution layer 280 on the device substrate 100 extends to the second bottom portion 230b, and the opening 340 in the protective layer 300 is located in the second recess 230, the first end point 440a may be disposed on the device. The second recess 230 of the substrate 100 is electrically connected to the redistribution layer 280 extending to the second bottom portion 230b through the opening 340. In other embodiments, the redistribution layer 280 on the device substrate 100 extends When the third bottom portion 240b is extended and the opening 340 in the protective layer 300 is located in the second recess 230 or the third recess 240, the first end point 440a may be disposed on the second recess 230 or the third of the device substrate 100. In the recess 240, the depth of the second recess 230 or the third recess 240 may be greater than the depth of the first recess 220, and the lateral width of the second bottom 230b or the third bottom 240b may be greater than that of the first bottom 220b. Horizontal width.

In this embodiment, the wafer stack package further includes a wire 450 having a first end point 450a and a second end point 450b. The first end point 450a is disposed in the shallow groove structure of the first substrate 600, and is electrically connected to the redistribution layer 280' of the first bottom portion 220b through the opening 340'. The second end point 450b is disposed on the other conductive pad 400 of the second substrate 380 and electrically connected thereto. In an embodiment, one of the highest portions 450c of the wire 450 protrudes from the first upper surface 100a. In other embodiments, the highest portion 450c of the wire 450 can be lower than the first upper surface 100a. In the present embodiment, the second end 450b of the wire 450 is the starting point of the weld. Again, wiring 450 can include gold or other suitable electrically conductive material. Similar to the second end 440b of the wiring 440, in other embodiments, the second end 450b of the wiring 450 can be disposed within the second recess 230' or the third recess 240' of the first substrate 600.

An encapsulant 460 can selectively cover the wires 440 and 450, the first substrate 600 and the second substrate 380 or further extend onto the first upper surface 100a to form over the sensing region or the component region 200. A flattened contact surface. In the present embodiment, the encapsulation layer 460 may be composed of a molding material or a sealing material.

In an embodiment, when the highest portion 440c of the wiring 440 protrudes from the first upper surface 100a, the encapsulation layer 460 is thickly covered in the sensing region or the component region 200. The degree H1 is determined by the difference between the distance H2 between the highest portion 440c of the wiring 440 and the first bottom 220b of the first recess 220 and the depth D1 of the first recess 220 (i.e., H2-D1). Therefore, by adjusting the depth D1 of the first recess 220, the cover thickness H1 of the encapsulation layer 460 in the sensing region or the component region 200 can be reduced, so that the sensitivity of the sensing region or the component region 200 can be improved.

In an embodiment, a decorative layer (not shown) may be additionally disposed on the encapsulation layer 460, and may have a color according to design requirements to display an area having a sensing function. A protective layer (not shown, such as a sapphire substrate or a hard rubber) may be additionally disposed on the decorative layer to further provide a wear resistant, scratch resistant, and highly reliable surface, thereby avoiding the use of a wafer stack package. The sensing device is contaminated or destroyed during the sensing function.

Referring to FIGS. 3 and 4, there are shown cross-sectional views of a wafer stack package in accordance with various embodiments of the present invention, wherein components in the same reference numerals are used for the same reference numerals and the description thereof is omitted. To simplify the drawing, only a portion of the wafer stack package is shown here. The structure of the wafer stack package in FIG. 3 is similar to the structure of the wafer stack package in FIG. 2F, with the difference that the width of the second bottom portion 230b in the device substrate 100 in FIG. 3 is greater than that in the device substrate 100. The width of a bottom 220b. At the same time, the redistribution layer 280 further extends to the second sidewall 230a and the second bottom portion 230b in the device substrate 100. The opening 340 is located in the second recess 230 in the device substrate 100, and the first end point 440a of the wiring 440 is formed in The redistribution layer 280 extends to the second bottom portion 230b and is electrically connected thereto through the opening 340. As such, the highest portion 440c of the wiring 440 can be lower than the first upper surface 100a.

The structure of the wafer stack package in FIG. 4 is similar to that in FIG. The structure of the wafer stack package differs in that the first recess 220 in the device substrate 100 in FIG. 4 extends further into the substrate 150 such that the highest portion 440c of the wire 440 can be lower than the first upper surface 100a. Moreover, the second end 440b of the wire 440 is disposed in the shallow groove structure in the first substrate 600. For example, the second end point 440b is disposed on the first bottom portion 220b' extending into the first substrate 600. The wiring layer 280' is rewired and electrically connected thereto through the opening 340'. In addition, the redistribution layer 280' on the first substrate 600 further extends to the second sidewall 230a' and the second bottom portion 230b', and the protective layer 300' on the first substrate 600 further includes another layer exposing the redistribution layer 280' An opening 340'. The first terminal end 450a of the wiring 450 is disposed on the redistribution layer 280' extending to the second bottom portion 230b' of the first substrate 600, and is electrically connected thereto through the opening 340'.

Referring to FIGS. 5 and 6, a partial plan view of a wafer stack package according to various embodiments of the present invention is illustrated, wherein the same reference numerals are used for components in FIGS. 2F, 3, and 4, and the description thereof is omitted. . Similar to the wafer stack package of FIGS. 2F, 3 and 4, the wafer stack package of FIGS. 5 and 6 includes a device substrate, a first substrate 600 and a second substrate 380, which are vertically stacked on an encapsulation layer. Inside. To simplify the drawing, the device substrate and the encapsulation layer on the first substrate 600 are not shown in FIGS. 5 and 6.

As shown in Fig. 5, the first recess 220', the second recess 230', and the third recess 240' extend laterally along an edge of the first substrate 600. The redistribution layers 281, 282, and 283 are disposed on the upper surface of the first substrate 600, and are electrically connected to the corresponding signal pad regions 160' of the first substrate 600, and extend to the first recess 220' and the second recess, respectively. Port 230' and third recess 240. In order to clearly show the relative positions of the components in the wafer stack package, the signal pad region 160' and the weight are indicated by broken lines. The outline of the wiring layers 281, 282, and 283.

The protective layer 300' covers the first substrate 600, and includes a plurality of openings 340' exposing a portion of the redistribution layer 281 in the first recess 220', and a portion of the redistribution layer 282 in the second recess 230'. Part and a portion of the redistribution layer 283 in the third recess 240'. The redistribution layers 281, 282, and 283 are electrically connected to the conductive pads 400, 400', and 400" of the second substrate 380 through the wires 451, 452, and 453, respectively. For example, the first end point 451a of the wiring 451 is disposed at the first The second wiring terminal 451b is electrically connected to the conductive pad 400 and electrically connected thereto. The first terminal 452a of the wiring 452 is electrically connected to the redistribution layer 281 in the recess 220'. The second wiring end 452b is disposed on the conductive pad 400' and electrically connected thereto. The wiring 453 is disposed on the redistribution layer 282 in the second recess 230'. The first end point 453a is disposed on the redistribution layer 283 in the third recess 240' and electrically connected thereto through the opening 340', and the second end 453b of the wiring 453 is disposed on the conductive pad 400" and electrically connected thereto connection. In the present embodiment, the second end points 451b, 452b, and 453b are the starting points of the welding.

The structure of the wafer stack package in FIG. 6 is similar to the structure of the wafer stack package in FIG. 5, except that all of the redistribution layers 281, 282, and 283 in FIG. 6 extend to the third notch 240'. . Furthermore, the protective layer 300' in the second recess 230' includes two openings 340' exposing portions of the redistribution layers 281 and 282, respectively, and the protective layer 300' in the third recess 240' includes Three openings 340' expose portions of the redistribution layers 281, 282, and 283, respectively.

In one embodiment, the portions of the first recess 220', the second recess 230', and the third recess 240' are exposed by the redistribution layer 281 through three connections. The 451 is electrically connected to the same conductive pad 400. The portion of the red wiring layer 282 exposed in the second recess 230' is electrically connected to the corresponding conductive pad 400' through the wiring 452. Moreover, the exposed portions of the redistribution layers 282 and 283 in the third recess 240' are electrically connected to the same conductive pad 400" through the wires 452 and 453, respectively.

In addition, although not shown in the drawings, it can be understood that as long as the redistribution layer is electrically connected to the conductive pad, the redistribution layer, the opening in the protective layer, and the wiring may have other configurations. Furthermore, the wiring arrangement between the first substrate and the second substrate in FIGS. 5 and 6 can also be applied between the device substrate and the first substrate or between the device substrate and the second substrate.

According to the above-described embodiment of the present invention, since the device substrate 100 includes a shallow groove structure, and the first end point 440a of the wire 440 is disposed therein, the distance between the highest portion 440c of the wire 440 and the first upper surface 100a can be shortened, It is therefore possible to reduce the thickness H1 of the encapsulation layer 460 covering the sensing region or component region 200. Furthermore, the thickness H1 can be further reduced by adjusting the highest portion 440c of the wiring 440 to be lower than the first upper surface 100a. As a result, the sensitivity of the sensing region or component region 200 and the quality of the wafer stack package can be improved. Furthermore, the size of the wafer stack package can be further reduced and a flattened contact surface can be formed over the sensing region or component region 200.

Hereinafter, a method of manufacturing a wafer stack package according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2F, wherein 2A to 2B, 2C-1, 2D to 2F are diagrams showing a wafer stack package according to an embodiment of the present invention. A schematic cross-sectional view of a manufacturing method, and FIGS. 2C-2 and 2C-3 are schematic cross-sectional views of a chip package in accordance with various embodiments of the present invention.

Referring to FIG. 2A, a device having a plurality of wafer regions 120 is provided. Substrate 100 (eg, a wafer). To simplify the drawing, only a portion of a single wafer region 120 is depicted herein. The device substrate/upper substrate 100 has a first upper surface 100a and a first lower surface 100b. In an embodiment, the device substrate 100 includes an insulating layer 140 adjacent to the first upper surface 100a and a lower layer substrate 150 adjacent to the first lower surface 100b. Generally, the insulating layer 140 may be an interlayer dielectric layer (ILD). ), an inter-metal dielectric layer (IMD) and a covered passivation layer. In the present embodiment, the insulating layer 140 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination of the foregoing or other suitable insulating materials. In this embodiment, the underlying substrate 150 can comprise germanium or other semiconductor material.

In the present embodiment, the device substrate 100 in each wafer region 120 includes a signal pad region 160 and a sensing region or component region 200 that is adjacent to the first upper surface 100a. In one embodiment, the signal pad region 160 includes a plurality of conductive pads, which may be a single conductive layer or a conductive layer structure having multiple layers. To simplify the drawing, only a single conductive layer is exemplified herein, and only one conductive pad in the insulating layer 140 is illustrated as an example. In this embodiment, one or more openings 180 may be included in the insulating layer 140 to expose corresponding conductive pads.

In the present embodiment, the device area or sensing area 200 of the device substrate 100 includes a sensing component that can be used to sense biological features, that is, the device substrate 100 is a biosensing wafer (eg, a fingerprint identification wafer). . In another embodiment, the device substrate 100 is used to sense environmental features. For example, the device substrate 100 may include a temperature sensing component, a humidity sensing component, a pressure sensing component, a capacitive sensing component, or other suitable Sensing element. In yet another embodiment, device substrate 100 can include an image sensing element. In an embodiment, the sensing component in the device substrate 100 can be connected to the signal through an interconnect structure (not shown) in the insulating layer 140. The pad area 160 is electrically connected.

Please refer to FIG. 2B, which can be processed through a lithography process and an etching process (for example, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, or other suitable process) or a cutting process in each wafer area. A shallow groove structure is formed in the device substrate 100 within 120. In one embodiment, the shallow groove structure is formed by a plurality of lithography and etching processes or a dicing process, and is composed of a first notch 220, a second notch 230, and a third notch 240. The first recess 220 extends from the first upper surface 100a toward the first lower surface 100b along a scribe line (not shown) between the wafer regions 120 and passes through the insulating layer 140 to expose the lower substrate 150. The first recess 220 includes a first sidewall 220a and a first bottom 220b. In an embodiment, the first sidewall 220a of the first recess 220 abuts the insulating layer 140 (ie, the first sidewall 220a is an edge of the insulating layer 140). In other embodiments, the first sidewall 220a can extend further into the underlying substrate 150. In the present embodiment, the depth D1 of the first recess 220 is no more than 15 micrometers. In an embodiment, when the first recess 220 is formed by etching the insulating layer 140, the first sidewall 220a may be substantially perpendicular to the first upper surface 100a, for example, the first sidewall of the first recess 220. The angle between 220a and the first upper surface 100a may be in the range of approximately 84° to 90°. In other embodiments, when the first recess 220 is formed by cutting the insulating layer 140, the first sidewall 220a may be substantially inclined to the first upper surface 100a, for example, the first sidewall of the first recess 220. The angle between the 220a and the first upper surface 100a may be in the range of approximately 55° to 90°.

The second recess 230 extends from the first bottom portion 220b of the first recess 220 toward the first lower surface 100b along a scribe line (not shown) between the wafer regions 120, and includes a second sidewall 230a and a second Bottom 230b. In an embodiment, the second side The wall 230a can be substantially perpendicular to the first upper surface 100a. In other embodiments, the second sidewall 230a can be substantially oblique to the first upper surface 100a. In an embodiment, the second sidewall 230a of the second recess 230 abuts the substrate 150. In an embodiment, the depth D2 of the second recess 230 is smaller than the depth D1 of the first recess 220. In an embodiment, the width of the second bottom portion 230b is less than the width of the first bottom portion 220b.

The third recess 240 extends from the second bottom portion 230b of the second recess 230 toward the first lower surface 100b along a scribe line (not shown) between the wafer regions 120, and includes a third sidewall 240a and a third portion. Bottom 240b. In an embodiment, the third sidewall 240a can be substantially perpendicular to the first upper surface 100a. In other embodiments, the third sidewall 240a can be substantially oblique to the first upper surface 100a. In an embodiment, the depth D3 of the third recess 240 is equal to the depth D2 of the second recess 230. In other embodiments, the depth D3 can be less than or greater than the depth D2. In an embodiment, the width of the third bottom portion 240b is equal to the width of the second bottom portion 230b. In other embodiments, the width of the third bottom portion 240b can be less than or greater than the width of the second bottom portion 230b.

Referring to FIG. 2C-1, the compliance may be performed on the first upper surface 100a of the device substrate 100 through a deposition process (eg, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process). An insulating layer 260 is formed. The insulating layer 260 extends into the opening 180 of the insulating layer 140 and extends to the third sidewall 240a and the third bottom portion 240b via the first recess 220 and the second recess 230. In the present embodiment, the insulating layer 260 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination thereof, or other suitable insulating materials.

Then, through the lithography process and the etching process (for example, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, or His suitable process) removes the insulating layer 260 within the opening 180 to expose portions of the signal pad region 160. Then, through the deposition process (for example, coating process, physical vapor deposition process, chemical vapor deposition process, electroplating process, electroless process or other suitable process), lithography process and etching process, on the insulating layer 260 A patterned redistribution layer 280 is formed.

The redistribution layer 280 is compliantly extended into the opening 180 and the first sidewall 220a and the first bottom 220b of the first recess 220, and the exposed signal pad region 160 can be electrically connected via the opening 180. In an embodiment, the redistribution layer 280 does not extend to the edge of the first bottom 220b of the first recess 220. In other embodiments, the redistribution layer 280 may further extend to the second bottom portion 230b or the third bottom portion 240b, and the depth of the second recess 230 or the third recess 240 may be greater than the depth of the first recess 220. And the lateral width of the second bottom portion 230b or the third bottom portion 240b may be greater than the lateral width of the first bottom portion 220b. In an embodiment, when the substrate 150 includes a semiconductor material, the redistribution layer 280 can be electrically insulated from the semiconductor material through the insulating layer 260. In an embodiment, the redistribution layer 280 may include copper, aluminum, gold, platinum, nickel, tin, a combination of the foregoing, a conductive polymer material, a conductive ceramic material (eg, indium tin oxide or indium zinc oxide) or other suitable Conductive material.

In another embodiment, as shown in FIG. 2C-2, when the conductive pad of the signal pad region 160 selectively extends toward the sidewall of the insulating layer 140, and the insulating layer 140 completely covers the conductive pad of the signal pad region 160 ( That is, when the insulating layer 140 does not have the opening 180) in the second C-1 figure, the insulating layer 260 and the insulating layer 140 outside the signal pad region 160 may be removed through the dicing process to expose the signal pad region 160. The side walls of the conductive pads. Furthermore, the sidewalls of the conductive pads are coplanar with the edges of the insulating layer 140. As a result, the redistribution layer 280 extending to the shallow groove structure is directly Contact the exposed sidewalls of the conductive pad.

In other embodiments, as shown in FIG. 2C-3, the sidewall of the conductive pad of the signal pad region 160 may be exposed at the same time by the step of forming the first recess 220, so that the sidewall of the conductive pad and the first recess are The first side wall 220a of the port 220 is coplanar. After the insulating layer 260 is formed in the shallow recess structure, the insulating layer 260 extending to the first sidewall 220a may be removed through a dicing process to expose the sidewalls of the conductive pad again. As such, the redistribution layer 280 can directly contact the exposed sidewalls of the conductive pads.

After forming the redistribution layer 280 (as shown in Figures 2C-1 to 2C-3), the deposition process can be performed (for example, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process) A protective layer 300 is formed conformally on the redistribution layer 280 and the insulating layer 260. Here, only the structure in FIG. 2C-1 is taken as an example, and the protective layer 300 extends into the first recess 220, the second recess 230, and the third recess 240 as shown in FIG. 2D. In the present embodiment, the protective layer 300 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination of the foregoing or other suitable insulating materials.

Then, one or more openings may be formed in the protective layer 300 through a lithography process and an etching process (eg, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, or other suitable process). A portion of the redistribution layer 280 is exposed. In the present embodiment, openings 320 and 340 are formed in the protective layer 300 to expose the redistribution layer 280 on the signal pad region 160 and in the first recess 220, respectively. In another embodiment, only the opening 340 may be formed within the protective layer 300. In other embodiments, the protective layer 300 can include a plurality of openings 340 exposing the first notch 220, the second notch 230, and the third notch 240, respectively. Part of the rewiring layer 280 inside. It will be understood that the number and location of the openings in the protective layer 300 are not limited to this depending on the design requirements.

Next, along the dicing streets (not shown) between the wafer regions 120, the device substrate 100 is subjected to a dicing process to form a plurality of individual wafers. After the cutting process is performed, the first recess 220 in the device substrate 100 of each wafer extends from the first upper surface 100a toward the first lower surface 100b along the sidewall of the device substrate 100. Furthermore, the second recess 230 extends from the first bottom 220b of the first recess 220 toward the first lower surface 100b along the sidewall of the device substrate 100, and the third recess 240 follows the sidewall of the device substrate 100 from the second The second bottom portion 230b of the recess 230 extends toward the first lower surface 100b.

Referring to FIG. 2E, a first substrate/lower substrate 600 and a second substrate 380 are provided. A first substrate 600 can be attached to the upper surface of the second substrate 380 through an adhesive layer (eg, adhesive) 360. In the present embodiment, the first substrate 600 is a wafer (eg, a processor) or an interposer. In an embodiment, the structure of the first substrate 600 is the same as that of the device substrate 100, and the manufacturing method of the first substrate 600 may be the same or similar to the manufacturing method of the device substrate 100 described above. Components 140', 150', 160', 180', 220', 220a', 220b', 230', 230a', 230b', 240', 240a', 240b', 260 located on or in the first substrate 600 ', 280', 300', 320', 340' are respectively identical to the components 140, 150, 160, 180, 220, 220a, 220b, 230, 230a, 230b, 240, 240a located on or within the device substrate 100, 240b, 260, 280, 300, 320, 340, and the description thereof is omitted here. In other embodiments, the structure of the first substrate 600 can be different from the structure of the device substrate 100.

In this embodiment, the second substrate 380 can be a wafer, an interposer, or Circuit board. Taking a circuit board as an example, the circuit board can have one or more conductive pads 400 adjacent to its upper surface. Similarly, in an embodiment, the conductive pad 400 can be a single conductive layer or a conductive layer structure having multiple layers. To simplify the drawing, only two conductive pads 400 composed of a single conductive layer are illustrated here as an example.

Next, the device substrate 100 of the individual wafers can be attached to the first upper surface 600b of the first substrate 600 through an adhesive layer (eg, adhesive) 580. In the present embodiment, the size of the first substrate 600 is larger than the size of the device substrate 100 such that the device substrate 100 does not shield the shallow groove structure of the first substrate 600.

Referring to FIG. 2F, wirings 440 and 450 are formed on the second substrate 380 by a wire bonding process, which are electrically connected to the device substrate 100 and the first substrate 600, respectively. For example, the second terminal 440b of the wiring 440 may be formed on one of the conductive pads 400 of the second substrate 380, and the first end 440a of the wiring 440 is subsequently formed on the first bottom 220b extending to the device substrate 100. The wiring layer 280 is electrically connected to the wiring layer 280. Similarly, the second end 450b of the wiring 450 can be formed on the other conductive pad 400 of the second substrate 380, and the first end 450a of the wiring 450 is subsequently formed on the first bottom 220b extending to the first substrate 600. 'The heavy wiring layer 280' is electrically connected thereto. In the present embodiment, the second end 440b of the wire 440 and/or the second end 450b of the wire 450 are the starting points for welding. Further, wires 440 and 450 can include gold or other suitable electrically conductive material.

In an embodiment, the highest portion 440c of the wire 440 protrudes from the first upper surface 100a. In other embodiments, the highest portion 440c of the wire 440 can be lower than the first upper surface 100a. In an embodiment, one of the highest portions 450c of the wire 450 protrudes from the first upper surface 100a. In other embodiments, the wiring 450 is the most The high portion 450c can be lower than the first upper surface 100a.

Next, as shown in FIG. 2F, an encapsulation layer 460 may be formed on the first upper surface 100a of the device substrate 100 through a molding process or other suitable process, which may selectively cover the wires 440 and 450. The first substrate 600 and the second substrate 380 or further extend onto the first upper surface 100a to form a flattening contact surface over the sensing region or the component region 200. In the present embodiment, the encapsulation layer 460 may be formed of a shaped material or a sealing material.

In an embodiment, when the highest portion 440c of the wiring 440 protrudes from the first upper surface 100a, the cover thickness H1 of the encapsulation layer 460 in the sensing region or the component region 200 is determined by the highest portion 440c of the wiring 440 and the first bottom portion. The difference between the distance H2 between 220b and the depth D1 of the first notch 220 (ie, H2-D1). Therefore, by adjusting the depth D1 of the first recess 220, the cover thickness H1 of the encapsulation layer 460 in the sensing region or the component region 200 can be reduced, so that the sensitivity of the sensing region or the component region 200 can be improved.

Then, a decorative layer (not shown) may be formed on the encapsulation layer 460 through a deposition process (eg, a coating process or other suitable process), which may have a color according to design requirements to display a sensing function. region. Then, a protective layer (not shown, such as a sapphire substrate or a hard layer) may be formed on the decorative layer 480 through a deposition process (eg, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process). Plastic) to further provide a wear-resistant, scratch-resistant and highly reliable surface.

According to the above embodiment of the present invention, since the first end point 440a of the wiring 440 is formed in the shallow groove structure of the device substrate 100, the thickness H1 of the encapsulation layer 460 covering the sensing region or the element region 200 can be lowered, thereby enhancing the feeling Zone or element The sensitivity of the area 200 is reduced and the size of the wafer stack package is reduced.

Moreover, since the highest portion 440c can be lowered as much as possible by forming a plurality of continuous notches in the device substrate 100, instead of forming only a single notch and extending it directly downward, it is possible to avoid removing excess substrate material, thereby making the device The substrate 100 is capable of maintaining sufficient structural strength and preventing undercutting of the interface between the insulating layer 140 and the substrate 150 due to over-etching. Moreover, by forming the second notch 230 or forming the second notch 230 and the second notch 240, the distance between the wire 440 and the first bottom portion 220b of the first notch 220 can be increased, thereby reducing the welding process. The probability that the wire 440 is shorted or broken due to touching the edge of the first notch 220. In this way, the quality of the wafer stack package can be improved.

While the invention has been described above in terms of the preferred embodiments thereof, which are not intended to limit the invention, the invention may be modified and combined with the various embodiments described above without departing from the spirit and scope of the invention. example.

100‧‧‧Device base/upper substrate

100a‧‧‧ first upper surface

100b‧‧‧ first lower surface

140, 140', 260, 260' ‧ ‧ insulation

150, 150’ ‧ ‧ base

160, 160'‧‧‧ signal pad area

180, 180’, 320, 320’, 340, 340’ ‧ ‧ openings

200‧‧‧Sensor or component area

220, 220’‧‧‧ first notch

220a, 220a’‧‧‧ first side wall

220b, 220b’‧‧‧ first bottom

230, 230’‧‧‧ second notch

230a, 230a’‧‧‧ second side wall

230b, 230b’‧‧‧ second bottom

240, 240’‧‧‧ third notch

240a, 240a’‧‧‧ third side wall

240b, 240b’‧‧‧ third bottom

280, 280'‧‧‧Rewiring layer

300, 300’ ‧ ‧ protective layer

360, 580‧‧‧ adhesive layer

380‧‧‧Second substrate

400‧‧‧Electrical mat

440, 450‧‧‧ wiring

440a, 450a‧‧‧ first endpoint

440b, 450b‧‧‧ second endpoint

The highest part of 440c, 450c‧‧

460‧‧‧Encapsulation layer

600‧‧‧First substrate/lower substrate

600a‧‧‧Second upper surface

600b‧‧‧second lower surface

D1‧‧ depth

H1‧‧‧ thickness

H2‧‧‧ distance

Claims (23)

A wafer stack package comprising: a device substrate having a first upper surface, a first lower surface, and a sidewall, wherein the device substrate comprises a shallow recess structure and a sensing adjacent to the first upper surface a region or an element region and a signal pad region, and wherein the shallow groove structure extends from the first upper surface toward the first lower surface along the sidewall of the device substrate; a redistribution layer electrically connecting the signal connection a pad region extending into the shallow groove structure; a first substrate and a second substrate disposed under the first lower surface, wherein the first substrate is located between the device substrate and the second substrate; and a wiring Having a first end point and a second end point, wherein the first end point is disposed in the shallow groove structure and electrically connected to the redistribution layer, and wherein the second end point and the first substrate / or the second substrate is electrically connected. The wafer stack package of claim 1, wherein the device substrate is a biometric wafer. The wafer stack package of claim 2, wherein the biometric wafer is a fingerprint identification wafer. The wafer stack package of claim 1, wherein the first substrate is a wafer or an interposer. The wafer stack package of claim 1, wherein the second substrate is a wafer, an interposer or a circuit board. The wafer stack package of claim 1, wherein the shallow groove structure comprises: a first recess having a first sidewall and a first bottom, wherein the redistribution layer extends to the first sidewall and the first bottom; and a second recess is located below the first recess, and There is a second sidewall and a second bottom, wherein the second recess extends from the first bottom toward the first lower surface. The wafer stack package of claim 6, wherein the first bottom has a lateral width greater than the second bottom, and wherein the first end of the wire is disposed at the weight extending to the first bottom On the wiring layer. The wafer stack package of claim 6, wherein the redistribution layer extends further to the second sidewall and the second bottom, and the first end of the wiring is disposed to extend to the second bottom And on the redistribution layer, wherein the second bottom has a lateral width greater than the first bottom. The wafer stack package of claim 6, wherein the device substrate comprises an insulating layer and a lower substrate, and wherein the first sidewall of the first recess abuts the insulating layer and a portion of the underlying substrate And the second sidewall of the second recess abuts the underlying substrate within the substrate of the device. The wafer stack package of claim 1, wherein the second end of the wire is a starting point of soldering. The wafer stack package of claim 1, wherein the first substrate has a second upper surface, a second lower surface, and a sidewall, and wherein the first substrate comprises a further shallow recess structure. The sidewall along the first substrate extends from the second upper surface toward the second lower surface. The wafer stack package of claim 11, wherein the second end of the wire is disposed in the other shallow groove structure. The wafer stack package of claim 11, further comprising a further wire having a first end point and a second end point, wherein the first end point of the other wire is disposed on the other A shallow groove structure, and the second end of the other wire is disposed on the second substrate. The wafer stack package of claim 1, wherein a highest portion of the wire is lower than the first upper surface. The wafer stack package of claim 1, further comprising an encapsulation layer covering the wiring and the first upper surface to form a flat contact surface over the sensing region or the component region, wherein the wiring One of the highest portions protrudes from the first upper surface, and a thickness of the encapsulation layer on the sensing region or the component region is determined by a distance between the highest portion of the wiring and a bottom portion of the shallow groove structure. The difference in depth of the shallow groove structure. The wafer stack package of claim 1, wherein the redistribution layer extending into the shallow trench structure contacts a sidewall of a conductive pad of the signal pad region. A wafer stack package includes: an upper substrate having a first upper surface, a first lower surface, and a first sidewall, wherein the upper substrate includes: a first signal pad region adjacent to the first An upper surface; and a first shallow groove structure extending from the first upper surface toward the first lower surface along the first sidewall; a lower substrate having a second upper surface and a second a lower surface and a second sidewall, wherein the lower substrate comprises: a second signal pad region adjacent to the second upper surface; a second shallow groove structure extending along the second upper surface toward the second lower surface along the second sidewall; a first redistribution layer extending into the first shallow groove structure And electrically connecting the first signal pad region; a second redistribution layer extending into the second shallow groove structure and electrically connecting the second signal pad region; a circuit board; a wire disposed in the first shallow groove structure and electrically connected to the first redistribution layer and the upper substrate or the circuit board; and a second wire disposed in the second shallow groove structure And electrically connecting the second redistribution layer and the lower substrate or the circuit board. The wafer stack package of claim 17, wherein the upper substrate is a biometric wafer. The wafer stack package of claim 18, wherein the biometric wafer is a fingerprint identification wafer. The wafer stack package of claim 18, wherein the lower substrate is a wafer or an interposer. The wafer stack package of claim 17, wherein the upper substrate and the lower substrate are the same. The wafer stack package of claim 17, wherein the first redistribution layer extending into the first shallow trench structure contacts a sidewall of a conductive pad of the first signal pad region. A method of manufacturing a wafer stack package includes: providing a device substrate having a first upper surface and a first lower surface; a sidewall, wherein the device substrate comprises: a sensing region or component region and a signal pad region adjacent to the first upper surface; and a shallow groove structure along the sidewall of the device substrate from the first The upper surface extends toward the first lower surface, wherein the shallow groove structure has at least a first recess and a second recess, and the second recess is located below the first recess; forming a redistribution layer Extending into the shallow groove structure and electrically connecting the signal pad region; providing a first substrate and a second substrate under the first lower surface, wherein the first substrate is located at the device substrate and the second Between the substrates; forming a wire having a first end point and a second end point, wherein the first end point is disposed in the shallow groove structure and electrically connected to the redistribution layer, and wherein the second An end point is disposed on the first substrate or the second substrate and electrically connected thereto; and covering the wiring, the first upper surface, the first substrate and the second substrate through an encapsulation layer to form a flat Contact the surface.