TW201440194A - Semiconductor package and its manufacturing method - Google Patents

Abstract

A semiconductor package comprising: a substrate having an opening, a first semiconductor component disposed in the opening, a cladding layer covering the first semiconductor component, and a second semiconductor component disposed on the cladding layer Since the substrate has an opening to provide the first semiconductor element in the opening, the height of the semiconductor package can be reduced without polishing the semiconductor element. The invention provides a method of fabricating the semiconductor package.

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package, and more particularly to a semiconductor package in which a plurality of semiconductor elements are stacked.

Due to the miniaturization of electronic products and the increasing demand for high operating speeds, in order to improve the performance and capacity of a single semiconductor package structure to meet the demand for miniaturization of electronic products, the semiconductor package structure is integrated into a multichip module. The trend is to combine two or more semiconductor wafers in a single package structure to reduce the overall circuit structure volume of the electronic product and improve electrical functions. That is, the multi-chip package structure can minimize the limitation of the operating speed of the system by combining two or more wafers in a single package structure. In addition, the multi-chip package structure reduces the length of the connection line between the chips and reduces signal delay and access time.

A common multi-chip package structure is a side-by-side multi-chip package structure in which two or more wafers are mounted side by side on a main mounting surface of a common substrate. The connection between the wafer and the conductive lines on the common substrate is generally achieved by wire bonding. to make. However, the side-by-side multi-chip package construction has the disadvantage that the package cost is too high and the package size is too large, since the area of the common substrate increases as the number of wafers increases.

In order to solve the above conventional problems, in recent years, a vertical stacking method has been used to increase the number of wafers, and the manner of stacking varies depending on the design of the wafer and the wiring process. For example, a flash memory chip provided in an electronic device of a memory card, the pads of the wafer are concentrated on one side, so the stacking manner is a stepped structure, so as to facilitate wire bonding and reduce placement memory. The area of the body wafer.

1A is a multi-wafer stacked semiconductor package 1 of a conventional memory card, in which a plurality of memory chips 14 are stacked on a package substrate 10, and the memory chips 14 are mutually instructed without impeding the wire bonding operation. Stacked in a stepped structure, a control chip 12 is disposed on the memory chip 14, and the memory chips 14 and the control wafer 12 are electrically connected to the package substrate 10 by a plurality of bonding wires 120, 140.

FIG. 1B is a conventional multi-wafer stacked semiconductor package 1 ′, comprising: a package substrate 10 , a control wafer 12 disposed on the package substrate 10 by the bonding layer 11 , and formed on the package substrate 10 a plurality of memory chips 14 on the cladding layer 13 and a package formed on the package substrate 10 in a manner of stacking the cladding layer 13 of the control wafer 12 and the stepped structure of the bonding layer 14a Colloid 15.

However, in the above two conventional semiconductor packages 1, 1', as the number of layers of the memory chip 14 is increased, the height of the semiconductor package 1, 1' is also increased, so that it is difficult to meet the demand for thinning. To maintain a thinner semiconductor package The volume of the package 1,1' needs to be thinned by the thinning method such as grinding, thereby increasing the manufacturing cost, which is not economical.

Therefore, how to overcome various problems of the conventional semiconductor package is an important issue.

In order to overcome the problems of the prior art, the present invention provides a semiconductor package comprising: a substrate having an opening; a first semiconductor component disposed in the opening; and a cladding layer formed in the opening Coating the first semiconductor element; and at least one second semiconductor element is disposed on the cladding layer.

The invention further provides a method for fabricating a semiconductor package, comprising: providing a substrate having an opening; placing a first semiconductor component in the opening; and forming a cladding layer in the opening to encapsulate the first semiconductor component, And bonding at least one second semiconductor component on the cladding layer.

In the above method, the process for forming the cladding layer includes: forming the cladding layer on the second semiconductor component; and bonding the second semiconductor component to the first semiconductor component by the cladding, The cladding layer covers the first semiconductor element.

In the above semiconductor package and method of fabricating the same, the opening is through the substrate. Therefore, in the foregoing method, the forming includes a carrier on one side of the opening, so that the carrier carries the first semiconductor component in the opening, and after forming the cladding, including removing the carrier .

In the foregoing semiconductor package and the method of manufacturing the same, the opening is stepped.

In the above semiconductor package and method of manufacturing the same, the first semiconductor component is a control wafer, and the first semiconductor component is electrically connected to the substrate, for example, electrically connected to a surface in the opening of the substrate.

In the above semiconductor package and method of fabricating the same, the second semiconductor component is a memory wafer, and the second semiconductor component is electrically connected to the substrate.

In the above semiconductor package and method of fabricating the same, the width of the second semiconductor component is greater than the width of the opening, and the second semiconductor component is disposed above the surface of the substrate having the opening.

In the foregoing semiconductor package and the method of fabricating the same, when the second semiconductor element is plural, the second semiconductor elements are stacked in a stepped structure with each other.

In addition, in the foregoing semiconductor package and the manufacturing method thereof, an encapsulant is further included on the substrate to cover the second semiconductor element and the cladding layer.

It can be seen from the above that the semiconductor package of the present invention and the method for manufacturing the same are provided in the opening by the substrate, so that the present invention does not need to polish the semiconductor component, that is, the prior art The height of the semiconductor package can be reduced, thereby reducing the size of the package and reducing the manufacturing cost.

1,1',2,2'‧‧‧ semiconductor package

10‧‧‧Package substrate

11,14a‧‧‧ bonding layer

12‧‧‧Control chip

120,140,220,240‧‧‧welding line

13,23‧‧ ‧ coating

14‧‧‧ memory chip

15,25‧‧‧Package colloid

20‧‧‧Substrate

20a‧‧‧ first surface

20b‧‧‧second surface

20c‧‧‧ bottom

200,200’‧‧‧ openings

21‧‧‧Carrier

210‧‧‧First bonding layer

22‧‧‧First semiconductor component

24,24'‧‧‧second semiconductor component

24a‧‧‧Second bonding layer

1A is a schematic cross-sectional view of a conventional semiconductor package; FIG. 1B is a schematic cross-sectional view of a conventional semiconductor package; and FIGS. 2A to 2D are diagrams showing a first embodiment of a method for fabricating a semiconductor package of the present invention; Schematic diagram of the section; 3A to 3C are cross-sectional views showing a second embodiment of the method of fabricating the semiconductor package of the present invention.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2A to 2D are cross-sectional views showing a first embodiment of the method of fabricating the semiconductor package 2 of the present invention.

As shown in FIG. 2A, a substrate 20 having an opening 200 is provided.

In this embodiment, the substrate 20 is a circuit board for packaging and has a first surface 20a and a second surface 20b opposite thereto, and the bottom portion 20c of the opening 200 communicates with the second surface 20b of the substrate 20 to The opening 200 is stepped through the substrate 20.

As shown in FIG. 2B, a carrier 21 is disposed on one side of the opening 200 (the second surface 20b of the substrate 20 in the figure), and a first semiconductor component 22 is bonded by a first bonding layer 210. The carrier 21 in the opening 200 is such that the carrier 21 carries the first semiconductor component 22.

In this embodiment, the first semiconductor device 22 is a control wafer and is electrically connected to the substrate 20, for example, by wire bonding of the bonding wires 220 or by flip-chip bonding of conductive bumps (not shown). An electrical contact pad (not shown) on the bottom 20c of the opening 200.

Furthermore, the carrier 21 is a temporary film, and the first bonding layer 210 is a film or a polymer compound such as epoxy.

As shown in FIG. 2C, a cladding layer 23 is formed in the opening 200 to cover the first semiconductor element 22 and the bonding wire 220. Specifically, a non-conductive cladding layer 23 is bonded under the second semiconductor component 24, and the cladding layer 23 is pressed onto the first semiconductor component 22 and the bonding wire 220 in the direction of the substrate 20. The cladding layer 23 is covered with the first semiconductor element 22 and the bonding wire 220.

In the present embodiment, the process of coating the first semiconductor element 22 and the bonding wire 220 by the cladding layer 23 is performed by a film over wire (FOW) technique.

Furthermore, the width of the second semiconductor component 24 is greater than the width of the opening 200, and the second semiconductor component 24 is disposed above the first surface 20a of the substrate 20.

As shown in FIG. 2D, other plural second semiconductor elements 24' are stacked. On the second semiconductor component 24. Next, an encapsulant 25 is formed on the substrate 20 to cover the second semiconductor elements 24, 24' and the cladding layer 23. Finally, the carrier 21 is removed to expose the first bonding layer 210.

In this embodiment, the second semiconductor elements 24, 24' are stacked in a stepped structure with each other and bonded to each other by the second bonding layer 24a, and at least one of the second semiconductor elements 24, 24' is For the memory chip, before the formation of the encapsulant 25, the second semiconductor components 24, 24' are electrically connected to the substrate 20, for example, by bonding the bonding wires 240 or by using conductive bumps. Show) the flip chip method.

3A to 3C are cross-sectional views showing a second embodiment of the method of fabricating the semiconductor package 2' of the present invention. The difference between this embodiment and the first embodiment lies only in the design of the opening 200', and the other structures are substantially the same, so the details are not described again.

As shown in Fig. 3A, a substrate 20 having an opening 200' is provided, and the opening 200' does not penetrate the substrate 20, i.e., the bottom portion 20c of the opening 200 does not communicate with the second surface 20b of the substrate 20. In another embodiment, although the opening 200' does not penetrate the substrate 20, the opening 200 can still be stepped.

As shown in FIG. 3B, a first semiconductor element 22 is bonded to the bottom portion 20c of the opening 200', and the first semiconductor element 22 is electrically connected to the substrate 20 by a bonding wire 220.

Since the opening 200' does not penetrate the substrate 20, it is not necessary to use a temporary film.

As shown in FIG. 3C, a cladding layer 23 is attached under the second semiconductor component 24, and the cladding layer 23 is pressed onto the first semiconductor component 22. And on the bonding wire 220, the cladding layer 23 is formed in the opening 200' to cover the first semiconductor element 22 and the bonding wire 220. Next, a plurality of other second semiconductor elements 24' are stacked on the second semiconductor element 24. Thereafter, an encapsulant 25 is formed on the substrate 20 to cover the second semiconductor elements 24, 24' and the cladding layer 23.

In the present invention, the first semiconductor component 22 is disposed in the opening 200, 200' of the substrate 20, and the second semiconductor component 24 is disposed over the first semiconductor component 22 to avoid the semiconductor package 2, 2' The volume is increased, and it is not necessary to polish the second semiconductor element 24, so that the manufacturing cost can be reduced.

Furthermore, the bonding wire 220 for connecting the first semiconductor component 22 is electrically connected to the surface of the substrate 20 in the opening 200, 200' instead of the surface of the substrate 20 outside the opening 200, 200', thereby reducing the soldering. The loop height of the wire 220 not only reduces the height of the cladding layer 23, but also reduces the volume of the semiconductor package 2, 2', and at the same time reduces the length of the bonding wire 220 and reduces the material cost.

The present invention provides a semiconductor package 2, 2' comprising: a substrate 20 having an opening 200, 200', and a first semiconductor component 22 disposed in the opening 200, 200', formed in the opening 200, 200' A cladding layer 23 of the first semiconductor component 22 and at least one second semiconductor component 24 stacked on the cladding layer 23 are coated.

The semiconductor package 2, 2' includes an encapsulant 25 formed on the substrate 20, which covers the second semiconductor component 24 and the cladding layer 23.

The first semiconductor component 22 is a control wafer and is electrically connected. The substrate 20 is.

The second semiconductor component 24 is a memory wafer and is electrically connected to the substrate 20 .

In one embodiment, the opening 200' extends through the substrate 20. In one embodiment, the openings 200, 200' are stepped.

In one embodiment, the width of the second semiconductor component 24 is greater than the width of the opening 200.

In one embodiment, the second semiconductor component 24 is disposed above the first surface 20a of the substrate 20.

In one embodiment, when the second semiconductor element 24 is plural, the second semiconductor elements 24 are stacked in a stepped structure with each other.

In summary, the semiconductor package of the present invention and the method for fabricating the same are mainly used for accommodating the first semiconductor component in the opening of the substrate to achieve the purpose of thinning the package, and simplifying the manufacturing process to reduce the manufacturing cost. The advantages.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Semiconductor package

20‧‧‧Substrate

20a‧‧‧ first surface

20b‧‧‧second surface

200‧‧‧ openings

210‧‧‧First bonding layer

22‧‧‧First semiconductor component

23‧‧‧Cladding

24,24'‧‧‧second semiconductor component

24a‧‧‧Second bonding layer

240‧‧‧welding line

25‧‧‧Package colloid

Claims (27)

A semiconductor package comprising: a substrate having an opening; a first semiconductor component disposed in the opening; a cladding layer formed in the opening to encapsulate the first semiconductor component; and at least one Two semiconductor elements are provided on the cladding layer. The semiconductor package of claim 1, wherein the opening extends through the substrate. The semiconductor package of claim 1, wherein the opening is stepped. The semiconductor package of claim 1, wherein the first semiconductor component is a control wafer. The semiconductor package of claim 1, wherein the first semiconductor component is electrically connected to the substrate. The semiconductor package of claim 5, wherein the first semiconductor component is electrically connected to a surface of the opening of the substrate. The semiconductor package of claim 1, wherein the second semiconductor component is a memory wafer. The semiconductor package of claim 1, wherein the second semiconductor component is electrically connected to the substrate. The semiconductor package of claim 1, wherein the second semiconductor element has a width greater than a width of the opening. The semiconductor package of claim 1, wherein The second semiconductor component is disposed above a surface of the substrate having the opening. The semiconductor package of claim 1, wherein when the second semiconductor element is plural, the second semiconductor elements are stacked in a stepped structure with each other. The semiconductor package of claim 1, further comprising an encapsulant formed on the substrate to encapsulate the second semiconductor component and the cladding layer. A method of fabricating a semiconductor package, comprising: providing a substrate having an opening; placing a first semiconductor component in the opening of the substrate; forming a cladding layer in the opening to encapsulate the first semiconductor component; and combining at least A second semiconductor component is on the cladding layer. A method of fabricating a semiconductor package, comprising: providing a substrate having an opening; placing a first semiconductor component in the opening of the substrate; bonding a cladding layer to the at least one second semiconductor component; and the second semiconductor The component is laminated on the first semiconductor component with the cladding, and the cladding layer covers the first semiconductor component. The method of fabricating a semiconductor package according to claim 13 or claim 14, wherein the opening is through the substrate. The method of manufacturing a semiconductor package according to claim 15 further comprising forming a carrier on one side of the opening to allow the carrier to bear The first semiconductor component in the opening is carried. The method of fabricating a semiconductor package according to claim 16, wherein after the cladding layer encapsulates the first semiconductor component, the carrier is removed. The method of fabricating a semiconductor package according to claim 13 or claim 14, wherein the opening is stepped. The method of fabricating a semiconductor package according to claim 13 or claim 14, wherein the first semiconductor component is a control wafer. The method of fabricating a semiconductor package according to claim 13 or claim 14, wherein the first semiconductor component is electrically connected to the substrate. The method of fabricating a semiconductor package according to claim 20, wherein the first semiconductor component is electrically connected to a surface of the opening of the substrate. The method of fabricating a semiconductor package according to claim 13 or claim 14, wherein the second semiconductor component is a memory wafer. The method of fabricating a semiconductor package according to claim 13 or claim 14, wherein the second semiconductor component is electrically connected to the substrate. The method of fabricating a semiconductor package according to claim 13 or claim 14, wherein the second semiconductor element has a width greater than a width of the opening. The method of fabricating a semiconductor package according to claim 13 or claim 14, wherein the second semiconductor component is disposed above a surface of the substrate having the opening. The manufacture of a semiconductor package as described in claim 13 or 14 The method wherein, when the plurality of second semiconductor elements are plural, the second semiconductor elements are stacked in a stepped structure with each other. The method of fabricating a semiconductor package according to claim 13 or 14, further comprising forming an encapsulant on the substrate to encapsulate the second semiconductor element and the cladding layer.