TW201432849A - Manufacturing method of metal line and device having metal line produced by same - Google Patents

Abstract

A method for manufacturing metal lines and a device having metal lines produced by same method are provided. The manufacturing method of the metal lines includes: forming a first barrier layer and a sacrificial layer in order onto a substrate; forming at least one opening penetrated the sacrificial layer to expose the first barrier layer; growing a metal line from a top of the first barrier layer disposed at a bottom of the opening; removing the sacrificial layer and forming a second barrier layer onto the metal line, around the sidewall of the metal line, and onto the first barrier layer; performing an etching process to remove part of the second barrier layer and part of the first barrier layer in order, while leaving the second barrier layer disposed around the sidewall of the metal line and the first barrier layer disposed under the second barrier layer and the metal line; and forming a insulating layer onto the substrate having the metal line, the first barrier layer and the second barrier layer.

Description

Metal wire manufacturing method and component with metal wire

The present invention relates to a method of manufacturing a metal wire and a metal wire structure, and more particularly to a method of manufacturing a metal wire having a high aspect ratio and a metal wire structure manufactured using the same.

According to Moore's Law, the number of transistors per unit area in the wafer is increasing, and the critical line width and spacing will become smaller and smaller. However, with the miniaturization of components, the damascene process used in the current copper process faces the problems caused by the miniaturization of the wires in terms of process and electrical properties. In order to reduce the resistance of the wire by relatively increasing the aspect ratio of the metal wire without increasing the component area, the relative difficulty of the metal filling process is relatively increased.

In the copper process for forming a metal wire, a hole to be filled is usually formed in the insulating layer, and a diffusion barrier layer and a seed layer are sequentially formed on the sidewall and the bottom of the hole. The metal wire is grown by electroplating. However, when the aspect ratio of the hole is increased, it means that the hole depth is deep or the opening aperture is relatively small. Therefore, when the opening diameter of the top of the hole to be filled is reduced and the thickness of the barrier layer is constant, the process conditions of the seed layer are relatively more severe, and the seed layer is prepared by the conventional physical vapor deposition method in the process. In the process of causing overhang. Therefore, the opening is shrunk smaller, and it is easy to cause a failure of the subsequent plating process to create a hole.

In addition, for high aspect ratio holes, during the plating process, deposits in the holes The rate of narrowing caused by the metal on both sides of the hole is faster than the growth rate of the bottom metal. If the metal deposit at the bottom of the hole does not completely reach the tip, and the tip of the hole has been sealed first, it will cause internal hole defects in the metal wire. When a hole defect is generated inside the metal wire, the resistance value of the wire is relatively increased and the reliability is lowered. If the thickness of the diffusion barrier layer is reduced to increase the space of the electroplatable metal wire, in the case of the copper wire, the too thin diffusion barrier layer is not necessarily effective against the diffusion of copper. Also, because the thickness of the diffusion barrier layer cannot be reduced, when the copper wire is thinned, the overall effective resistance of the wire will rise. If the thickness of the seed layer is reduced to increase the space of the electroplatable metal wire, the seed layer may be discontinuous due to poor uniformity on both sidewalls of the hole, resulting in a portion lacking the seed layer during the plating process. It is impossible to deposit copper on it, thus forming internal void defects. Therefore, the current copper process is facing the development stage of new materials and new process technologies, such as looking for new seed materials, such as metal ruthenium (Ru) or cobalt (Co), to make continuous films by CVD, and to reduce the PVD method at the open end. The formation of overhang phenomena, etc.; or new barrier process technology, such as atomic layer deposition (ALD) or CVD technology to replace the PVD process. When the process conditions have to meet the component size of 22 nm or less, the physical vapor deposition (PVD) which is conventionally used to fabricate the diffusion barrier layer and the seed layer is likely to cause uniformity of film coverage. The narrowing of the hole and the hole can not be applied to the hole-draw process of high aspect ratio; or when the conventional yellow etching process is used to form the hole to be filled, the condition control of the etching process becomes more difficult, especially in etching. The processing conditions of the porous low-k dielectric are controlled, for example, etching sidewall smoothness, etching selectivity, etching stop layer, and damage control and recovery of the etching process. The above shortcomings make the traditional process face a major challenge in the process of small size line width.

In view of this, it is necessary to propose a new metal wire process technology and structure to solve the problem of fabrication of the miniaturized metal wire.

The invention provides a method for manufacturing a metal wire, which is manufactured by using a lithography process Continued to grow the opening of the metal wire to avoid complicated etching process and accompanying plasma damage.

The invention provides a method for manufacturing a metal wire, which utilizes the growth mode of the metal wire deposited from the bottom up, without the problem of the occurrence of the hole, and can solve the problem of manufacturing the metal wire which is miniaturized.

The invention provides a metal wire structure, which utilizes an air gap formed by a non-uniform insulating layer during filling to make the overall metal wire structure have low capacitance characteristics to improve component performance.

In order to achieve the above advantages or other advantages, an embodiment of the present invention provides a method for manufacturing a metal wire, comprising: providing a substrate, and forming a first barrier layer over the substrate; forming a sacrificial layer over the first barrier layer; Forming at least one opening in the layer, wherein the opening penetrates the sacrificial layer and exposes the first barrier layer; performing a metal growth process over the first barrier layer at the bottom of the opening to grow the metal wire; removing the sacrificial layer and forming The second barrier layer is above the metal wires, above the sidewalls and the first barrier layer; an etching process is performed to remove a portion of the second barrier layer and a portion of the first barrier layer, leaving the sidewall of the metal wire a barrier layer, and leaving a first barrier layer under the second barrier layer and under the metal wiring; and forming an insulating layer over the substrate having the metal wiring, the first barrier layer and the second barrier layer.

In an embodiment of the invention, the metal growth process is an electroplating process or an electroless plating process, and is an anisotropic growth deposited from the bottom up.

In an embodiment of the invention, more than two openings are formed in the sacrificial layer, the openings penetrating the sacrificial layer and exposing the first barrier layer, and performing over the first barrier layer at the bottom of the openings a metal growth process for growing metal wires in the openings, wherein a gap between the adjacent second barrier layers of the two metal wires is less than 30 nm, and the second barrier is covered by the non-uniform insulating layer An air-gap is naturally formed between two adjacent metal wires covered by the layer.

The invention further provides a method for manufacturing a metal wire, comprising: providing a substrate, forming a barrier layer over the substrate, and forming a sacrificial layer over the barrier layer; forming in the sacrificial layer At least one opening, wherein the opening penetrates the sacrificial layer and exposes the barrier layer; a metal growth process is performed over the barrier layer at the bottom of the opening to grow the metal wire; and the sacrificial layer and the barrier layer below it are removed, leaving The lower metal wire and the underlying barrier layer are then formed over the substrate having the metal wires and the barrier layer.

The invention further provides an element having a metal wire, comprising: a substrate, an insulating layer above the substrate and a first metal wire structure embedded in the insulating layer. The first metal wire structure includes a metal conductor layer, a first barrier layer and a second barrier layer, wherein the first barrier layer is located between the substrate and the metal conductor layer, and the second barrier layer is located above the first barrier layer And located on the side wall of the metal conductor layer. The thickness of the second barrier layer adjacent to the first barrier layer is greater than the thickness of the second barrier layer away from the first barrier layer.

In an embodiment of the present invention, the insulating layer is further embedded with a second metal wire structure, and the insulating layer between the first metal wire structure and the second metal wire structure having the same structure further includes an air gap, wherein The spacing between a metal wire structure and the second metal wire structure is less than 30 nm.

In an embodiment of the invention, the material of the metal wire is one selected from the group consisting of silver, tungsten, molybdenum, niobium and nickel.

In an embodiment of the invention, the second barrier layer has a curved sidewall and a planar sidewall, wherein the planar sidewall is in contact with the sidewall of the metal conductor layer, and the sidewall of the curved surface and the planar sidewall are adjacent to the second barrier layer One end of the first barrier layer.

In summary, the method of manufacturing a metal wire of the present invention utilizes a lithography process to create an opening for subsequent growth of a metal wire, thereby eliminating complex etching processes and accompanying plasma damage. In addition, the metal growth process of the present invention utilizes electroplating, electroless plating or electrophoresis processes, and a first barrier layer at the bottom of the via or trench to make the metal wire completely bottom-up or close to or from the bottom of the via or trench. The top of the through hole or the groove can control the growth height of the metal wire, and the subsequent chemical mechanical polishing (CMP) process can be eliminated. However, the present invention can also be controlled by a chemical mechanical polishing process after the metal growth process. The growth height of the metal wire. In this way, no holes are generated, which will overcome the problem of the leftover of the metal wire holes.

In addition, by using the metal wire manufacturing method of the present invention, an air gap can naturally be formed in the insulating layer between two adjacent metal wires having a small pitch, and the thus obtained metal wire structure has low capacitance characteristics and can improve component performance. Improve component delay issues.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

110, 310‧‧‧ substrate

112, 114, 312, 314‧‧‧Optoelectronic structures

116, 316‧‧‧ dielectric layer

117, 317‧‧‧metal layer window

120, 320‧‧‧ first barrier layer

130‧‧‧ Sacrifice layer

132, 134‧‧‧ openings

140, 142‧‧‧Metal wires

150, 350‧‧‧ second barrier layer

152, 352‧‧‧ curved side walls

154, 354‧‧‧ plane sidewall

160, 360‧‧‧ insulation

162, 362‧‧‧ air gap

300‧‧‧ Components with metal wires

340, 342‧‧‧Metal conductor layer

370‧‧‧First metal wire structure

372‧‧‧Second metal wire structure

1A to 1F are schematic flow charts showing a method of manufacturing a metal wire according to an embodiment of the present invention.

2 is a schematic view showing the structure of an element having a metal wire according to another embodiment of the present invention.

3A is a schematic view showing the structure of an element having a metal wire according to another embodiment of the present invention.

Fig. 3B is an enlarged view of the range of the dotted circle in Fig. 3A of the present invention.

1A to 1F are schematic flow charts showing a method of manufacturing a metal wire according to an embodiment of the present invention. Referring to FIG. 1A, the method for manufacturing a metal wire of the present embodiment includes the following steps: First, a substrate 110 is provided, and a first barrier layer 120 is formed over the substrate 110, as shown in FIG. 1A. The above method of forming the first barrier layer 120 is, for example, Atomic Layer Deposition (ALD).

The substrate 110 may be a semiconductor substrate (for example, a germanium substrate) or a metal substrate, and the substrate 110 has, for example, completed a transistor structure 112, 114, a memory structure, or other circuit elements that need to be electrically connected by metal wires. The invention has completed the transistor structure 112, 114 on the semiconductor substrate as an illustrative example, and the transistor structure The upper portion 112, 114 further includes a dielectric layer 116 and a metal via plug 117, but the transistor structure and the metal layer via are not limited to the number shown in the drawing. It is worth mentioning that the first barrier layer 120 is formed above the dielectric layer 116 and the metal via 117.

In addition, the material of the first barrier layer 120 may be selected from a pure metal (such as tantalum (Ta), tungsten (W), cobalt (Co), titanium (Ti) or ruthenium (Ru)), a multi-metal alloy (such as titanium tungsten). Alloy (Ti-W)), metal nitride (such as titanium nitride (Ti-N), tantalum nitride (Ta-N), tungsten nitride (WN) or tantalum nitride (NbN)), metal carbide ( For example, titanium carbide (TiC), tantalum carbide (Ta-C), tungsten carbide (WC), metal oxides (such as ruthenium oxide (Ru-O), iridium oxide (Ir-O), manganese oxide (Mn-O) , alumina (Al-O)) or a combination thereof. Further, the thickness of the first barrier layer (film) is, for example, several nanometers. Furthermore, the first barrier layer is for example compounded from one or more of the above materials, wherein the first barrier layer can be a single layer, a composite layer or a progressive layer. Further, the above-described progressive layer may be obtained by implanting atoms of different concentrations of carbon, nitrogen or oxygen in a longitudinal depth in the above-mentioned metal material film layer. In addition, the above composite materials generally have a material having a property of promoting adhesion or lowering junction resistance, such as a Ti/TiN composite material used in a tungsten embedding process, and a TaN\Ta composite material used in a copper process. However, the material and thickness of the first barrier layer of the present invention are not limited to the above.

Next, referring to FIG. 1B, a sacrificial layer 130 is formed on the first barrier layer 120, wherein the sacrificial layer 130 comprises a photosensitive material. Thereafter, the sacrificial layer 130 is subjected to a lithography process such as exposure, development, and hard baking to form at least one opening in the sacrificial layer 130. The present invention is illustrated in the formation of openings 132, 134 in sacrificial layer 130, however the number of openings is not limited to the above. The openings 132, 134 are respectively located above the partial transistor structures 112, 114 and the metal layer via 117, and the openings 132, 134 extend through the sacrificial layer 130 and expose the first barrier layer 120 at the bottom of the openings 132, 134. The openings 132, 134 extending through the sacrificial layer 130 may be of a type such as a slot or a via. It is worth mentioning that the sacrificial layer 130 is, for example, a photoresist material or an insulating material. The present invention proposes to utilize lithography The process is used to create subsequent openings for growing metal wires, eliminating the need for traditional complex etching process control and accompanying plasma damage.

After the openings 132 and 134 are formed in the sacrificial layer 130, the first barrier layer 120 exposed at the bottom of the openings 132 and 134 is subjected to a surface modification process (not shown). The surface modification process is, for example, a physical plasma bombardment method or an oxidation method using an oxidizing agent, or a chemical modification method of soaking an acid-base solution or a diluted HF (DHF) solution.

Referring to FIG. 1C, after the surface modification process of the first barrier layer 120 exposed at the bottom of the openings 132, 134, a metal growth process, such as an electroplating process, an electroless process, or Other wet chemical processes (such as electrophoresis processes or supercritical fluid plating processes, etc.), above the first barrier layer 120 at the bottom of the openings 132, 134, are anisotropically grown from the bottom up. In the anisotropic growth mode, the metal wires 140, 142 are grown to the top of the openings 132, 134. The metal growth process of the present invention can eliminate the subsequent chemical mechanical polishing (CMP) process by controlling the growth height of the metal wires. However, the present invention can also utilize a chemical mechanical polishing process to control the growth height of the metal wires after the metal growth process.

It is worth mentioning that the main purpose of surface modification of the first barrier layer 120 is to allow the metal wires 140 and 142 to grow on the surface of the modified first barrier layer 120 on average, and to improve the metal wires 140. , 142 the wetting characteristics in the metal growth process to form good metal wires 140, 142. Further, the material of the metal wires 140 and 142 is one selected from the group consisting of silver, tungsten, molybdenum, niobium, nickel or other metal elements, but is not limited thereto.

Referring to FIG. 1D, after the growth process of the metal wires 140 and 142 is completed, the sacrificial layer 130 is removed, and a second barrier is formed above the metal wires 140 and 142, the sidewalls, and the first barrier layer 120. Layer 150. Forming the second barrier The method of layer 150 is, for example, an atomic layer deposition method. It is worth mentioning that the second barrier layer 150 is mainly used for blocking the diffusion of metal elements in the metal wires, and can also be used to enhance the adhesion between the metal wires and the subsequently formed insulating layer. In addition, the material of the second barrier layer 150 may be selected from pure metal (such as tantalum, tungsten, cobalt, titanium or tantalum), multi-metal alloy (such as titanium tungsten alloy), metal nitride (such as titanium nitride, tantalum nitride, Tungsten nitride or tantalum nitride), metal carbides (such as titanium carbide, tantalum carbide, tungsten carbide), metal oxides (such as yttria, yttria, manganese oxide, aluminum oxide) or a combination thereof.

Referring to FIG. 1E , an anisotropic etching process is performed on the second barrier layer 150 to remove a portion of the second barrier layer 150 and a portion of the first barrier layer 120 while leaving sidewalls of the metal wires 140 and 142 . The second barrier layer 150 is left with a first barrier layer 120 under the second barrier layer 150 and under the metal wires 140, 142. The thickness of the second barrier layer 150 after the non-isotropic etching process is completed is close to the thickness of the first barrier layer 120, for example, greater than the thickness of the first barrier layer 120. In addition, the second barrier layer 150 has a curved sidewall 152 and a planar sidewall 154. The planar sidewall 154 is in contact with the sidewalls of the metal wires 140 and 142, and the curved sidewall 152 and the planar sidewall 154 are in contact with the second barrier layer 150. It is away from one end of the first barrier layer 120.

Referring to FIG. 1F, an insulating layer 160 is formed over the substrate 110 having the metal wires 140, 142, the first barrier layer 120, the second barrier layer 150, and the transistor structures 112, 114, and finally the insulating layer 160. Perform a flattening process such as chemical mechanical polishing. It is worth mentioning that if the spacing between the adjacent second barrier layers 150 of the two metal wires 140, 142 is reduced, for example, the pitch is less than 30 nm, the air gap is naturally formed due to the non-uniformity of the insulating layer 160. An air-gap 162 is between the two adjacent second barrier layers 150. The air gap 162 of the present invention is not limited to the position depicted in Figure 1F. Such an insulating layer 160 having an air gap is referred to as a non-uniform film layer. The invention utilizes the insulating layer 160 with poor step coverage capability, and the metal wire structure of the invention has both low resistance and low capacitance characteristics, which helps to improve the delay problem derived from the metal process to improve the component performance. In addition, the material of the insulating layer 160 is, for example, an oxide or a nitride, but is not limited thereto. The metal wires 140 and 142 of the present invention can be used as a connection between the conductor layers (not shown) and the transistor structures 112 and 114 which are subsequently grown on the metal wires 140 and 142, the second barrier layer 150 and the insulating layer 160. wire. Further, a via plug 117 can also be produced by using the metal wire manufacturing method of the present invention.

It is worth mentioning that the present invention further provides a method for fabricating a metal wire, similar to the process flow of FIGS. 1A to 1F, except that the step of forming the second barrier layer 150 of FIG. 1D may be omitted. In detail, after the metal wires 140 and 142 are formed and the sacrificial layer 130 is removed, the second barrier layer 150 may not be formed, and a portion of the first barrier layer 120 may be directly removed by anisotropic etching. The first barrier layer 120 under the metal wires 140, 142 is left; then the insulating layer 160 is formed over the substrate 110 having the metal wires 140, 142, the first barrier layer 120 and the transistors 112, 114, A schematic diagram of the structure of the component having the metal wire completed in the step is shown in FIG. 2. In this process method, the process steps of actively forming the second barrier layer 150 around the metal wires are omitted. Therefore, the method is suitable for forming a metal wire by using a metal material which is less prone to diffusion, or for additionally forming a metal wire, and additionally adding a surface oxidation reaction or surface nitridation reaction with the insulating layer 160. The metal material is added with a metal element such as aluminum, manganese, tantalum or tungsten, but the invention is not limited thereto. In addition, if a metal material which easily generates an oxidation reaction or a nitridation reaction with the insulating layer 160 is used, the side walls around the completed metal wires 140 and 142 are naturally surrounded by a metal oxide layer or a metal nitride layer. In addition, when the pitch of the two metal wires 140, 142 is reduced, an air gap 162 is naturally formed between the two metal wires 140, 142 due to the non-uniform characteristics of the insulating layer 160.

3A is a schematic view showing the structure of an element having a metal wire according to another embodiment of the present invention. Referring to FIG. 3A, the component 300 having a metal wire of the present invention includes a substrate 310, an insulating layer 360 over the substrate 310, and a first metal wire structure 370 and a second metal wire structure 372 embedded in the insulating layer 360. Substrate 310 and substrate 110 The structure is the same and will not be described here. In addition, the transistor structure 312, 314 is completed on the substrate 310, and the dielectric layer 316 and the metal via plug 317 are further included above the transistor structures 312, 314. The insulating layer 360 of the present invention is illustrated by inlaid with two metal wire structures 362. However, the insulating layer 360 may be embedded with one or more metal wire structures, and the present invention is not limited thereto.

The first metal wire structure 370 and the second metal wire structure 372 respectively include metal conductor layers 340, 342, a first barrier layer 320, and a second barrier layer 350. The first barrier layer 320 is located between the transistor structures 312 and 314 on the substrate 310 and the metal conductor layers 340 and 342. The second barrier layer 350 is located on the sidewalls of the metal conductor layers 340 and 342 and is located at the first barrier layer. Above 320. In addition, the thickness of the second barrier layer 350 adjacent to the first barrier layer 320 is greater than the thickness of the second barrier layer 350 away from the first barrier layer 320, for example. Please refer to Figure 3B. Fig. 3B is an enlarged view of the range of the dotted circle in Fig. 3A of the present invention. The second barrier layer 350 has, for example, a curved sidewall 352 and a planar sidewall 354. The planar sidewall 354 is in contact with the sidewalls of the metal conductor layers 340 and 342 , and the sidewall 352 and the planar sidewall 354 are adjacent to one end of the second barrier layer 350 away from the first barrier layer 320 .

It is worth mentioning that the insulating layer 360 between the first metal wire structure 370 and the second metal wire structure 372 further includes an air gap 362. The distance between the first metal wire structure 370 and the second metal wire structure 372 is, for example, less than 30 nm. The materials of the first barrier layer 320, the second barrier layer 350, and the metal conductor layers 340 and 342 are the same as those of the first barrier layer 120, the second barrier layer 150, and the metal wires 140 and 142, respectively. This will not be repeated here.

In summary, the method of manufacturing a metal wire of the present invention utilizes a lithography process to create an opening for subsequent growth of a metal wire, thereby eliminating complex etching processes and accompanying plasma damage. In addition, electroplating, electroless plating or other wet chemical processes (such as electrophoresis processes) and a first barrier layer at the bottom of the via or trench allow the metal wires to grow completely from the bottom of the via or trench to near or flush. The top of the hole or groove to solve the metallization of the miniaturization Line making problem. In addition, by using the metal wire manufacturing method of the present invention, an air gap can naturally be formed in the insulating layer between two adjacent metal wires having a small pitch, and the metal wire structure thus obtained has low resistance and low capacitance characteristics and can be improved. Component performance and improved component latency issues.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

110‧‧‧Substrate

112, 114‧‧‧Optoelectronic structure

116‧‧‧Dielectric layer

117‧‧‧Metal layer window

120‧‧‧First barrier layer

140, 142‧‧‧Metal wires

150‧‧‧second barrier layer

160‧‧‧Insulation

162‧‧‧Air gap

Claims (16)

A metal wire manufacturing method includes: providing a substrate; forming a first barrier layer over the substrate; forming a sacrificial layer over the first barrier layer; forming at least one opening in the sacrificial layer, the opening The sacrificial layer exposes the first barrier layer; performing a metal growth process over the first barrier layer at the bottom of the opening to grow a metal wire; removing the sacrificial layer and forming a second The barrier layer is above the metal wire, above the sidewall and the first barrier layer; an etching process is performed to sequentially remove a portion of the second barrier layer and a portion of the first barrier layer, leaving The second barrier layer of the sidewall of the metal wire, and leaving the first barrier layer under the second barrier layer and under the metal wire; and forming an insulating layer having the metal wire, the first The barrier layer and the second barrier layer are above the substrate. The metal wire manufacturing process according to claim 1, wherein the metal growth process is an electroplating process or an electroless plating process, and an anisotropic growth is deposited from the bottom. The method for manufacturing a metal wire according to claim 1, further comprising forming more than two openings in the sacrificial layer, the openings penetrating the sacrificial layer and exposing the first barrier layer, and Performing the metal growth process over the first barrier layer at the bottom of the openings to grow the metal wires in the openings, wherein the metal wires are When a distance between adjacent second barrier layers is less than 30 nm, the insulating layer formed between two adjacent barrier layers is a non-uniform film layer having an air gap. The method for manufacturing a metal wire according to claim 1, wherein the metal wire is made of a metal selected from the group consisting of silver, tungsten, molybdenum, niobium, and nickel or an alloy thereof. A metal wire manufacturing method includes: providing a substrate; forming a barrier layer over the substrate; forming a sacrificial layer over the barrier layer; forming at least one opening in the sacrificial layer, the opening penetrating the sacrificial layer Exposing the barrier layer; performing a metal growth process over the barrier layer at the bottom of the opening to grow a metal wire; and removing the sacrificial layer and the barrier layer therebelow, leaving the metal The wire and the barrier layer therebelow, and then an insulating layer is formed over the substrate having the metal wire and the barrier layer. The method of manufacturing a metal wire according to claim 5, wherein the material of the metal wire is selected from one of silver, tungsten, molybdenum, niobium, and nickel or an alloy thereof. The method of manufacturing a metal wire according to claim 5, wherein the sacrificial layer is a photoresist material or an insulating material. The method for manufacturing a metal wire according to claim 5, wherein the metal growth process is an electroplating process or an electroless plating process, and is an anisotropic deposition from the bottom to the top. Sexual growth. The method for manufacturing a metal wire according to claim 5, further comprising performing a surface modification process on the barrier layer exposed at the bottom of the opening. The method for manufacturing a metal wire according to claim 5, further comprising forming more than two openings in the sacrificial layer, the openings penetrating the sacrificial layer and exposing the barrier layer, and Performing the metal growth process over the barrier layer at the bottom of the opening to grow the metal wire in the openings, wherein when a distance between two adjacent metal wires is less than 30 nm, between the two adjacent metal wires The insulating layer is formed as a non-uniform film layer having an air gap. The method of manufacturing a metal wire according to claim 5, wherein the substrate is a semiconductor substrate or a metal substrate, and a crystal structure or a memory structure is completed on the substrate. An element having a metal wire, comprising: a substrate; an insulating layer disposed above the substrate; a first metal wire structure embedded in the insulating layer, the first metal wire structure comprising: a metal conductor layer; a barrier layer between the substrate and the metal conductor layer; a second barrier layer over the first barrier layer and on the sidewall of the metal conductor layer; and wherein the first barrier layer is adjacent to the first barrier layer The thickness of the second barrier layer is greater than the distance The thickness of the second barrier layer of the first barrier layer. The component having a metal wire according to claim 12, wherein the insulating layer is further embedded with a second metal wire structure between the first metal wire structure and the second metal wire structure having the same structure. The insulating layer further includes an air gap, wherein a distance between the first metal wire structure and the second metal wire structure is less than 30 nm. The element having a metal wire according to claim 12, wherein the material of the metal wire is one selected from the group consisting of silver, tungsten, molybdenum, niobium, and nickel or an alloy thereof. The component having a metal wire according to claim 12, wherein the substrate is a semiconductor substrate or a metal substrate, wherein a crystal structure or a memory structure is completed on the substrate. The component having a metal wire according to claim 12, wherein the second barrier layer has a curved sidewall and a planar sidewall, the planar sidewall being in contact with the sidewall of the metal conductor layer, and the sidewall of the arc is The planar sidewall is adjacent to one end of the second barrier layer away from the first barrier layer.