TW201436207A - Germanium FINFET structure - Google Patents

Abstract

A germanium (Ge) FIN field effect transistor (FINFET) structure includes a substrate and a Ge layer. The Ge layer is formed on the substrate; a surface of the Ge layer is a Ge {110} lattice plane. The Ge layer includes at least a Ge spatial structure. The Ge spatial structure includes a top surface and a sidewall surface, wherein the top surface is a Ge {110} lattice plane and the sidewall surface is perpendicular to the top surface. An axis is formed at a junction of the sidewall surface and the top surface, and an extensive direction of the axis is parallel to a Ge [112] lattice vector on the surface of the Ge layer, therefore the sidewall surface is a Ge {111} lattice plane. The Ge FINFET structure is applied for fabricating Ge electron channel (N-type) FINFET devices.

Description

Yttrium field effect transistor structure

The present invention relates to a semiconductor device structure, and more particularly to a germanium semiconductor fin field effect transistor structure including a germanium {111} crystal face.

By "crystal material" is meant a periodic arrangement of atoms of the material; the so-called "single crystal material" means that the atom is periodically aligned along the entire material. For the lattice direction and the crystal plane direction of the single crystal material, according to the Miller Index (the three-dimensional index based on the right-angled solid coordinates), wherein: the <hkl> lattice direction indicates the origin from the single crystal material ( 0,0,0) points to the vector formed by the coordinate point (h,k,l). For example, the lattice direction <100> means that the origin (0,0,0) points to the coordinate point (1,0,0). The vector; the lattice direction [hkl] is a vector set containing all the points (0, 0, 0) in the single crystal material formed by (±h, ±k, ±l), for example: lattice direction [100] is a set of vectors containing coordinate points (1,0,0) and (-1,0,0) from the origin (0,0,0); (hkl) crystal plane refers to the normal vector as [h] The plane of , k, l], for example: (100) crystal plane refers to the plane perpendicular to the vector [1, 0, 0]; {hkl} crystal plane means that all the vectors are included (±h, ±k, ± l) vertical plane set, for example: {100} crystal plane refers to all plane sets perpendicular to the vector (1,0,0) and (-1,0,0); and lattice direction [hkl] and {hkl The crystal plane is perpendicular, for example, the lattice direction [100] is perpendicular to the {100} crystal plane.

In the sub-nano generation semiconductor process, in order to achieve the design requirements for continuously reducing the size of semiconductor components, and further increase the reaction speed of semiconductor components and reduce the power consumption of semiconductor components, semiconductor materials with high carrier mobility are selected, for example: (Ge), to manufacture Semiconductor components are a solution. Under an electric field perpendicular to the surface, a single crystal 锗 {111} surface forms a potential well. The electrons in the potential well are redistributed due to the quantum mechanical limiting effect, and the redistributed electrons occupy the lowest energy state, which has the lowest effective mass on the {111} plane. Therefore, the {111} crystal with a single crystal 锗 structure The surface is used as a conduction channel for electron carriers, and is applied to N-type germanium semiconductor devices in which most carriers are electrons, for example, an N-type field effect transistor (abbreviation: N-type Ge FET), which can generate the highest electrons. Carrier mobility. In addition, the standard type of N-type fin gate field effect transistor (abbreviation: N-type Ge fin-FET), the vertical side wall of the rectangular section channel structure can contribute a large channel effective width, and can effectively increase The drive current of the component.

It can be seen from the above two points that the channel structure of the standard type N-type Ge fin-FET can have an excellent electrical performance if the vertical sidewall surface is a 锗{111} crystal plane. However, the conventional technique cannot form a structure in which a vertical surface is a 锗{111} crystal plane on a germanium layer having a surface of 锗{100} crystal plane, and thus it is impossible to manufacture a standard type fin gate having a {111} plane side wall.锗 field effect transistor. Therefore, how to form a skeletal structure including a vertical plane of 锗{111} crystal plane on the ruthenium layer whose surface is 锗{110} crystal plane is one of the main purposes of developing the present invention.

It is an object of the present invention to provide a skeletal field effect transistor structure comprising a substrate and a layer of germanium. The ruthenium layer is formed on the substrate, and the surface of the ruthenium layer is a 锗{110} crystal plane. The layer of germanium contains at least one solid structure. The 锗 three-dimensional structure comprises a top surface and a sidewall surface, wherein the top surface is a 锗{110} crystal plane, and the sidewall surface is perpendicular to the top surface. An axis is formed at the interface between the sidewall surface and the top surface, and the axis extends in a direction parallel to the 锗[112] lattice direction of the surface of the ruthenium layer, and the sidewall surface is a 锗{111} crystal plane.

In an embodiment of the invention, the substrate is a substrate of a ruthenium, osmium or gallium arsenide material, and the surface of the substrate is a {110} crystal plane.

In an embodiment of the invention, the substrate includes an oxide layer formed on the surface of the substrate, and the oxide layer includes at least one opening parallel to the surface of the substrate [112] The lattice direction, the above-described 锗 three-dimensional structure is formed in the opening.

In one embodiment of the present invention, the 锗[112] lattice direction of the surface of the ruthenium layer means that the [110] lattice direction of the surface of the ruthenium layer is rotated counterclockwise by 50-60 degrees or clockwise along the surface of the ruthenium layer. Rotating the range of 120-130 angles can also be rotated clockwise by 50-60 degrees or counterclockwise by 120-130 angles to obtain other equivalent [112] lattice directions.

In an embodiment of the invention, the 锗-dimensional structure further includes a dielectric layer, a conductive structure, and an electron carrier (N-type) source/drain doping region. The dielectric layer is formed on a portion of the above-described 锗-dimensional structure. A conductive structure is coated over the dielectric layer. The conductive structure combines the dielectric layer to form a first gate. The electron carrier (N-type) source/drain-doped region is formed in the above-described 锗-dimensional structure and disposed on both sides of the first gate.

In an embodiment of the invention, the 锗 three-dimensional structure further includes a bottom surface, and the bottom surface is located below the top surface and suspended on the base.

In an embodiment of the invention, the first three-dimensional structure further includes a first gate sidewall and a first stress layer. The first gate sidewall surrounds the sidewall of the conductive structure. The first stress layer is disposed on the electron carrier (N-type) source/drain doping region, wherein a lattice size of the first stress layer is smaller than a lattice size of the germanium layer.

In an embodiment of the invention, the surface height of the electron carrier (N-type) source/drain doped region is lower than the surface height of the top surface.

In an embodiment of the invention, the germanium layer further comprises at least one hole carrier (P-type) planar field effect transistor structure, and the P-type planar field effect transistor structure comprises a second gate and a hole carrier. Sub (P-type) source/drain doped regions and one channel. The second gate is disposed on the surface of the germanium layer. A hole carrier (P-type) source/drain-doped region is formed on the tantalum layer and disposed on both sides of the second gate. The channel is disposed on the surface of the germanium layer below the second gate, wherein the surface of the channel is a 锗{110} crystal plane.

In an embodiment of the invention, the hole carrier (P-type) planar field effect transistor structure further comprises a second stress layer disposed in the hole carrier (P type) source/drain doped region. Above, wherein the lattice size of the second stress layer is larger than the lattice size of the germanium layer.

The present invention provides a lattice [112] lattice orientation parallel to the surface of the {110} layer The three-dimensional structure is formed, so that a ruthenium field effect transistor structure including a vertical side surface of 锗{111} crystal plane can be fabricated on the 锗{110} crystal plane.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

10‧‧‧ Single crystal layer

10a‧‧‧Single side of the single crystal layer

11‧‧‧Single crystal layer surface

12‧‧‧ Single crystal layer

Θ‧‧‧锗[110] The angle between the lattice direction and the [112] lattice direction

⊙‧‧‧The direction of the [112] lattice perpendicular to the layer of paper

200, 300‧‧‧ base

210‧‧‧锗

Channel surface of 210P‧‧‧P type planar field effect transistor structure

210S‧‧‧P+ source region

210D‧‧‧P+ type bungee area

211‧‧‧锗layer surface

220, 320‧‧‧锗 three-dimensional structure

220a, 320a‧‧‧锗 top surface of the three-dimensional structure

Side wall surface of 220b, 320b‧‧‧锗 three-dimensional structure

220S, 221S‧‧‧N+ source region

220D, 221D‧‧‧N+ type bungee area

230‧‧‧ mask

240‧‧‧Insulation structural layer

241, 330‧‧ ‧ gate dielectric layer

250, 340‧‧‧ conductive structure

260‧‧‧ first gate

261‧‧‧First gate sidewall

270‧‧‧N-type fin field effect transistor structure

271‧‧‧First stress layer

280‧‧‧second gate

290‧‧‧P type planar field effect transistor structure

291‧‧‧Second stress layer

301‧‧‧Base surface

310‧‧‧Insulation

310a‧‧‧Insulation opening

350‧‧‧ gate

1A to 1C are graphs showing the lattice and crystal plane orientation of a single crystal germanium layer.

2A to 2E are partial structural views showing an embodiment of the present invention.

3A to 3D are partial structural views showing another embodiment of the present invention.

In order to facilitate the description of the present invention, a ruthenium field effect transistor structure including a vertical side surface of a 111{111} crystal plane is formed on the 锗{110} crystal plane, and FIGS. 1A to 1C are for specific (110). The single crystal ruthenium layer is in the three-dimensional coordinate system, and its crystal faces are marked with a specific relationship with the lattice direction.

See the xyz right-angled stereograph shown in Figure 1A. In Figure 1A, the vertical axis is labeled z-axis (along the <001> lattice direction), and the two horizontal axes are labeled x-axis (along the <100> lattice direction) and y The axis (along the <010> lattice direction), as a description of the single crystal germanium layer 10 is shown as a wafer-like disk, the center of which is located at the origin of the xyz stereo coordinates. The surface 11 of the single crystal germanium layer is a (110) crystal plane, and the vertical mark 图 in the figure indicates that the lattice direction perpendicular to the surface 11 of the single crystal germanium layer is <110> lattice direction, that is, the normal direction of the surface 11 of the single crystal germanium layer. The flat side 10a of the single crystal germanium layer 10 is Crystal face, its normal direction is Lattice direction. On the surface 11 of the single crystal germanium layer The lattice direction is rotated counterclockwise along the surface (the angle of Θ is about 54.7 degrees) on the surface 11 of the single crystal germanium layer. Lattice direction, or clockwise rotation of π-Θ angle on the surface of the single crystal germanium layer 11 Lattice direction.

Please refer to the plane plane coordinate diagram of the single crystal germanium layer (110) shown in FIG. 1B, and the vertical axis in FIG. 1B is denoted as the z-axis. On the surface 11 of the single crystal germanium layer Lattice direction (reverse direction is The direction of the crystal lattice is perpendicular to Lattice direction.

Referring again to the xyz rectangular solid coordinate diagram shown in FIG. 1C, the vertical axis of FIG. 1C is denoted as the z-axis, and the two horizontal axes are denoted by the x-axis and the y-axis, and the single crystal germanium layer 10 is illustrated as a single crystal germanium. On the surface 11 of the layer Extend to the opposite direction A vertical sectional perspective view made in the direction of the crystal lattice, which is perpendicular to the single-crystal tantalum layer 12, is a single crystal layer The lattice direction, that is, the slice 12 of the single crystal germanium layer is Planes.

Please refer to FIG. 1B again. It is worth mentioning that due to the symmetrical relationship, the surface of the single crystal layer is on the surface 11 The lattice direction is rotated clockwise along the surface (an angle of about 54.7 degrees) on the surface 11 of the single crystal germanium layer. Lattice direction (not shown) or counterclockwise rotation π-Θ angle is the opposite direction Lattice direction, by Extend to the opposite direction The vertical direction of the lattice direction is cut, and the obtained cut surface is Planes.

1A to 1C, the present invention can be vertically formed by cutting vertically along the [112] lattice direction on the surface of the single crystal germanium layer on a single crystal germanium layer having a {110} crystal plane on the surface. The surface is the three-dimensional structure of the {111} crystal plane. It should be noted that the [112] lattice direction on the surface of the single crystal germanium layer referred to in the present invention means that the [110] lattice direction on the surface 11 of the single crystal germanium layer is counterclockwise rotated along the surface or The π-turn angle is rotated clockwise, wherein Θ±5 degrees are within the range of the [112] lattice direction on the surface of the single crystal germanium layer defined by the present invention. In detail, it is a single crystal germanium layer defined by the present invention, which is rotated by a 50-60 degree angle counterclockwise from the [110] lattice direction of the surface 11 of the single crystal germanium layer surface or rotated 120-130 degrees clockwise. [112] lattice direction on the surface.

The present invention can further utilize a three-dimensional structure in which the vertical plane is a 锗{111} crystal plane to fabricate a skeletal field effect transistor having high-speed electron carrier mobility.

2A to 2E are partial schematic views showing the steps and structures of an embodiment of the present invention.

Referring to the cross-sectional view of FIG. 2A, a substrate 210 is formed on the substrate 200. The substrate 200 may be a germanium substrate, a bulk germanium, an insulating germanium germanium (SOI) or a compound semiconductor substrate, for example, arsenic. For gallium or the like, the surface 211 of the germanium layer is a {110} crystal plane. In the figure, ⊙ is marked as perpendicular to the 锗 [112] lattice direction of the paper surface. The method for forming the ruthenium layer may be: epitaxial growth of the ruthenium layer on the substrate; forming a buffer layer on the substrate, for example: a SixGey buffer layer, a regenerated ruthenium layer, wherein the ruthenium layer The excess layer in 210 can be used to adjust the difference in lattice size between the germanium layer and the heterogeneous substrate and to reduce the defect density in the germanium layer; (smart cut): after forming the tantalum layer 210 on another substrate, an oxide layer is grown between the substrate and the tantalum layer 210, the tantalum layer 210 is cut by the oxide layer, and the tantalum layer 210 is attached to the substrate 200, etc. The method forms a layer 210 on the substrate 200, which is not limited in the present invention. On the other hand, if a germanium layer is directly formed by using a heterogeneous substrate, since the lattice size of the germanium layer and the heterogeneous base material are different, a dislocation defect may occur in the structure of the germanium layer. The method of eliminating the above-mentioned difference in the defect can be performed by performing a reverse annealing process on the tantalum layer to eliminate the defective defect in the structure of the tantalum layer, according to the technique disclosed in the specification of the patent application No. 101117652.

Referring to the cross-sectional view shown in FIG. 2B, after the mask 230 is formed in the [112] lattice direction on the surface 211 of the enamel layer, a portion of the ruthenium layer is removed to form the ruthenium structure 220. Further, as disclosed in the above-mentioned Patent Application No. 101117652, the structure in which the defect of the tantalum layer and the substrate is poorly arranged is weak, and the difference between the tantalum structure 220 and the substrate joint interface is removed, and the three-dimensional structure is suspended on the substrate. The surface forms a bottom surface. In this embodiment, the bottom of the 锗-dimensional structure 220 can be fabricated to the interface between the ruthenium layer 210 and the substrate 200, even deep into the substrate 200, and the 锗-dimensional structure 220 includes the top surface 220a sidewall surface 220b. The top surface 220a is also a 锗{110} crystal plane. The sidewall surface 220b forms an axis perpendicular to the interface of the top surface 220a (as indicated by the arrow in FIG. 3D), and the axis extends in a direction parallel to the 锗[112] lattice direction of the 锗 layer, under which the sidewall surface 220b is a 111{111} crystal plane.

Referring to the cross-sectional view shown in FIG. 2C, an insulating structure layer 240 of an insulating material such as yttrium oxide is formed by chemical deposition or atomic layer deposition on the surface of the ruthenium layer including the 锗-dimensional structure. Next, a portion of the insulating structure layer 240 is removed to expose a portion of the germanium structure 220. Thereafter, a gate dielectric layer 241 is formed on a portion of the tantalum structure surface 220 with zirconium dioxide or other high dielectric constant insulating material, and the conductive structure 250 is coated with titanium or other metal material to cover the gate dielectric layer. The first gate 260 can be formed by 241. The first gate 260 covers a top surface 220a of the portion and a sidewall surface 220b. Then, an N-type dopant, such as phosphorus or arsenic, is doped in the exposed three-dimensional structure on both sides of the first gate 260 to form an electron carrier (N-type) source/drain-doped region. . The 锗-dimensional structure as shown in FIG. 2C can in turn produce a standard N-type fin field effect transistor having a vertical plane of 锗{111} crystal plane.

According to the technical solution provided by the present invention, a germanium structure having a vertical plane of 锗{111} crystal plane can be easily formed on a germanium layer having a surface of 锗{110} crystal plane, thereby producing high carrier migration. The rate of the N-type fin gate field effect transistor. In addition, the mobility of the hole carrier on the 锗{110} crystal plane is the highest, and therefore, in addition to the above-mentioned technical solution for manufacturing the N-type skeletal field effect transistor, the present invention can also utilize the 锗{110} crystal plane. The surface of the germanium layer is formed to form a P-type germanium planar field effect transistor, or a stressor may be further formed on the source drain region of the field effect transistor to further improve the electrical performance of the field effect transistor component.

Referring to the cross-sectional view of FIG. 2D, the germanium layer 210 includes a N-type fin field effect transistor structure 270, and may further include a P-type planar field effect transistor structure 290. The fabrication of the P-type planar field effect transistor structure 290 can be based on the general method of fabricating a planar field effect transistor, and will not be described here. The channel surface 210P under the second gate 280 in the P-type planar field effect transistor structure 290 is a 锗{110} crystal plane; the sidewall surface 220b of the vertical channel in the N-type fin field effect transistor structure 270 is 锗{110} crystal surface. An N-type fin field effect transistor structure 270 having a 锗{111} plane channel and a P-type planar field effect transistor structure 290 having a 锗{110} plane channel can be combined to form a complementary field effect with excellent electrical performance. Transistor (CMOS).

In detail, in the N-type fin field effect transistor structure 270, the N+ type source region 220S and the N+ type drain region 220D are disposed on both sides of the first gate 260, and the source region 220S and the drain region 220D are further disposed. A first stress layer 271 is disposed. The first stressor layer 271 can be completed as follows. First, the first gate sidewall 261 is formed to surround the sidewall of the first gate 260, and a portion of the dome structure is exposed. Next, in the exposed three-dimensional structure, a high concentration of N-type dopant is doped to form an N+ source region 220S and an N+ type drain region 220D. And on the surface of the N+ type source region 220S and the N+ type drain region 220D, the epitaxial growth lattice size is smaller than the N+ doped semiconductor material layer of germanium, for example: germanium (Si), germanium (SiGe), The first stress layer 271 is formed of germanium-carbon (SiGe: C) or germanium carbon (SiC). The first stress layer 271 can increase the electron mobility by generating tensile strain in the channel region. In addition, in view of the different carrier characteristics of the electron and the hole, the present invention may also select a semiconductor material having a lattice size larger than that of the germanium layer, for example, germanium tin (GeSn), P+ type of the P-type planar field effect transistor structure 290. On the source region 210S and the P+ type drain region 210D, a high concentration P-doped second stress layer 281 is formed. As shown in FIG. 2D, the first stressor layer 271 disposed in the N-type fin field effect transistor structure 270 and the second stress layer 291 disposed in the P-type planar field effect transistor structure 290 are lifted stress layers (raised) Type stressor), and in other embodiments, an embedded type stressor may also be formed.

Referring to the cross-sectional view shown in FIG. 2E, after forming the first gate sidewall 261 and exposing a portion of the three-dimensional structure, the three-dimensional structure of the partially exposed portion is removed, and the N+ source region 221S and the N+ type drain region 221D are removed. The surface is lower than the top surface 220a of the three-dimensional structure. Next, as described above, the first stressor layer 271 is formed on the N+ source region 221S and the N+ type drain region 221D to form an N-type fin field effect transistor structure 270 having an embedded stress layer.

3A to 3D are partial structural views showing another embodiment of the present invention.

Referring to the cross-sectional view of FIG. 3A, an insulating layer 310 is formed on the substrate 300. The substrate 300 may be a germanium substrate, a bulk germanium, an insulating germanium germanium (SOI) or a compound semiconductor substrate, for example, arsenic. Gallium and the like, the present invention does not limit this. The substrate surface 301 is a {110} crystal plane, and the ⊙ mark [112] lattice direction is perpendicular to the paper surface. A portion of the insulating layer is removed along the [112] lattice direction on the surface 301 of the semiconductor substrate to form at least one opening 310a.

Referring to the cross-sectional view shown in FIG. 3B, the germanium layer is epitaxially grown by {110} crystal plane on the surface of the substrate. The ruthenium layer includes at least one 锗 stereostructure 320 formed in the opening 310a. The 锗 stereostructure 320 includes a top surface 320a and a sidewall surface 320b, wherein the top surface 320a is a 锗{110} crystal plane. Referring again to the cross-sectional view of FIG. 3C, a portion of the insulating layer 310 is removed by etch back to expose a portion of the sidewall surface 320b.

Please refer to the perspective view of the three-dimensional structure 320 shown in FIG. 3D. An axis (shown by an arrow in the figure) is formed at a boundary between the sidewall surface 320b of the three-dimensional structure 320 and the top surface 320a. The axis extends in a direction parallel to the [112] lattice direction of the substrate, and the sidewall surface 320b is a 锗{111} crystal. surface. A gate dielectric layer 330 of the fin field effect transistor is formed on a portion of the germanium structure 320, and a conductive structure 340 is formed to cover the gate dielectric layer 330. The conductive structure 340 is combined with the gate dielectric layer 330 to form a gate. Extreme 350. The 锗 stereostructure 320 is in turn applicable to the fabrication of a skeletal field effect transistor having a vertical channel surface of 锗{111} crystal plane.

In summary, the technical solution of the present invention is to form a 锗-dimensional structure in a lattice direction parallel to the surface of the {110} 锗 layer, so that it can be easily formed on the 锗 layer of the 110{110} crystal plane. The ruthenium field effect transistor structure including the vertical side surface is a 111{111} crystal plane, thereby manufacturing a semiconductor element having excellent electrical performance.

Although the present invention has been disclosed above in the preferred embodiments, it is not intended to limit the present invention. The invention is to be understood as being limited by the scope of the appended claims.

300‧‧‧Base

310‧‧‧Insulation

320‧‧‧锗Three-dimensional structure

320a‧‧‧锗Top surface of the three-dimensional structure

320b‧‧‧锗Side structure of the side wall surface

330‧‧‧ gate dielectric layer

340‧‧‧Electrical structure

350‧‧‧ gate

Claims (10)

A skeletal field effect transistor structure comprising: a substrate; and a germanium layer formed on the substrate, the surface of the germanium layer being a germanium {110} crystal plane, the germanium layer comprising at least one germanium structure, The 锗 stereostructure comprises: a top surface, the top surface is a 锗{110} crystal plane; and a sidewall surface perpendicular to the top surface, the sidewall surface forming an axis at the interface with the top surface, the axis extending in parallel The surface of the tantalum layer is in the direction of [112] lattice, and the surface of the sidewall is a 锗{111} crystal plane. The frog-type field effect transistor structure according to claim 1, wherein the substrate is a substrate of a ruthenium, osmium or gallium arsenide material, and the surface of the substrate is a {110} crystal plane. The skeletal field effect transistor structure of claim 2, wherein the substrate comprises an oxide layer formed on the surface of the substrate, the oxide layer comprising at least one opening parallel to the surface of the substrate In the [112] lattice direction, the 锗 stereostructure is formed in the opening. The frog-type field effect transistor structure according to claim 1, wherein the 锗[112] lattice direction of the surface of the ruthenium layer refers to the [110] lattice direction of the surface of the ruthenium layer along the surface of the ruthenium layer Rotate counterclockwise at a 50-60 degree angle or clockwise at a 120-130 angle. The frog-type field effect transistor structure according to claim 1, further comprising: a dielectric layer formed on a portion of the surface of the 锗-dimensional structure; and a conductive structure covering the surface of the dielectric layer, wherein The conductive structure combines the dielectric layer to form a first gate; and an electron carrier (N-type) source/drain region is formed in the three-dimensional structure, and is disposed in the first Both sides of the gate. The frog-type field effect transistor structure of claim 5, wherein the 锗-dimensional structure further comprises a bottom surface, the bottom surface being located below the top surface and suspended above the substrate. The frog-type field effect transistor structure of claim 5, further comprising: a first gate sidewall surrounding the sidewall of the conductive structure; and a first stress layer disposed on the electron carrier On the sub (N-type) source/drain region, wherein the lattice size of the first stress layer is smaller than the lattice size of the germanium layer. The frog-type field effect transistor structure according to claim 7, wherein the surface height of the electron carrier (N-type) source/drain region is lower than the surface height of the top surface. The frog-type field effect transistor structure according to claim 5, wherein the 锗 layer further comprises at least one hole carrier (P type) planar field effect transistor structure, and the P type planar field effect transistor structure The method includes: a second gate disposed on the surface of the germanium layer; a hole carrier (P-type) source/drain region formed on the germanium layer, disposed on both sides of the second gate; and a channel And a surface of the germanium layer disposed under the second gate, wherein the surface of the channel is a 锗{110} crystal plane. The frog-type field effect transistor structure according to claim 9, wherein the hole carrier (P-type) planar field effect transistor structure further comprises a second stress layer disposed on the hole carrier ( P-type) on the source/drain region, wherein the lattice size of the second stress layer is larger than the lattice size of the germanium layer.