TW201427089A - Light-emitting chip and method of manufacturing same - Google Patents

Abstract

An illuminating chip includes a substrate and a first semiconductor layer, a luminescent layer, a second semiconductor layer and an electrode sequentially stacked on the substrate, and the luminescent wafer opens a trench extending from the top of the second semiconductor to at least the top of the first semiconductor layer, the luminescent layer The light emitted from the side is emitted outside the light-emitting chip via the groove. The light-emitting chip can meet the heat dissipation and light-emitting efficiency, and is suitable for industrial applications. The present invention also provides a method of making a light emitting wafer combination.

Description

Light-emitting chip and method of manufacturing same

The present invention relates to a wafer, and more particularly to an illuminating wafer and a method of manufacturing the same.

As an emerging light source, light-emitting diodes have been widely used in various applications. The light emitting diode generally includes a susceptor, a wafer mounted on the pedestal, and a package covering the wafer. The wafer is composed of a substrate and an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer which are sequentially grown on the substrate. The wafer also forms a P electrode and an N electrode on the N-type semiconductor layer and the P-type semiconductor layer, respectively, to be electrically connected to the pedestal, thereby introducing a current into the wafer to drive the luminescent layer to emit light.

However, the luminescent wafer generates heat when it is in operation. The larger the area of the wafer, the more the area through which the current flows, resulting in more heat generated, and the luminous efficiency of the wafer is also reduced. If the wafer area is reduced, although the amount of heat generation is reduced, the corresponding light output is also reduced, which also affects the luminous efficiency of the wafer.

Therefore, it is necessary to provide a light-emitting wafer that combines light emission and heat dissipation and a method of manufacturing the same.

An illuminating chip includes a substrate and a first semiconductor layer, a luminescent layer, a second semiconductor layer and an electrode sequentially stacked on the substrate, and the luminescent wafer opens a trench extending from the top of the second semiconductor to at least the top of the first semiconductor layer, the luminescent layer The light emitted from the side is emitted outside the light-emitting chip via the groove.

A method of manufacturing an illuminating wafer, comprising the steps of: providing a semiconductor structure bonded with a substrate, the semiconductor structure comprising a first semiconductor layer, a luminescent layer and a second semiconductor layer stacked in sequence; forming a groove in the semiconductor structure, and grooving from the second The top surface of the semiconductor layer extends at least to the top surface of the first semiconductor layer, and the light emitted from the side of the light-emitting layer is emitted outside the light-emitting chip through the opening.

Since the area through which the current flows through the light-emitting wafer is reduced by forming a trench on the light-emitting wafer, the heat generated when the light-emitting wafer is operated is reduced. Moreover, since the trench extends through the light emitting layer to the first semiconductor layer, the light emitted from the side surface of the light emitting layer can be emitted outside the light emitting chip via the groove, thereby offset the area of the light emitting layer due to the opening of the trench to some extent. Less of the reduction in light output. Therefore, the light-emitting chip can simultaneously take into consideration heat dissipation and light-emitting efficiency, and is suitable for industrial promotion and application.

Referring to FIG. 1-6, a method for fabricating an illuminating wafer 90 according to an embodiment of the present invention is shown, which mainly includes the following steps:

As shown in FIGS. 1-2, a semiconductor structure 20 to which a substrate 10 is bonded is provided. The semiconductor structure 20 includes a first semiconductor layer 30, a light emitting layer 40, and a second semiconductor layer 50 which are sequentially stacked on a substrate 10. The first semiconductor layer 30, the second semiconductor layer 50, and the light-emitting layer 40 are each made of a material such as gallium nitride. In the present embodiment, the first semiconductor layer 30 is a P-type semiconductor layer, the second semiconductor layer 50 is an N-type semiconductor layer, and the substrate 10 is a metal substrate. The semiconductor structure 20 is formed by sequentially growing the second semiconductor layer 50, the light emitting layer 40, and the first semiconductor layer 30 on a temporary substrate (such as a sapphire substrate, not shown), and then on the first semiconductor layer 30. The metal substrate 10 is bonded, and finally the temporary substrate is peeled off. The metal substrate 10 is preliminarily provided with a plurality of slits 100 before being bonded to the first semiconductor layer 30. These slots 100 can be formed in the substrate 10 by etching. The slots 100 include a plurality of first slots 102 and second slots 104 extending through the top and bottom surfaces of the metal substrate 10. Each of the first slots 102 has a cross section, and each of the second slots 104 has a rectangular cross section. The array of the first slots 102 is arranged in a central portion of the substrate 10, and the second slots 104 are arranged around the first slots 102 at the edge of the substrate 10. Each of the adjacent first slots 102 and second slots 104 collectively partitions the substrate 10 into a plurality of square island regions 106. These island areas 106 are arranged in an array, and adjacent island areas 106 are connected by a connecting section 108. The width of the connecting section 108 is much smaller than the width of the island area 106 and is approximately half the length of the island area 106.

Further, as shown in FIG. 3-4, a trench 200 having the same structure as that of the trench 100 of the substrate 10 is formed on the semiconductor structure 20 composed of the first semiconductor layer 30, the light-emitting layer 40, and the second semiconductor layer 50. These slots 200 can be formed by plasma etching. These slots 200 also penetrate the top and bottom surfaces of the semiconductor structure 20 to communicate with the slots 100 of the substrate 10. These slots 200 also include a plurality of first slots 202 and second slots 204. The structure and distribution of the first slot 202 and the second slot 204 of the semiconductor structure 20 are the same as those of the first slot 102 and the second slot 104 of the substrate 10. The semiconductor structure 20 is separated into a plurality of island regions 206 by a first trench 202 and a second trench 204. These island regions 206 are arranged in an array, and adjacent island regions 206 are connected by a connecting segment 208.

Finally, as shown in FIGS. 5-6, a transparent insulating layer 60 is implanted into the grooves 100, 200. The transparent insulating layer 60 extends from the bottom surface of the substrate 10 to the top surface of the second semiconductor layer 50 to completely fill the respective trenches 100, 200, thereby protecting the side surface of the semiconductor structure 20 exposed in the trench 200. In the present embodiment, the transparent insulating layer 60 is made of cerium oxide. The top surface of the transparent insulating layer 60 is flush with the top surface of the second semiconductor layer 50. Thereafter, a transparent conductive layer 70 is formed on the top surface of the second semiconductor layer 50 and the top surface of the transparent insulating layer 60 by sputtering, and an electrode 80 is formed on the transparent conductive layer 70 by evaporation to form the light-emitting wafer 90. . The transparent conductive layer 70 covers and connects the tops of all of the island regions 206 to evenly diffuse current drawn from the electrodes 80 into each of the island regions 206. In the present embodiment, the transparent conductive layer 70 is preferably made of indium tin oxide, and the electrode 80 is preferably made of a metal material.

In operation, the luminescent wafer 90 is placed on a metal pedestal (not shown) such that the substrate 10 is in direct contact with the metal pedestal. Current is introduced into the luminescent wafer 90 from the metal pedestal. The current sequentially flows through the substrate 10, the first semiconductor layer 30, the light-emitting layer 40, the second semiconductor layer 50, and the transparent conductive layer 70, and finally the light-emitting wafer 90 is taken out via the electrode 80. Since the semiconductor structure 20 is divided into a plurality of island regions 206 by using the slits 200, the area of the current required to flow through the light-emitting wafers 90 is reduced, so that the heat emitted from the light-emitting wafers 90 can be reduced. Moreover, since the sides of the light-emitting layer 40 of each of the island regions 206 are exposed in the slot 200, the light emitted from the side of the light-emitting layer 40 can be transmitted to the outside of the light-emitting chip 90 via the transparent insulating layer 60 and the transparent conductive layer 70, thereby To the extent that the reduction in light emission due to the reduction in the area of the light-emitting layer 40 is offset. In addition, a transparent conductive layer 70 is connected to the top of each of the island regions 206 so that current can be evenly distributed throughout each of the island regions 206 to make the light more uniform.

It can be understood that the slot 200 formed on the semiconductor structure 20 does not have to penetrate the first semiconductor layer 30, and may extend only to the top surface of the first semiconductor layer 30 to expose the side surface of the light-emitting layer 40. At this time, the light emitted from the side surface of the light-emitting layer 40 can also be emitted from the transparent insulating layer 60 filled in the slit 200 and the transparent conductive layer 70 covering the semiconductor structure 20. In this case, the substrate 10 does not need to form the slot 100 to retain the complete structure.

It is also understood that the slot 200 formed on the semiconductor structure 20 does not necessarily include the first slot 202 and the second slot 204, and may include only one of them, or may be different from the first slot 202 and The other slots of the second slot 204 are slotted (not shown). Accordingly, each island region 206 is not limited to being a square, and may be changed to other shapes depending on the shape of the slot 200.

It will also be appreciated that, in extreme cases, each of the first slots 202 may also be in communication with an adjacent first slot 202 or second slot 204 to eliminate connections between adjacent island regions 206 of the semiconductor structure 20. Segment 208 is to completely separate adjacent island regions 206. In this case, the substrate 10 does not form a corresponding slot 100 to maintain a complete top surface to support the separated island region 206, facilitating the subsequent filling of the transparent insulating layer 60. At this time, there is no direct connection between the adjacent island regions 206, and thus each can only be electrically connected to the electrode 80 through the transparent conductive layer 70, so that the current distribution will be more uniform.

It can also be understood that the first groove 202 of the semiconductor structure 20 and the inner circumferential surface of the second groove 204 may further be roughened by etching (not shown). Therefore, the probability that light rays are emitted from the side of the light-emitting layer 40 becomes large, so that the brightness of the light-emitting wafer 90 is improved.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

10. . . Substrate

100. . . Slotting

102. . . First slot

104. . . Second slot

106. . . Island area

108. . . Connection segment

20. . . Semiconductor structure

200. . . Slotting

202. . . First slot

204. . . Second slot

206. . . Island area

208. . . Connection segment

30. . . First semiconductor layer

40. . . Luminous layer

50. . . Second semiconductor layer

60. . . Transparent insulation

70. . . Transparent conductive layer

80. . . electrode

90. . . Wafer

1 shows a first step of a method of fabricating an illuminating wafer according to an embodiment of the present invention.

2 is a plan view of the substrate in the semi-finished product obtained after the step of FIG. 1.

Figure 3 shows the second step of the method of fabricating an illuminating wafer.

Figure 4 shows a top view of the semifinished product obtained after the step of Figure 3.

Figure 5 shows a finished luminescent wafer.

Figure 6 shows a top view of a fabricated luminescent wafer.

10. . . Substrate

100. . . Slotting

20. . . Semiconductor structure

30. . . First semiconductor layer

40. . . Luminous layer

50. . . Second semiconductor layer

200. . . Slotting

Claims (10)

An illuminating wafer comprising a substrate and a semiconductor structure, the semiconductor structure comprising a first semiconductor layer, a luminescent layer and a second semiconductor layer sequentially stacked on the substrate, wherein the illuminating wafer is opened from the top surface of the second semiconductor layer and penetrates the luminescent layer At least a slit extending to the top surface of the first semiconductor layer, the light emitted from the side of the light-emitting layer is emitted through the slit to the outside of the light-emitting chip. The illuminating wafer of claim 1, wherein the grooving extends through the first semiconductor layer to the top surface of the substrate, and the semiconductor structure is slotted into a plurality of island regions. The illuminating wafer of claim 2, wherein adjacent island regions are connected by a connecting segment. The luminescent wafer of claim 2, wherein the adjacent island regions are completely separated by a groove. The luminescent wafer of any one of claims 2 to 4, further comprising a grooved transparent insulating layer, the top surface of the transparent insulating layer being flush with the top surface of the second semiconductor layer. The luminescent wafer of claim 5, further comprising a transparent conductive layer covering the second semiconductor layer and the transparent insulating layer, the transparent conductive layer connecting each island region. A method of manufacturing a light-emitting wafer, comprising the steps of:
Providing a semiconductor structure bonded with a substrate, the semiconductor structure comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked in sequence;
A slot is formed in the semiconductor structure, the slot extends from the top surface of the second semiconductor layer through the light emitting layer and extends to at least the top surface of the first semiconductor layer, and the light emitted from the side of the light emitting layer is emitted outside the light emitting chip through the slot. The method of claim 7, wherein the slot extends to the top surface of the substrate to divide the semiconductor structure into a plurality of island regions, and the adjacent island regions are connected by a connecting portion. The method of claim 8, wherein the step of filling the trench in the semiconductor structure further comprises the step of filling the trench with a transparent insulating layer, the top surface of the transparent insulating layer being flush with the top surface of the second semiconductor layer. The method of claim 9, wherein the filling the transparent insulating layer further comprises the step of covering the transparent conductive layer on the top surface of the second semiconductor layer and the top surface of the transparent conductive layer, wherein the transparent conductive layer connects the island regions.