TW201413828A - Methods and apparatus for forming tantalum silicate layers on germanium or III-V semiconductor devices - Google Patents

Abstract

Described are apparatus and methods for forming tantalum silicate layers on germanium or III-V materials. Such tantalum silicate layers may have Si/(Ta+Si) atomic ratios from about 0.01 to about 0.15. The tantalum silicate layers may be formed by atomic layer deposition of silicon oxide and tantalum oxide, followed by interdiffusion of the silicon oxide and tantalum oxide layers.

Description

Method and apparatus for forming a bismuth ruthenate layer on a bismuth or III-V semiconductor device

Embodiments of the present invention generally relate to the field of semiconductor fabrication processes and components, and more particularly to methods and apparatus for forming a gate dielectric layer on a Ge or III-V semiconductor component.

Microelectronic components are fabricated on a semiconductor substrate as an integrated circuit in which various conductive layers are interconnected to each other to allow electronic signals to propagate within the component. An example of such a component is a complementary metal oxide semiconductor (CMOS) field effect transistor (FET) or MOSFET.

An exemplary FET or MOSFET includes a gate electrode on a gate dielectric layer on the surface of the germanium substrate. However, as CMOS technology continues to shrink and the number of transistors increases exponentially, total power consumption also increases, making the performance per watt of energy consumption an important figure-of-merit for today's performance microprocessors. Narrow-gap semiconductor-based materials, such as Ge and III-V components, allow next-generation logic transistors to operate at supply voltages below 0.5V because of their excellent low-field and high-field electron transport properties. This causes high-speed switching under low operating electric fields. Further scaling of triple gate MOSFETs with new channel materials requires scaling of high k/metal gate stacks with inverted layer thicknesses (T _inv ) below 1.3 nm. However, current gate stack materials do not meet these requirements for T _inv .

Therefore, there is a need for new materials for gate stacking of Ge and III-V family channel transistors, as well as methods and apparatus for forming such layers.

One aspect of the present invention is directed to a method of treating a substrate to provide a layer of bismuth ruthenate on the surface of the substrate. In various embodiments, the method comprises the steps of: depositing a ruthenium oxide layer on the substrate; depositing a ruthenium oxide layer on the ruthenium oxide layer; and diffusing the ruthenium oxide layer into the ruthenium oxide layer to provide A layer of bismuth acid. In one or more embodiments, the bismuth ruthenate layer has a Si/(Ta+Si) ratio in the range of from about 0.01 to about 0.15. In some embodiments, the Si/(Ta+Si) ratio is in the range of from about 0.03 to about 0.10. The substrate can have a tantalum or III-V semiconductor surface.

According to one or more embodiments, the ruthenium oxide layer may be diffused by annealing the substrate. Exemplary annealing temperatures can range from about 500 °C to about 1000 °C. In other embodiments, the yttria and yttria layers are internally diffused without annealing.

One or more embodiments provide that the yttria layer is entangled prior to diffusion. In some embodiments, the yttria layer has a Ta:O ratio of about 2:3. Alternatively, the cerium oxide layer can be stoichiometric.

The bismuth ruthenate layer may have a predetermined thickness. In some embodiments, the bismuth ruthenate layer has a thickness of less than about 2.5 nm.

According to some embodiments, one or more of the ruthenium oxide layer and the ruthenium oxide layer are deposited via atomic layer deposition.

The method may further comprise additional steps, such as atomic hydrogen cleaning the surface of the substrate prior to depositing the yttria layer. In one or more embodiments, the substrate is not exposed to air between atomic hydrogen cleaning and deposition of the tantalum oxide layer, and the substrate is not deposited between depositing the tantalum oxide layer and depositing the tantalum oxide layer Being exposed to the outside air.

Another aspect of the invention is directed to a method of treating a substrate to provide a bismuth ruthenate layer on a substrate having a ruthenium or III-V semiconductor surface. In this embodiment, the method comprises the steps of depositing a layer of ruthenium oxide on the substrate via an atomic layer deposition process, the substrate having a ruthenium or III-V semiconductor surface; Depositing a layer of ruthenium oxide on the ruthenium oxide layer; and annealing the substrate to provide a ruthenium ruthenate layer having Si/(Ta) in the range of about 0.01 to about 0.15 +Si) ratio. In some embodiments, the Si/(Ta+Si) ratio is in the range of from about 0.03 to about 0.10.

In one or more embodiments of this aspect, the ruthenium oxide layer is ruthenium-rich. In some embodiments, the yttria layer has a Ta:O ratio of about 2:3. In other embodiments, the yttria layer is stoichiometric.

The annealing temperature can range from about 500 °C to about 1000 °C.

Still another aspect of the present invention is directed to a substrate processing apparatus for forming a bismuth ruthenate layer having a predetermined Si/(Ta+Si) ratio. In this embodiment, the substrate processing apparatus includes: a first processing chamber for cleaning a substrate having a germanium or III-V semiconductor surface; a second process chamber, the second process chamber and the first process chamber Connected to deposit a layer of ruthenium oxide on the substrate; a third process chamber, the third process chamber is in communication with the second process chamber and is used to deposit a layer of ruthenium oxide on the substrate; And a control system in communication with the first, second and third process chambers for forming a bismuth ruthenate layer having a predetermined Si/(Ta+Si) ratio. The predetermined Si/(Ta+Si) ratio may range from about 0.01 to about 0.15. The first, second, and third process chambers can be in communication under load lockout conditions (ie, under vacuum).

In one or more embodiments, the apparatus further includes a fourth processing chamber in communication with the third processing chamber for annealing the substrate.

In some embodiments, the second and third process chambers are atomic layer deposition chambers.

The foregoing description has outlined the broad features and technical advantages of the invention. Those skilled in the art should understand that the specific embodiments disclosed may be readily utilized as a basis for alteration or design of other structures or processes within the scope of the invention. Those skilled in the art should also understand that such an equal construction does not depart from the spirit and scope of the invention as disclosed in the appended claims.

101‧‧‧ chamber cover

102‧‧‧ chamber wall

103‧‧‧Cell plate

104‧‧‧Cell controller

105‧‧‧temperature controller

106‧‧‧Precursor supply

107‧‧‧Precursor supply

108‧‧‧Inert gas supply

109‧‧‧Precursor valve

110‧‧‧Precursor valve

111‧‧‧Inert gas valve

112‧‧‧Precursor flow controller

113‧‧‧Precursor flow controller

114‧‧‧ Lifting mechanism

115‧‧‧ throttle valve

116‧‧‧Isolation valve

117‧‧‧Drainage line

118‧‧‧Drainage system

121‧‧‧Syringe

124‧‧‧Substrate process area

125‧‧‧ catheter

127‧‧‧ catheter

128‧‧‧ pump

129‧‧‧ catheter

131‧‧‧Draining duct

133‧‧‧Flow controller

134‧‧‧CPU

135‧‧‧ memory

136‧‧‧I/O

210‧‧‧Multi-chamber processing system

212‧‧‧Load lock chamber

214‧‧‧Load lock chamber

220‧‧‧First robotic arm

232‧‧‧Substrate processing chamber

234‧‧‧Substrate processing chamber

236‧‧‧Substrate processing chamber

238‧‧‧Substrate processing chamber

242‧‧‧Transfer chamber

244‧‧‧Transfer chamber

250‧‧‧Second robotic arm

253‧‧‧ Controller

254‧‧‧CPU

255‧‧‧ memory

256‧‧‧Input/Output (I/O) Circuit

262‧‧‧Processing chamber

264‧‧‧Processing chamber

266‧‧‧Processing chamber

268‧‧‧Processing chamber

The above-described features of the present invention can be understood in detail by reference to the embodiments, which are briefly described in the foregoing. FIG. It is to be understood, however, that the appended claims

1 shows a device in accordance with one or more embodiments of the present invention Schematic diagram.

2 is a schematic diagram of a cluster tool system in accordance with one or more embodiments of the present invention.

In order to avoid the absence of other gate stack materials, a new method of forming gate stack materials for Ge and III-V semiconductor components is provided. In detail, embodiments of the present invention provides a method based embodiment of the apparatus for forming a tantalum-rich layer TaSiO _x Ge and III-V group semiconductor element. TaSiO _x can be used as a common gate dielectric for Ge and III-V materials, thus enabling high-performance/low-power CMOS components using Ge-channel p-MOSFETs and III-V-channel n-MOSFETs.

Both cerium and cerium oxide (SiO ₂ ) are candidates for interfacial layers between Ge or III-V materials and high-k dielectrics. However, since the silicon atomic layer deposition (ALD) on a substrate having difficult Ge and Group III-V surface occurs, for example, is deposited on SiO ₂ based embodiment of the present invention, SiO ₂ is deposited more easily than pure silicon deposited film.

Further, cerium oxide (HfO ₂ ) has a similar dielectric constant as lanthanum pentoxide (Ta ₂ O ₅ ), but the use of HfO ₂ on SiO ₂ has a limitation of EOT proportionalization of 1.3 nm. However, it has been discovered that by depositing a ruthenium oxide layer and then depositing a ruthenium oxide layer, the ruthenium oxide layer can at least partially consume the ruthenium oxide layer to provide a ruthenium ruthenate layer. If the yttrium oxide layer is all consumed, the interface layer between the channel and the high-k dielectric layer will have a thickness of substantially zero. In one or more embodiments, this process can make very thin electrical oxide thicknesses (i.e., T _inv < 1.2 nm) possible.

Accordingly, one aspect of the present invention is based on processing a substrate to provide the tantalum layer silicate (TaSiO _x) a method on the surface of the substrate. As used herein, "substrate surface" refers to any substrate or surface of a material that is formed on a substrate, and film processing is performed on any substrate or surface of the material during the manufacturing process. For example, the surface of the substrate on which the treatment can be performed depends on the application including materials such as tantalum, niobium oxide, stretched niobium, tantalum insulator (SOI), carbon doped yttria, tantalum nitride, doped yttrium, yttrium. , gallium arsenide, glass, sapphire, and any other materials (such as metals, metal nitrides, metal alloys, and other conductive materials). The barrier layer, metal, or metal nitride on the surface of the substrate includes titanium, titanium nitride, tungsten nitride, tantalum and tantalum nitride, aluminum, copper, or any other conductor useful for component fabrication or conductive or non-conductive Barrier layer. The substrate can have a variety of sizes, such as 200 mm or 300 mm diameter wafers as well as rectangular or square panels. Substrates useful in embodiments of the present invention include, but are not limited to, semiconductor wafers such as crystalline germanium (e.g., germanium <100> or germanium <111>), hafnium oxide, tensile germanium, germanium, doped or undoped. Polycrystalline germanium, doped or undoped germanium wafers, III-V materials (such as GaAs, GaN, InP, etc.), and patterned or unpatterned wafers. The substrate can be exposed to a pretreatment process to grind, etch, reduce, oxidize, hydroxylate, anneal, and/or bake the surface of the substrate.

According to one or more embodiments, the substrate has a ruthenium or III-V material surface.

One aspect of the present invention is directed to a method of forming a ruthenium ruthenate layer on a substrate having a ruthenium or Group III-V material on its surface. The bismuth ruthenate layer can serve as an interface layer and a dielectric layer for the gate stack. In an embodiment of this aspect, the method comprises depositing a ruthenium oxide layer on a substrate having a ruthenium or III-V semiconductor surface And depositing a ruthenium oxide layer on the ruthenium oxide layer and then interdiffusion the ruthenium oxide layer and the ruthenium oxide layer to provide a ruthenium ruthenate layer.

According to one or more embodiments, the bismuth ruthenate layer has a Si/(Ta+Si) atomic ratio of less than 0.3, such as in the range of from about 0.01 to about 0.15. Although not wishing to be bound by any particular theory, it is desirable to have a higher amount of germanium (i.e., a Si/(Ta+Si) ratio of 0.3 or higher) because this reduces the gate material. k value. In some embodiments, the Si/(Ta+Si) ratio is in the range of from about 0.03 to about 0.10. The Si/(Ta+Si) ratio can be changed by changing the respective thicknesses of the ruthenium oxide layer and the ruthenium oxide layer before diffusion.

In some embodiments, the substrate is annealed to allow interdiffusion of the cerium oxide and cerium oxide layers. Suitable annealing temperatures can range from about 500 °C to about 1000 °C. Exemplary annealing temperatures can be about 500 ° C, about 600 ° C, about 700 ° C, about 800 ° C, about 900 ° C, or about 1000 ° C. However, in the case where the substoichiometric amount of oxygen present in the ruthenium oxide layer is such that the layer is a ruthenium-rich embodiment (i.e., the yttrium oxide layer has a formula of Ta ₂ O _<5 ), the heat formed by the Ta-O bond The dynamic driving force makes high temperature annealing unnecessary. Therefore, if a germanium-rich layer is used, little or no annealing is required to drive the diffusion.

Thus, in one or more embodiments, the yttrium oxide layer deposited on the substrate is ruthenium rich. In one or more embodiments, the Ta:O atomic ratio is in the range of from about 1:1 to about 1:2. In some embodiments, the hafnium oxide layer has a Ta:O atomic ratio of about 2:3, ie, a chemical formula having Ta ₂ O ₃ .

However, in other embodiments, the yttria layer is stoichiometric, i.e., has a Ta:O ratio of about 2:5.

The atomic layer deposition process allows the thickness of the yttrium oxide layer and/or the yttrium oxide layer Precise control of degrees. If an ALD process is used to deposit one or both of these films, the films can be thin and conformal. Thus, in some embodiments, both a ruthenium oxide layer and a ruthenium oxide layer are deposited in an ALD process. The ruthenium ruthenate film caused by ALD yttrium oxide and ALD yttrium oxide may have a smaller thickness and better conformality than the ruthenium ruthenate film formed by other methods. However, in an alternate embodiment, one or both of the ruthenium oxide layer and the ruthenium oxide layer are deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable deposition process.

In one or more embodiments, the deposition of the ruthenium oxide layer and the ruthenium oxide layer is controlled to provide a ruthenium ruthenate layer of a desired thickness. In various embodiments, the bismuth ruthenate layer can have a thickness of less than about 10 nm, about 7 nm, about 5 nm, about 4 nm, about 3 nm, about 2.5 nm, about 2 nm, about 1.5 nm, about 1 nm, or about 0.5 nm. In some embodiments, the thickness of the yttrium oxide layer prior to interdiffusion is less than about 1.5 nm, about 1.0 nm, or 0.5 nm.

Exemplary precursors for the formation of cerium oxide by ALD include tetraethyl decane (TEOS) and tris (dimethylamino) decane and others. Suitable oxidant co-reactants include, but are not limited to, H ₂ O and O ₃ .

Exemplary precursors for the formation of cerium oxide by ALD include, but are not limited to, penta(ethoxy)anthracene and penta(dimethylamino)phosphonium (PDMAT). Again, suitable oxidizing agents include, but are not limited to, H ₂ O and O ₃ .

In one or more embodiments, the method is performed under vacuum conditions (ie, at low pressure and without exposing the substrate to outside air). According to one or more embodiments, an inert gas such as nitrogen may be present in the chamber.

In the typical ALD process, the "A" precursor and the "B" precursor Alternating pulses or streams of matter may be used in pulsed delivery of multiple cycles of pulsed precursors and co-reactants (eg, A precursor pulse, B precursor pulse, A precursor pulse, B precursor pulse, A precursor) A film is deposited by a pulse of material, a pulse of B precursor, or the like. The surfaces are alternately exposed to the reactants "A" and "B" until the desired thickness of the film is reached. However, instead of pulsing the reactants, such gases can flow simultaneously from the gas delivery head or nozzle and the substrate and/or gas delivery head can be moved such that the substrate is sequentially exposed to the gases. Of course, the foregoing ALD cycle is merely an example of a wide variety of ALD process cycles in which the deposited layers are formed by alternating layers of precursors and co-reactants.

In some embodiments, a ruthenium oxide layer and/or a ruthenium oxide layer may be formed during a plasma enhanced atomic layer deposition (PEALD) process that provides sequential pulses of precursor and plasma. In a particular embodiment, the co-reactant can be related to a plasma. In other embodiments, involving the use of a plasma, during the plasma step, the reagent is substantially ionized during the process, although this only occurs upstream of the deposition chamber such that ions or other energized or luminescent species are not in direct contact. Deposited film (this configuration is often referred to as remote plasma). Thus, in this type of PEALD process, plasma is generated outside of the process chamber, such as by a remote plasma generator system. During the PEALD process, plasma can be generated from a microwave (MW) frequency generator or a radio frequency (RF) generator. Although plasma can be used during the deposition process disclosed herein, it should be understood that no plasma is required. In fact, other embodiments are directed to deposition processes under very mild conditions without plasma.

According to one or more embodiments, the substrate is further advanced before or after the formation of the ruthenium ruthenate layer, or between the deposition of the ruthenium oxide layer and the ruthenium oxide layer Reason. This further processing can be performed in the same chamber as any deposition chamber, or this further processing can be performed in one or more different processing chambers. In one embodiment, a layer of yttrium oxide is deposited in the first chamber, and the substrate having the yttrium oxide layer thereon is moved from the first chamber to a different second chamber for further processing. This second chamber may be a yttrium oxide deposition chamber. The substrate having the yttrium oxide layer thereon can be moved directly from the first chamber to a different process chamber, or the substrate having the yttrium oxide layer thereon can be moved from the first chamber to one or more A plurality of transfer chambers are then moved to the desired different process chambers. Alternatively, a ruthenium oxide layer and a ruthenium oxide layer may be formed in the same deposition chamber, and then the substrate having the two layers is transferred to a subsequent process chamber.

According to one or more embodiments, when the substrate is moved from one chamber to the next, the substrate is continuously under vacuum or "load lock" conditions and is not exposed to outside air. The transfer chamber is therefore under vacuum and is "pumped down" under vacuum pressure. An inert gas may be present in the process chamber or transfer chamber. In some embodiments, the inert gas acts as a purge gas to remove some or all of the reactants after forming a layer of ruthenium oxide or ruthenium oxide on the surface of the substrate. According to one or more embodiments, the purge gas is injected at the outlet of the deposition chamber to avoid movement of reactants from the deposition chamber to the transfer chamber and/or the process chamber. Therefore, the flow of the inert gas forms a curtain at the outlet of the chamber.

Other process chambers may include, but are not limited to, a deposition chamber, a cleaning chamber, and an annealing chamber. According to one or more embodiments, a hafnium oxide dielectric layer is deposited on the hafnium oxide layer by a deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). In a particular embodiment, via an atomic layer deposition process A layer of ruthenium oxide is deposited on the ruthenium oxide layer.

According to one or more embodiments, a substrate having a ruthenium or III-V semiconductor surface is cleaned prior to depositing a ruthenium oxide layer. In some embodiments, the cleaning process comprises atomic hydrogen cleaning. In order to avoid contamination of the surface of the cleaned substrate, the substrate can be under load lockout conditions, i.e., the substrate is not exposed to air between the atomic hydrogen cleaning and the deposited ruthenium oxide layer. After depositing the yttrium oxide layer, the substrate can be maintained under load lock conditions until the yttrium oxide layer is deposited.

Another aspect of the present invention is directed to a method of treating a substrate, the method comprising depositing a yttrium oxide layer on a substrate having a ruthenium or group III-V semiconductor surface via an atomic layer deposition process, and depositing an oxide via an atomic layer deposition process The tantalum layer is on the tantalum oxide layer, and the substrate is annealed to provide a tantalum ruthenate layer. Embodiments of this aspect may have any of the features described in the first aspect. In one or more embodiments, the bismuth ruthenate layer has a Si/(Ta+Si) atomic ratio in the range of about 0.01 to 0.15. In some embodiments, the Si/(Ta+Si) ratio is from about 0.03 to about 0.10.

Again, the ruthenium oxide layer can be stoichiometric or rich. In one or more embodiments, the yttria layer has a Ta:O atomic ratio in the range of from about 1:1 to about 1:2. In some embodiments, the Ta:O atomic ratio is about 2:3.

Yet another aspect of the present invention is directed to an apparatus for performing a process in accordance with any of the above-described embodiments. In particular, a device for forming a layer of bismuth ruthenate on a surface having a ruthenium or group III-V semiconductor is provided. In one or more embodiments, the device includes one or more process chambers. Each process chamber can have a chamber body, one or more syringes, and a control system. This device will provide a supply of precursor to the surface of the substrate to deposit a layer of ruthenium oxide and/or ruthenium oxide. Layer on the substrate. The device may also include components such as a temperature controller or a pressure controller.

Figure 1 shows an embodiment in accordance with this aspect of the invention. The chamber body includes a chamber cover 101, a chamber wall 102, and a chamber plate 103. The chamber cover 101, the chamber wall 102 and the chamber plate 103 define a substrate processing region 124, and a deposition reaction occurs on the surface of the substrate at the substrate processing region 124. The lifting mechanism 114 raises and lowers the substrate such that the substrate can be moved into and out of the substrate processing region by mechanical arm blades or other suitable transport mechanism. The apparatus can include a transfer valve (not shown) to move the substrate from the process area to the transfer chamber under controlled pressure to avoid exposure of the substrate to outside air.

The first precursor is provided by the precursor supply 106, which is delivered to the process area 124 via conduit 125, which may be any suitable for transporting the precursor to the process area 124 at a suitable flow rate through the injector 121. a conduit (such as a pipe or passage). The first and second precursors can be dispersed from the same syringe, or multiple syringes can be used to avoid mixing prior to reaching the substrate processing region. Any suitable flow configuration can be used to flow the precursor into the substrate processing region, including cross flow or top-down flow. The injector 121 can include any mechanism for dispersing the reactants into the processing region of the substrate, including a showerhead or baffle.

The precursor supply can be any suitable precursor source, including a precursor gas cylinder or a production system to produce a precursor gas. The flow of the first precursor gas to the chamber is regulated by the precursor valve 109 and the precursor flow controller 112, and the precursor valve 109 and the precursor flow controller 112 can be in communication with the chamber controller 104. The flow controller 112 can be mass flow or volume flow control Device. A second precursor is provided by the precursor supply 107 and the second precursor is delivered to the process area 124 via the conduit 127 through the injector 121. The flow of the second precursor is regulated by the precursor valve 110 and the precursor controller 113, which may be a mass flow or volume flow controller. Valve 110 and flow controller 113 can be in communication with chamber controller 104. As shown in Figure 1, the first and second precursors can be separately delivered to the chamber via respective conduits 125 and 127. However, it is within the scope of the invention to mix the precursors prior to directing the gases into the chamber and transporting the precursors in a single conduit.

The inert gas supply 108 can be used to provide an inert gas as a purge gas via the inert gas conduit 129 to remove reactants and/or byproducts from the chamber body via the exhaust system 118. Additionally, the inert gas can act as a carrier gas to deliver reactants into the chamber by mixing the inert gas with one or both of the first precursor supply or the second precursor supply. If an inert gas is to be used as the carrier gas, the inert gas conduit includes a suitable internal connection (not shown) to connect the inert gas conduit 129 to one or both of the precursor gas conduit 125 and/or the precursor conduit 127. A suitable internal connection includes a valve and/or flow controller (not shown) in communication with the chamber controller 104. The inert gas valve 111 regulates the flow of inert gas to the chamber body. The flow controller 133 can also be used to regulate the flow of inert gas into the chamber.

The temperature controller 105 can control various heating and cooling components of the device (such as heating and/or cooling components for the chamber plate 103). The temperature controller maintains the temperature during deposition at or below the maximum temperature. In various embodiments, the maximum temperature can be 800 ° C, 700 ° C, 600 ° C, 500 ° C, 400 °C, 350 ° C, 300 ° C, 250 ° C, 200 ° C, 150 ° C, 100 ° C, 50 ° C, or even room temperature.

In one or more embodiments, the device can include an exhaust system 118 to remove gas from the chamber body. Pump 128 is in fluid communication with discharge line 117, which is connected to the chamber via a discharge conduit 131 that removes excess of the yttrium oxide layer and/or yttrium oxide layer formation process from process region 124 when the layer has been deposited. Reactants and by-products. Isolation valve 116 can be used to isolate the chamber body from pump 128. The throttle valve 115 can be used to adjust the pressure in the chamber body to achieve the desired pressure in the process region 124.

In one or more embodiments, various components of the device, such as precursor flow controller 112, precursor flow controller 113, and temperature controller 105, are controlled by chamber controller 104, which is provided by chamber controller 104 I/O control of the device. In a particular embodiment, the chamber controller 104 is in communication with various other control members to control the thickness of the ruthenium oxide layer and/or the ruthenium oxide layer or the final ruthenium ruthenate layer. The chamber controller 104 can control the amount of precursor delivered to the process chamber region such that the formed layer has a predetermined thickness. The chamber controller 104 can also control other factors (such as temperature and/or pressure in the process area) that can affect the thickness of the yttria layer and/or the yttria layer.

In some embodiments, the thickness of the hafnium oxide layer, the hafnium oxide layer, or the final hafnium niobate layer may be a predetermined thickness with respect to the desired properties of the gate stack. According to one or more embodiments, the predetermined thickness of the yttrium oxide layer is less than about 2 nm. In some embodiments, the predetermined thickness of the hafnium oxide layer is less than about 1 nm. The ruthenium ruthenate layer may also have a predetermined thickness, such as less than about 10 nm, about 7 nm, about 5 nm, about 4 nm, about 3 nm, about 2.5 nm, about 2 nm, about 1.5 nm, about 1 nm, or about 0.5 nm.

The chamber controller 104 can include a CPU 134, memory 135, and I/O 136 in wired or wireless communication with various controllers. The CPU 134 transmits signals to the precursor flow controller 112 and the precursor flow controller 113 and receives signals from the precursor flow controller 112 and the precursor flow controller 113 to control the first and second precursors to the injector 121. flow. The CPU 134 also transmits a signal to the throttle valve 115 and receives a signal from the throttle valve 115 to control the pressure in the process region of the substrate, so that the throttle valve 115 operates as a pressure control valve for the device. The CPU 134 can also be in communication with the isolation valve 116 and the pump 128 to further control the flow of emissions from the chamber.

The CPU can be in any of any form of computer processor that can be used in industrial equipment to control various chambers and sub-processors. Therefore, the CPU can be coupled to the memory 135, and the memory can be one or more of easily accessible memories, such as random access memory (RAM), read only memory (ROM), flash memory. , CD, floppy disk, hard drive, or any other form of local or remote digital storage device. A support circuit (not shown) can be coupled to the CPU to support the CPU in a conventional manner. These circuits include caches, power supplies, clock circuits, input/output wiring, subsystems, and the like. CPU 134 and memory 135 are coupled to appropriate I/O circuitry 136 to communicate with various controllers of the apparatus.

In an atomic layer deposition type chamber, the substrate can be exposed to the first and second precursors in a spatial or temporary separation process. Temporary ALD is a conventional process in which a first precursor flows into a chamber to react with a surface. The first precursor is purged from the chamber prior to flowing the second precursor. In space ALD, both the first and second precursors are simultaneously flowed into the chamber, but spatially separated, There is therefore a region between the flows that avoid mixing of these precursors. In space ALD, the substrate must be moved relative to the gas distribution plate, or vice versa.

The substrate can be processed in a single substrate deposition chamber where a single substrate deposition chamber is loaded, processed, and unloaded before another substrate is processed. The substrate can also be processed in a continuous manner, similar to a conveyor belt system in which a plurality of substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The shape of the chamber and the associated conveyor system can form a straight path or a curved path. Additionally, the process chamber can be a turntable in which a plurality of substrates are moved about a central axis and exposed to deposition gases at different locations.

The control system can further include a computer readable medium having a set of machine executable instructions. These instructions may cause the apparatus to perform any of the foregoing methods when executed by the CPU. In one embodiment, the instructions relate to a method of exposing a substrate surface to one or more precursors to form a ruthenium oxide layer or exposing the substrate surface to one or more precursors to form a ruthenium oxide layer. The instructions may also be directed to exposing the surface of the substrate to a co-reactant such as an oxide. The control system can control the deposition of the ruthenium oxide and ruthenium oxide layers such that the final ruthenium ruthenate layer has a Si/(Ta+Si) ratio of from about 0.01 to about 0.15 or from about 0.03 to about 0.10.

In another embodiment, the instructions are directed to a method comprising: exposing a surface of a substrate to one or more precursors to provide a ruthenium oxide layer; and processing a substrate having a ruthenium oxide layer thereon Moving the area to the transfer chamber; moving the substrate from the transfer chamber to the deposition chamber; and depositing a layer of ruthenium oxide On the yttrium oxide layer.

In addition to the yttria and yttria deposition chambers, the device may include other chambers. These chambers may include a transfer chamber and additional process chambers (such as a deposition chamber, a cleaning chamber, and an annealing chamber). These chambers can be internally connected in a "cluster tool system."

In general, a cluster tool is a modular system that includes a plurality of chambers that perform various functions including substrate center finding and orientation, degassing, annealing, deposition, and/or etching. According to an embodiment of the invention, the cluster tool includes at least one first chamber configured to deposit a layer of ruthenium oxide. A plurality of chambers of the cluster tool are mounted to the central transfer chamber, the central transfer chamber containing a robotic arm adapted to transport the substrate between the chambers. The transfer chamber is typically maintained under vacuum and provides an intermediate platform for transporting the substrate from one chamber to another and/or to a load lock chamber disposed at the front end of the cluster tool. Two known clustering tools that may be suitable for use in the present invention are Centura® and Endura®, both of which are available from Applied Materials, Inc., of Santa Clara, California. The details of one such a platformed vacuum substrate processing apparatus are disclosed in U.S. Patent No. 5,186,718, issued to Feb. However, the correct arrangement and combination of such chambers can be varied for the purpose of performing the specific steps of the process as described herein.

FIG. 2 illustrates an example of a cluster tool or multi-chamber processing system 210 that may be used in connection with an aspect of the present invention. Processing system 210 may include one or more load lock chambers 212, 214 to transport substrates into and out of system 210. Typically, since the system 210 is under vacuum, the load lock chamber 212, 214 can "pump down" the substrate introduced into system 210. The first robot arm 220 can transfer the substrate between the load lock chambers 212, 214 and the first set of one or more substrate processing chambers 232, 234, 236, 238. Each of the process chambers 232, 234, 236, 238 can be configured to perform a number of substrate processing operations. For example, process chamber 232 can be an etch processor designed to perform an etch process, and process chamber 234 can be a deposition reaction chamber to perform ALD or CVD, or designed to form heat on a substrate Rapid thermal processing (RTP) or RadOx® chamber for the oxide layer. Process chambers 236, 238 may also be provided to provide, for example, cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning. , heat treatment (such as RTP), plasma nitriding, degassing, orientation, hydroxylation and other substrate processes.

The first robot arm 220 can also transport the substrate to/from one or more of the transfer chambers 242, 244. The transfer chambers 242, 244 can be used to maintain vacuum conditions while allowing the substrate to be transported within the system 210. The second robotic arm 250 can transfer the substrate between the transfer chambers 242, 244 and the second set of one or more process chambers 262, 264, 266, 268. Like process chambers 232, 234, 236, 238, process chambers 262, 264, 266, 268 can be configured to perform various substrate processing operations, except for cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor phase Deposition (CVD), physical vapor deposition (PVD), epitaxial deposition, etching, pre-cleaning, chemical cleaning, heat treatment (such as RTP/RadOx®), plasma nitridation, degassing and orientation, including etching processes. Any of the substrate processing chambers 232, 234, 236, 238, 262, 264, 266, 268 can be removed from the system 210 if not desired.

By performing this process in a chamber on a cluster tool, the substrate can be protected from surface contamination by atmospheric impurities and a thin conformal tantalum ruthenate film can be provided.

Applied Materials, Inc., of Santa Clara, Calif., provides a substrate processing chamber that includes a process called RadOx® to form a thin layer of hafnium oxide for CMOS transistor gates. The RadOx® process heats the substrate with a lamp and injects hydrogen and oxygen into the process chamber. These gases form free radicals when these gases strike the surface of the substrate. Free radicals are more reactive than neutral species, providing a layer growth rate that is faster than the layer growth rate that can be achieved by a so-called in-situ steam generation (ISSG) oxide growth steam process.

A suitable etching or cleaning chamber can be provided for wet or dry etching, reactive ion etching (RIE), or the like. Exemplary etch chamber comprising SICONI ^TM, Producer®, or Carina ^TM chamber, the chambers may be obtained from Kelao La, California Applied Materials, Inc. of Santa. A non-limiting exemplary dry etching process may include ammonia (NH ₃ ) or nitrogen trifluoride (NF ₃ ) gas or any anhydrous hydrogen fluoride (HF) gas mixture and a remote plasma, such as at a low temperature (eg, about 30) °C) is condensed on SiO ₂ and reacted to form a compound that can sublime at moderate temperatures (eg, >100 ° C) to etch SiO ₂ . Such an exemplary etch process will shrink over time and eventually saturate to the extent that no further etch occurs (unless a portion of the compound is removed (eg, by the sublimation process described above)). The etching process can be controlled using the above mechanisms and/or by a timed etching process (e.g., etching for a predetermined period of time). An exemplary wet etch process can include hydrogen fluoride (HF) or the like. An exemplary plasma or remote plasma etching process can include one or more etchants (such as carbon tetrafluoride (CF ₄ ), trifluoromethane (CHF ₃ ), sulfur hexafluoride (SF ₆ ), hydrogen ( H ₂ ), or the like, and can be performed with or without a heating jig.

In a particular embodiment, a process is performed that includes a first step in which the robotic arm 220 moves the substrate from one of the load lock chambers 212, 214 to the deposition chamber to form a ruthenium oxide layer. Alternatively, the substrate surface can be cleaned prior to depositing the ruthenium oxide layer, such as by atomic hydrogen cleaning. After depositing the yttrium oxide layer, the substrate can be moved into the load lock chambers 212, 214 or directly to the deposition chamber in a second step to form a ruthenium oxide layer. After depositing the yttrium oxide layer, the substrate can then be moved to other chambers for subsequent processing or the substrate can be moved to the load lock chambers 212, 214.

Controller 253 can be in any of any of a variety of forms of data processing systems that can be used in industrial equipment to control the general purpose of various secondary and secondary controllers. In general, controller 253 includes a central processing unit (CPU) 254 and other general components, and central processing unit (CPU) 254 is in communication with memory 255 and input/output (I/O) circuitry 256.

In an exemplary process, a substrate having a surface of a ruthenium or group III-V material is cleaned by atomic hydrogen cleaning and then transferred to a yttrium oxide deposition chamber under load lock conditions. The ruthenium oxide layer is formed on the surface of the cleaned substrate by an atomic layer deposition process. The substrate is then transferred to another deposition chamber under load lock conditions, wherein a layer of ruthenium oxide is formed on the ruthenium oxide layer, such as by an atomic layer deposition process. By integrating these three in-situ processes into the cluster tool configuration, the yttrium oxide layer and the yttrium oxide layer can be formed without exposure to outside air or other contaminants. The deposition chambers may also be clustered with further processing chambers, such as annealing chambers, to diffuse the ruthenium oxide and ruthenium oxide layers to provide a ruthenium ruthenate layer.

In the present specification, "an embodiment", "an embodiment", "one or more embodiments" or "an embodiment" means that the description relates to a particular feature, structure, material or Features are included in at least one embodiment of the invention. Thus, the appearance of words such as "in one embodiment", "in a particular embodiment", "in an embodiment" or "in one embodiment" It necessarily means the same inventive embodiment. Further, the particular features, structures, materials, or characteristics may be combined in one or more embodiments in any suitable manner. The order of the above description of the method should not be construed as limiting, and the method may use the described operations, and may be omitted or added.

It should be understood that the above description is for the purpose of illustration and not limitation. Many other embodiments will be apparent to those skilled in the art in the <RTIgt; Therefore, the scope of the invention should be determined by reference to the scope of the appended claims and the scope of the equivalents.

101‧‧‧ chamber cover

102‧‧‧ chamber wall

103‧‧‧Cell plate

104‧‧‧Cell controller

105‧‧‧temperature controller

106‧‧‧Precursor supply

107‧‧‧Precursor supply

108‧‧‧Inert gas supply

109‧‧‧Precursor valve

110‧‧‧Precursor valve

111‧‧‧Inert gas valve

112‧‧‧Precursor flow controller

113‧‧‧Precursor flow controller

114‧‧‧ Lifting mechanism

115‧‧‧ throttle valve

116‧‧‧Isolation valve

117‧‧‧Drainage line

118‧‧‧Drainage system

121‧‧‧Syringe

124‧‧‧Substrate process area

125‧‧‧ catheter

127‧‧‧ catheter

128‧‧‧ pump

129‧‧‧ catheter

131‧‧‧Draining duct

133‧‧‧Flow controller

134‧‧‧CPU

135‧‧‧ memory

136‧‧‧I/O

Claims (20)

A method of treating a substrate, comprising the steps of: depositing a layer of ruthenium oxide on a substrate having a ruthenium or group III-V semiconductor surface; depositing a ruthenium oxide layer on the ruthenium oxide layer; The ruthenium oxide layer is diffused into the ruthenium oxide layer to provide a ruthenium ruthenate layer having a Si/(Ta+Si) ratio in the range of from about 0.01 to about 0.15. The method of claim 1, wherein the step of diffusing the ruthenium oxide layer comprises annealing the substrate. The method of claim 1, wherein the cerium oxide layer is cerium-rich. The method of claim 3, wherein the ruthenium oxide layer has a Ta:O ratio of about 2:3. The method of claim 1, wherein the cerium oxide layer is stoichiometric. The method of claim 1, wherein the Si/(Ta+Si) ratio is in the range of from about 0.03 to about 0.10. The method of claim 1, wherein the bismuth ruthenate layer has a thickness of less than about 2.5 nm. The method of claim 1, wherein one or more of the ruthenium oxide layer and the ruthenium oxide layer are deposited via atomic layer deposition. The method of claim 1, further comprising the step of: atomic hydrogen cleaning the surface of the substrate prior to depositing the yttrium oxide layer. The method of claim 9, wherein the substrate is not exposed to air between atomic hydrogen cleaning and depositing the yttria layer, and the substrate is not deposited between depositing the yttrium oxide layer and depositing the yttrium oxide layer. Being exposed to the outside air. A method of processing a substrate, comprising the steps of: depositing a ruthenium oxide layer on a substrate via an atomic layer deposition process, the substrate having a ruthenium or III-V semiconductor surface; and an atomic layer deposition process Depositing a ruthenium oxide layer on the ruthenium oxide layer; and annealing the substrate to provide a ruthenium ruthenate layer having a Si/(Ta+Si) in the range of about 0.01 to about 0.15 )proportion. The method of claim 11, wherein the cerium oxide layer is cerium-rich. The method of claim 12, wherein the ruthenium oxide layer has a Ta:O ratio of about 2:3. The method of claim 11, wherein the cerium oxide layer is stoichiometric. The method of claim 11, wherein the Si/(Ta+Si) ratio is in the range of from about 0.03 to about 0.10. The method of claim 11, wherein the substrate is annealed at a temperature in the range of from about 500 °C to about 1000 °C. A substrate processing apparatus comprising: a first processing chamber for cleaning a substrate, the substrate having a germanium or III-V semiconductor surface; and a second processing chamber a second process chamber is in communication with the first process chamber and is configured to deposit a layer of ruthenium oxide on the substrate; a third process chamber, the third process chamber is in communication with the second process chamber and is used Depositing a layer of ruthenium oxide on the substrate; and a control system, the control system being in communication with the first, second, and third process chambers for forming a bismuth ruthenate layer having A predetermined Si/(Ta+Si) ratio, wherein the first, second, and third process chambers are in communication under load lock conditions. The device of claim 17, further comprising a fourth processing chamber in communication with the third processing chamber for annealing the substrate. The device of claim 17, wherein the second and third process chambers are atomic layer deposition chambers. The device of claim 17, wherein the Si/(Ta+Si) ratio is in the range of from about 0.01 to about 0.15.