TW201419478A - Memory device using monopolar programmable metallization cell, integrated circuit and manufacturing method thereof - Google Patents

Abstract

A programmable metallization device includes a first electrode and a second electrode, and a dielectric layer, a conductive ion barrier layer and an ion supply layer connected in series between the first and second electrodes. In operation, a conductive bridge is used to enable a diode access device by forming or self-destructing in a dielectric layer using a bias having the same polarity to represent a data value. In order to form a conductive bridge, a sufficiently high bias voltage is applied, causing ions to penetrate the conductive ion barrier layer into the dielectric layer and then form a filament or bridge. In order to self-destruct the conductive bridge, a bias of the same polarity is applied, which causes current to flow through this configuration, while the ion flow is obstructed by the conductive ion barrier layer. As a result of Joule heat, any bridge in the dielectric layer will collapse.

Description

Memory device using monopolar programmable metallization cell, integrated circuit and manufacturing method thereof

The present invention relates to a Programmable Metallization Cell (PMC) technology.

Programmable Metallization Cell (PMC) technology has been explored for use in non-volatile memory, reconfigurable logic, and other switching applications due to its low current, good tunability, and high programming speed. The resistance switching of the PMC device is to grow and remove the conductive bridge by an electrochemical or electrolytic process. Therefore, the PMC device is also referred to as a Conducting Bridge (CB) device or an Electrochemical (EC) device.

The PMC device has an ON state and an OFF state. In the ON state, the conductive bridge can form a current path between the electrodes. In the OFF state, the conductive bridge is cut to prevent a current path from being formed between the electrodes. This PMC unit cell has a bipolar operating characteristic. Thus, when configured in a memory array, the underlying transistor is required to avoid currents flowing from the unselected cells of the ON state that hinder the read operation of the selected cell and other operations. In the case where a transistor is used as an access device, the density of the array is lowered, and the peripheral circuits are complicated.

A variety of three-dimensional (3D) memory concepts have been proposed to produce high density memory. September 2004, IEEE Transactions on Device and Materials Reliability Journal, Vol. 4, No. 3, Li et al of "a 3D-OTP Memory of SiO ₂ in the anti-fuse evaluation _{(Evaluation of SiO 2 Antifuse in a} 3D -OTP Memory)" Description Configured as a memory cell with a polysilicon diode and an antifuse. 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 24-25, Sasago et al. "Cross-point with 4F ² unit cell size driven by low contact resistivity polysilicon diodes" The phase change memory with 4F ² cell size driven by low-contact-resistivity poly-Si diode)" is described as a memory cell by a polycrystalline germanium diode and a phase change element. IEDM 09-617, (2009) pp. 27.1.1 to 27.1.4, Kau et al., "A stackable cross point phase change memory" describes a memory cell, The bidirectional threshold switch OTS included therein is an insulating device having one phase change element. These techniques rely on a combination of an insulating device and a memory component to construct a memory cell. The insulating device adds additional processing and thickness and/or area to the memory structure. Moreover, the insulating device/memory device method is not suitable for most 3D memory structures, including the so-called Bit Cost Scalable BiCS architecture and other 3D memory structures including a plurality of memory layers.

In IEDM 03-905, (2003), pages 37.4.1 to 37.4.4 of Chen et al. "Using a new threshold switching, self-rectifying chalcogenide device zero access transistor (0T/lR) non-volatile "Resistance-Transistor-Free (0T/lR) Non-Volatile Resistance Random Access Memory (RRAM) Using a Novel Threshold Switching, Self-Rectifying Chalcogenide Device) Zero-transistor/single-resistor 0T/1R memory cell with phase change element of separate isolation device. (Also, see U.S. Patent No. 7,236,394).

Therefore, it is desirable to provide a memory technology that is suitable for high density construction and that is easy to manufacture.

The present invention describes a memory device suitable for unipolar operation that includes a programmable metallization cell (PMC) that is a thermal reset architecture. The device comprises: a first electrode and a second electrode; a dielectric layer connected between the first and second electrodes, a conductive ion barrier layer and an ion supply layer, and the ion supply layer comprises ions of a suitable material a source to form a conductive bridge in the dielectric layer. The material of the conductive ion barrier layer is capable of preventing ions from diffusing from the ion supply layer to the dielectric layer during the reset operation and allowing sufficient ions to diffuse from the ion supply layer to the dielectric layer during the set operation to form a conductive bridge. The dielectric layer includes a material or materials that support the use of ions from the ion supply layer to electrolyze to form a conductive bridge in the dielectric layer. The device including the memory cell may have a support circuit for applying a first bias condition having a polarity between the first and second electrodes to initiate formation of a conductive bridge within the dielectric layer, and A second bias condition having one of the polarities is applied to initiate thermal decomposition of the conductive bridge in the dielectric layer.

The memory device of this type can be configured in an array, and the circuit can be coupled to the array to apply a bias voltage to the first and second electrodes for setting the memory in the set state to represent a first data. The value is used to set the memory in the reset state to indicate a second data value. To sense the data value, a read bias condition is applied to obtain a voltage or current level between the thresholds in the set and reset states.

The array can be an array of intersections, wherein the memory cell and the corresponding diode access device are formed in an interface between the plurality of word lines and the intersection of the plurality of bit lines. The array can include a plurality of two-dimensional intersection arrays stacked in a three-dimensional array.

Other embodiments and advantages of the invention will be apparent from the description, appended claims and claims.

Embodiments of the present invention are described in detail with reference to Figures 1-7.

Figure 1 shows a cross-sectional view of a PMC unit cell including a thermal reset configuration. The PMC unit cell includes a first electrode 100, which in this example includes a plug that is positioned within a via of one of the dielectric materials 111. The unit cell includes a dielectric layer 102 overlying the first electrode 100 and contacting the first electrode 100. Dielectric layer 102 can include any dielectric material that allows conductive ions to diffuse through the layer and form a conductive bridge through the PMC cell. The dielectric layer can be ceria, tantalum nitride, hafnium oxynitride, metal oxide, high K dielectric material or other material that can be electrolytically formed and destroyed through the dielectric bridge.

A conductive ion barrier layer 104 overlies the dielectric layer 102. The material of the conductive ion barrier layer 104 is susceptible to ion diffusion. The conductive ion barrier layer 104 is designed to pass sufficient ions to form a conductive bridge in the dielectric layer 102 under a first bias condition that results in a high electric field; and at one of the low electric fields Under two bias conditions, ions are blocked as current flows through this configuration to cause the conductive bridges in dielectric layer 102 to be thermally decomposed.

An ion supply layer 108 overlies the conductive ion barrier layer 104 to provide ions to form a conductive bridge through the dielectric layer 102. The ion supply layer 108 can include a chalcogenide layer, such as Ge _x Sb _y Te _z , where x, y, and z can be, for example, 2, 2, and 5, which also include a metal such as copper. The copper metal can react with the ruthenium in the chalcogenide to form a Cu-Te compound such as CuTe or Cu ₂ Te. Similarly, other materials that support the Cu-Te compound can be used. This Cu-Te can be easily decomposed to release copper ions that can diffuse into the dielectric layer 102, thereby causing the conductive bridge or monofilament to be formed within the memory cell. For embodiments using aluminum ions, the ion supply layer 108 can comprise aluminum metal.

Suitable materials for the conductive ion barrier layer 104 include nitrogen-containing conductive materials such as metal nitrides. For example, titanium nitride, tungsten nitride, and tantalum nitride are suitable materials. In an embodiment where the ion supply layer is a source of copper ions, the conductive ion barrier layer 104 is titanium nitride having a thickness of between about 3 and 6 nanometers. If the thickness of the conductive ion barrier layer 104 is too small, it cannot be thermally decomposed to achieve a unipolar reset because ions cannot be effectively prevented from entering the dielectric layer. If the thickness of the conductive ion barrier layer 104 is too large, it will hinder the setting operation or make the setting operation too slow. Therefore, for each material combination, the thickness can be determined empirically.

A second electrode 110 overlies the ion supply layer 108. The second electrode 110 includes a patterned copper metallization element or any other metallization technique that is compatible with adjacent layers.

A first bias condition having a first polarity may be applied between the first electrode 100 and the second electrode 110, which causes ions supplied by the ion supply layer 108 to migrate into the dielectric via the conductive ion barrier layer 104. In the electrical layer 102, a conductive bridge is established through a process such as electrochemical deposition. The conductive bridge can be sufficiently grown to electrically connect the first electrode 100 to the conductive ion barrier layer 104 such that the conductive bridge extends through the dielectric layer 102. This conductive bridge establishes a first resistive state of the PMC cell, with a relatively low resistance between the first electrode 100 and the second electrode 110. The resistive state in which the conductive bridge is present may be referred to as the "set" state for the memory cell.

A second bias condition having one of the same "first" polarities can be applied between the first electrode 100 and the second electrode 110, thereby causing a current to flow and causing resistive Joule heat in the dielectric layer 102. Resistance heating initiates thermal decomposition of the conductive bridge because the ions decompose and separate from the conductive bridge. The second bias condition is designed to induce a lower voltage than the first bias condition in this configuration. As a result of the second bias condition, the conductive ion barrier layer 104 allows current to flow while avoiding a sufficient amount of ions to migrate from the ion supply layer 108 into the dielectric layer 102 such that the conductive bridge cannot be maintained. The resistance heating induces thermal decomposition of the conductive bridge, thereby establishing a second resistance state in the PMC unit, and a relatively high resistance between the first electrode 100 and the second electrode 110. The resistance state of a non-conductive bridge can be referred to as a "reset" state for a memory cell.

Figures 2a-2c show a continuous phase or condition of a memory cell having the architecture of Figure 1 during a "set" operation of the cell to establish a set state for the cell that was initially reset. Figure 2a shows the PMC unit cell in a high resistance, first condition before forming a conductive bridge. The first condition corresponds to one of the first data values of the unit cell. As with the PMC cell configuration shown in FIG. 1, the PMC cell includes a dielectric layer 131 overlying and electrically contacting a first electrode 138. A first ion supply layer 134 is overlying the dielectric layer 131. The intermediate conductive ion barrier layer 136 is disposed between the dielectric layer 131 and the ion supply layer 134. A second electrode 139 overlies and is in electrical contact with the ion supply layer 134. The cell line shown in Figure 2a is in a reset condition in which a conductive bridge is not present in the dielectric layer 131.

Figure 2b shows the application of a set bias condition (indicated by arrow 150) having a first polarity to the unit cell for changing the unit cell from the reset state of Figure 2a to a set state. In this embodiment, the bias voltage includes applying approximately 4.5 volts to the second electrode 139 and applying approximately 0 volts or ground potential to the first electrode 138. This creates an electric field that tends to drive the positive metal ions to the first electrode so that the positive metal ions can be reduced to the metal form. Therefore, applying a bias voltage between the first and second electrodes 138 and 139 forms in the dielectric layer 131 by migrating metal ions into the dielectric layer 131 in a process such as electrochemical or electrolytic deposition. Conductive bridge 140. The conductive bridge 140 is sufficiently grown to contact the conductive bridge 140 in the dielectric layer 131 to the intermediate conductive ion barrier layer 136. Therefore, the unit cell in the set state exhibits a relatively low resistance.

The unit cell shown in Fig. 2c is that the set bias condition applied during the set operation is changed to a neutral bias condition. In a neutral bias condition, the conductive bridge 140 in the dielectric layer 131 establishes a relatively low resistance connection between the first and second electrodes and can be used to represent a data value.

Figures 3a and 3b show the operation when a reset bias condition (indicated by arrow 151) is applied. In this embodiment, the bias for resetting includes applying about 2 volts to the second electrode 139, and applying about 0 volts or grounding to the first electrode 138. This establishes an electric field to easily drive the positive metal ions toward the first electrode 138. However, as indicated by "X" in Figure 3a, under this reset bias condition, the conductive ion barrier layer 136 prevents ions from moving into the dielectric layer 131, such that the conductive bridge cannot be maintained. Again, during such reset bias conditions, current will flow, thereby causing resistive Joule heat in the dielectric layer, resulting in thermal decomposition of the bridge, as indicated by symbol 140a. Under conditions that impede the flow of ions from the ion supply layer, heat in the dielectric layer can cause the conductive path to be broken, resulting in a relatively high resistance state or a reset state, as shown in Figure 3b.

In this embodiment, both the set bias voltage and the reset bias voltage applied between the first electrode and the second electrode are positive. The PMC unit cell in this embodiment has a unipolar operating characteristic. In other words, under the set operation and the reset operation, the current flows in the same direction (from the second electrode to the first electrode).

Figure 4 is a function of current-voltage (IV characteristics) applied to a PMC unit cell (like the unit cell shown in Figure 1). Line 170 represents the current-voltage characteristic obtained by applying a bias condition to a cell that is initially in a high resistance state or a reset state, the biasing condition including applying a positive voltage to the upper electrode and grounding the lower electrode. As the voltage increases, the current through this cell is maintained low. Finally, ions from the ion supply layer begin to penetrate the ion barrier layer. When the threshold value V _TS (about 4.6 V in this example system), or has a sufficient number of ions to form a conductive bridge to transfer, to reduce the resistance of the cell, as shown in the fourth line of the transitions 170 to line 172, thereby achieving electrically conductive Condition or setting status.

For a cell that is initially in a low resistance set state and a conductive bridge has been formed in the dielectric layer, track 174 exhibits an IV characteristic at increased voltage. As the voltage increases, the current through the cell increases, thereby causing Joule heat in the dielectric layer. The conductive bridge collapses when sufficient thermal power has been applied and ions from the ion supply layer are blocked. In Fig. 4, this condition is at point 176 to reach the threshold voltage _VTR , so that the resistance of the unit cell increases and the current through the unit cell decreases.

We can see in Figure 4 that the read voltage can be quite low, such as about 1 V.

Due to the unipolar operation characteristics, the PMC unit cell in this embodiment can be implemented in a "1D/1R" memory array configuration. Figure 5 is a schematic diagram of a cross-point memory array using a "1D/1R" memory array, each cell having a diode access device. As shown in FIG. 5, each of the memory cells (e.g., 550, 551, 552, 553) of array 500 is represented by a resistive memory element and a diode, along the corresponding bit line 510a-510c. And the current path between the corresponding word lines 520a-520c. These diodes form an access array having a plurality of word lines, and a memory cell can be formed over the word lines. In another array configuration, other access devices including field effect transistors and bipolar transistors can be used.

The array includes a plurality of bit lines 510a, 510b, and 510c extending in parallel in a first direction and a plurality of word lines 520a, 520b, and 520c extending in a second direction (perpendicular to the first direction). This array 500 is referred to as a cross-point array because bit lines 510a-510c and word lines 520a-520c intersect each other but do not physically intersect, and the memory cell system with access devices is located intersection.

The memory cell 550 represents the memory cell of the array 500 and is disposed at the intersection of the "selected" bit line 510b and the "selected" word line 520b.

Reading or writing to the memory cell 550 of the array 500 can be accomplished by applying appropriate voltage pulses to the corresponding bit line 510b and word line 520b to result in the selected memory crystal. Cell 550 is a set, reset or read bias condition and applies an appropriate inhibit voltage to the unselected bit line and word line. The level and duration of the applied voltage depends on the operations performed, such as read operations, set operations, and reset operations. Applying a positive voltage to the selected bit line and applying a lower voltage (eg, ground potential or zero volts) to the word line, the diodes in cell 550 are forward biased to allow current flow in the cell . Thus, as shown, current path 543 is formed to the selected cell (e.g., cell 550). The bias voltage of the unselected bit line utilizes a negative voltage or is insufficient to turn on the voltage of the diode (relative to the voltage applied to the selected bit line). The bias of the unselected word line may also be insufficient to turn on one of the positive voltages of the diode (relative to the voltage applied to the selected bit line). The leakage current of the unselected cells in the array (eg, represented by leakage current paths 544 and 545) is hindered, as indicated by "X", because the two-pole system in these cells is reverse-biased, thus hindering the crystal The current in the cell flows.

As described above, an array implemented by using a cross-point cell can have a plurality of layers each having a plurality of bit lines and word lines to form a very high density memory device. It can also be used to implement other 3D architectures including a three-dimensional array in which a plurality of word lines and a plurality of bit lines are arranged to access memory cells of different layers.

Fig. 6 is a simplified flow chart showing the manufacture of the PMC unit cells shown in Figs. 2a to 2c. In this example, the word line acts as a plurality of cell lower electrodes along the word line. Thus, this process first involves forming a diode access array (or other access device), including word lines (190) having corresponding array contacts. Next, a dielectric material, an intermediate conductive ion barrier layer, and an upper ion supply layer are deposited on the top of the array contacts of the diode (eg, the contacts on the electrode 100), such as described above with reference to FIG. Illustrated (191). The stacked layers are then patterned to form a plurality of columns (192). A fill material is applied and planarized, and then a one-dimensional material is deposited on the structure (193). In the next step, the bit line material in the stacked layers is patterned, and the etching of the pattern is discontinued or below the contacts of the array (194). The bit lines thus formed are coupled to the row lines of the memory cell array, and form an insulated cell stack at the intersection of the word lines and the bit lines. Finally, a fill material is applied to complete a memory plane and the process is repeated to form multiple planes of the memory cell (195).

Figure 7 is a simplified block diagram of integrated circuit 300 including a non-volatile memory array 306 implemented by a "1D/1R" PMC cell array (having a thermal reset configuration). The integrated circuit can be one-time programmable, multi-programmable, and resistive random access memory. This array can include a diode-like access device.

The integrated circuit 300 includes a word line decoder 302 coupled and electrically coupled to a plurality of word lines 304 disposed along a column in the memory array 306. A bit line and (optional) plane decoder 308 is electrically coupled to a plurality of bit lines 310 disposed along the plurality of rows in the array 306 and in a plurality of planes for The memory cells in array 306 are read, set, and reset. The address on bus 312 is supplied to word line decoder 302 and plane/bit line decoder 308. The sensing circuit (sense amplifier) and data input circuitry in block 314 are coupled to the planar/bit line decoder 308 via data bus 316. The data is supplied to the data input circuit in block 314 via data input line 318 from the input/output ports on integrated circuit 300, or from other sources internal or external to integrated circuit 300. The integrated circuit 300 can include other circuits 320, such as a general purpose processor or special purpose application circuit, or a combination of modules that provide system single chip functionality supported by the array 306. The data is supplied from the sense amplifiers in block 314 to the input/output ports on the integrated circuit 300 via the data output line 322, or to other data objects internal or external to the integrated circuit 300.

The integrated circuit 300 includes a sensing circuit (in block 314) coupled to the memory cell of the array to sense a resistive state of a selected memory cell.

In this example, the controller 324 implemented using a bias configuration state machine controls the application of the bias circuit voltage and current source 326 for setting, resetting, and reading of word lines and bit lines. Voltage and / or current bias configuration. Controller 324 may be implemented using known special purpose logic circuitry. In an alternate embodiment, controller 324 includes a general purpose processor that may be implemented on the same integrated circuit to execute a computer program to control the operation of the device. In still other embodiments, a combination of special purpose logic circuitry and a general purpose processor may be used to implement controller 324.

The control circuit 324, 326 is coupled to the plurality of bit lines and the plurality of word lines to apply a bias voltage for operation of the memory cell, and the circuits of the control circuits 324, 326 can be in the first and second Applying a first bias condition having a polarity between the electrodes to form a conductive bridge within the dielectric layer, and applying a second bias condition having one of the polarities to induce a conductive bridge in the dielectric layer Thermal decomposition. In one example, the control circuits 324, 326 are coupled to a plurality of bit lines and a plurality of word lines for applying a bias configuration for operation of the memory cell, including:

a read bias configuration for sensing a resistance state of a selected memory cell;

a first write bias configuration having a polarity for forming a conductive bridge in a dielectric layer of the selected memory cell to establish a first resistance state in the selected cell;

A second write bias configuration having the same polarity for inducing thermal decomposition of a conductive bridge in a dielectric layer of a selected memory cell to establish a second resistance state.

Moreover, in one embodiment of the memory technology described herein, the memory cell array includes a three-dimensional array, and a plurality of word lines and a plurality of bit lines are configured to access the three-dimensional array. Memory cell of multiple memory layers.

The present invention describes a method of operating a programmable metallized cell array having a read mode that includes applying a read bias configuration to sense a resistive state of a selected memory cell; the method has a a first write mode, comprising applying a first write bias configuration having a polarity for inducing formation of a conductive bridge in a dielectric layer of the selected memory cell, thereby establishing a first a resistance state; and the method having a second write mode comprising applying a second write bias configuration having one of the polarities for inducing the conductive bridge in the dielectric layer of the selected memory cell Thermal decomposition, in order to establish a second resistance state.

The present invention has been described with reference to the preferred embodiments and examples, which are intended to be illustrative and not restrictive. It is to be understood that those skilled in the art will be able to devise modifications and combinations, modifications and combinations within the scope of the present invention and the scope of the following claims.

V _TR . . . Threshold voltage

V _TS . . . Threshold

100. . . First electrode

102. . . Dielectric layer

104. . . Conductive ion barrier layer

108. . . Ion supply layer

110. . . Second electrode

111. . . Interlayer dielectric material

131. . . Dielectric layer

134. . . First ion supply layer

136. . . Conductive ion barrier layer

138. . . First electrode

139. . . Second electrode

140. . . Conductive bridge

140a. . . Thermal decomposition of conductive bridge

150. . . Arrow

151. . . Arrow

170. . . line

172. . . line

174. . . Trajectory

176. . . point

500. . . Array

510a, 510b, 510c. . . Bit line

520a, 520b, 520c. . . Word line

543. . . Current path

544, 545. . . Leakage current path

550, 551, 552, 553. . . Memory cell

190-195. . . step

300. . . Integrated circuit

302. . . Character line decoder

304. . . Word line

306. . . "1D/1R" PMC array with thermal reset architecture

308. . . Planar/bit line decoder

310. . . Bit line

312. . . Busbar

314. . . Sense amplifier and data input circuit

316. . . Data bus

318. . . Data input line

320. . . Other circuit

322. . . Data output line

324. . . Control circuit for unipolar read, set, reset mode

326. . . Bias circuit voltage and current source

Figure 1 is a cross-sectional view of a PMC unit cell including a thermal reset configuration.

Figure 2a-2c shows the setting operation for the PMC unit cell (as shown in Figure 1).

Figure 3a-3b shows a reset operation for one of the PMC cells (as shown in Figure 1).

Figure 4 is a current-voltage function applied to a PMC cell with a thermal reset configuration.

Figure 5 is a configuration circuit diagram of a PMC cell in an array configuration of a 1D/1R cross-point plane.

Fig. 6 is a flow chart showing the manufacture of the PMC unit cell shown in Fig. 1.

Figure 7 is a simplified block diagram of the integrated circuit 300 illustrated in the present application, and the integrated circuit 300 includes a memory array implemented by a PMC cell.

100. . . First electrode

102. . . Dielectric layer

104. . . Conductive ion barrier layer

108. . . Ion supply layer

110. . . Second electrode

111. . . Interlayer dielectric material

Claims (18)

A memory device comprising a programmable metallization cell comprising:
a first electrode and a second electrode;
a dielectric layer, a conductive ion barrier layer and an ion supply layer are connected in series between the first and second electrodes, the ion supply layer comprising an ion source, the material of which is suitable for forming through the dielectric layer Conductive bridges. The memory device of claim 1, wherein the dielectric layer comprises a material or materials that support electrolysis of ions of the ion supply layer to form the conductive bridges through the dielectric layer. The memory device as claimed in claim 1, comprising:
a circuit for applying a first bias condition having a polarity between the first and second electrodes for inducing formation of the conductive bridges within the dielectric layer; and for applying the One of the polarity second bias conditions is used to initiate thermal decomposition of the conductive bridges in the dielectric layer. The memory device of claim 3, wherein the material of the conductive ion barrier layer blocks ions from diffusing from the ion supply layer to the dielectric layer during the second biasing condition, and at the first A sufficient amount of ions are allowed to diffuse from the ion supply layer to the dielectric layer during biasing conditions to form the conductive bridges. The memory device of claim 1, wherein the conductive ion barrier layer comprises a nitrogen-containing conductive material. The memory device of claim 1, wherein the conductive ion barrier layer comprises a metal nitride. The memory device of claim 1, wherein the ion supply layer comprises a source of copper ions. The memory device of claim 1, wherein the ion supply layer comprises a source of silver ions. The memory device of claim 1, wherein one of the ion supply layers comprises copper and tantalum. The memory device of claim 1, wherein the material of the ion supply layer comprises a chalcogenide and at least one of copper and silver. The memory device of claim 1, wherein the memory device comprises a plurality of unit cells comprising the programmable metallization unit cell formed in an array of intersections. The memory device of claim 1, wherein
The one or more materials of the dielectric layer are selected from the group consisting of a dielectric oxide and a dielectric nitride, and one or more materials of the conductive ion barrier layer are selected from the group consisting of metal nitrides. The one or more materials of the ion supply layer are selected from the group consisting of copper-containing or silver-containing chalcogenides. An integrated circuit comprising:
a plurality of bit lines and a plurality of word lines; and a memory cell array and a corresponding access device array coupled to the plurality of bit lines and the plurality of word lines, the arrays The memory cell includes a dielectric layer, a conductive ion barrier layer, and an ion supply layer connected in series between the corresponding word line and the bit line. The integrated circuit as described in claim 13 of the patent scope includes:
a sensing circuit coupled to the memory cell array for sensing whether a selected memory cell has a threshold lower than a read threshold; and a control circuit coupled to the bits And a plurality of biasing configurations for applying the memory cell to the memory cell, including:
a read bias configuration for sensing a resistance state of one of the selected memory cells;
a first write bias configuration having a polarity for inducing formation of a conductive bridge in the dielectric layer of the selected memory cell to establish a first resistance state in the selected cell And a second write bias configuration having the polarity for inducing thermal decomposition of a conductive bridge in the dielectric layer of the selected memory cell to establish a second resistance state. The integrated circuit of claim 13, wherein the access device array comprises a diode for each memory cell. A method of fabricating a device comprising a programmable metallization memory cell comprising:
Forming a first electrode;
Forming a dielectric layer, a conductive ion barrier layer, and an ion supply layer in series, the ion supply layer includes an ion source of one of the conductive bridge materials; and forming a second electrode in contact with the ion supply layer. The method of manufacturing of claim 16, wherein the material of the dielectric layer is used to electrolytically form and destroy a conductive bridge through the dielectric layer. The manufacturing method of claim 17, further comprising forming a plurality of memory cells, and an array of corresponding access devices.