TW201409633A - Wafer and carrier package structure - Google Patents

Abstract

A package structure of a wafer and a carrier, comprising a thin wafer carrier, a stable material layer, a wafer, and an injection material, the thin wafer carrier having a first line metal layer, a second line metal layer, a pad and a dielectric material layer, A line metal layer is embedded in the dielectric material layer and exposed to form a coplanar surface with the dielectric material layer, the solder pad protrudes from the coplanar surface and is connected to the first line metal layer, and the stable material layer is disposed in the coplanar The two sides of the plane form an accommodating space for accommodating the wafer, the pins of the wafer are connected with the pad, and the injection material is filled into the accommodating space under the wafer to make the connection stable, and the total thickness can be reduced because no mold sealing is required. And to save costs, in addition, by the solid structure to avoid bending of the thin wafer carrier, no need to consider compensation, can design a thinner, denser circuit.

Description

Wafer and carrier package structure

The invention relates to a package structure of a wafer and a carrier board, in particular to make a stable structure by using a thin carrier plate to accommodate a wafer.

Referring to the first figure, a schematic cross-sectional view of a prior art wafer and carrier package structure. As shown in the first figure, the package structure 1 of the prior art wafer and carrier includes a thin wafer carrier 10 composed of a first wiring metal layer 16, a second wiring metal layer 18 and a dielectric material layer 30, Wafer 50 and implant material 60 and glued molding material 90.

The first line metal layer 16 is embedded in the dielectric material layer 30 and forms a coplanar plane with the dielectric material layer 30, and the second line metal layer 18 fills another layer formed on the dielectric material layer 30. The surface is filled with holes of the dielectric material layer 30 to be connected to the first wiring metal layer 16. The thin wafer carrier 1 further includes a plurality of pads 24 protruding from the coplanar plane, and a solder mask 20 overlying the second surface layer 18 of the other surface and portion of the dielectric material layer 30.

The pins 52 of the wafer 50 are connected to the pads 24, and portions of the pads 52 and pads 24 are connected under the wafer 50 to fill the implant material 60. Finally, the wafer 50 and the thin wafer carrier 10 are encapsulated by a glue molding material 90.

A disadvantage of the prior art wafer and carrier package structure is that since the thickness of the thin wafer carrier 10 is between 70 and 150 μm, the fabrication of the thin wafer carrier and the process of wafer packaging are usually performed by different companies, due to The thin wafer carrier is thin, and it may cause problems such as bending and deformation when transporting or filling the injection material and encapsulating it with the plastic sealing material. Therefore, in order to compensate for the deviation, the circuit design is limited. The line width cannot be designed to be finer.

In addition, the thickness of the package structure of the wafer and the carrier is about 1.2 mm to 2.0 mm, which is obviously insufficient in the design of the light and thin electronic products, and the plastic sealing material for the Molding. Expensive, which also makes The cost is increased and not competitive in the market. Therefore, there is a need for a package structure that is capable of designing thinner wires and reducing overall thickness and cost.

The main object of the present invention is to provide a package structure of a wafer and a carrier, the package structure of the wafer and the carrier comprises a thin wafer carrier, a stable material layer, a wafer and an injection material, and the thin wafer carrier comprises a first wiring metal layer a second line metal layer, a solder resist layer, a plurality of pads, and a dielectric material layer, the first line metal layer being embedded in the dielectric material layer and exposed to form a coplanar surface with the dielectric material layer a second line metal layer is formed on the other surface of the dielectric material layer and fills a hole corresponding to the first line metal layer in the dielectric material layer to be connected to the first line metal layer. A plurality of pads protrude from the coplanar surface and are connected to the first wiring metal layer, the solder mask covers the other surface of the dielectric material layer, and covers a portion of the second wiring metal layer.

The solid material layer is disposed on both sides of the coplanar plane of the thin wafer carrier to form an accommodating space, and the stabilizing material layer comprises a lower bonding layer and a stable layer disposed on the bonding layer, and the stable structure can be Stabilize the thin wafer carrier to avoid bending while providing an accommodation space. The pins of the wafer are respectively connected to the pads, and the injection material is filled into the accommodating space under the wafer, so that the connection of the pads and the pads of the wafer is stabilized, so that the conventional glue-molding (Molding) is not required. The total thickness of the package structure 2 of the rear wafer and the carrier is 300 to 850 μm.

The invention is characterized in that the conventional thickness of the carrier and the wafer after the package can be reduced, and the cost is saved, and the thin wafer carrier is prevented from being bent by the stable structure, since the conventional glue molding is not required. It is possible to design a finer, higher density line arrangement without having to consider the compensation required for bending.

The implementation of the present invention will be described in more detail below with reference to the drawings and component symbols, so that those skilled in the art can implement the present specification after studying the present specification.

Referring to the second figure, a schematic cross-sectional view of a package structure of a wafer and a carrier of the present invention. As shown in the second figure, the package structure 2 of the wafer and carrier of the present invention comprises a thin wafer carrier 10, a solid material layer 40, a wafer 50, and an implant material 60. The thin wafer carrier 10 includes a first wiring metal layer 16, a second wiring metal layer 18, a solder resist layer 20, a plurality of solder pads 24, and a dielectric material layer 30. A first wiring metal layer 16 is embedded in the dielectric layer 16 The electrically material layer 30 is exposed and forms a coplanar surface with the dielectric material layer 30. The second wiring metal layer 18 is formed on the other surface of the dielectric material layer 30 and fills the dielectric material layer 30. The hole corresponding to the first line metal layer 16 is connected to the first line metal layer 16. A plurality of pads 24 project from the coplanar surface and are connected to the first line metal layer 16, the solder mask 20 covers the other surface of the dielectric material layer 30, and cover a portion of the second line metal layer 18.

The sturdy material layer 40 is disposed on both sides of the coplanar plane of the thin wafer carrier 10 to form an accommodating space. The stabilizing material layer 40 includes a lower bonding layer 40 and a stabilizing layer 44 disposed on the bonding layer. The stabilizing layer 44 can be glass fiber, plastic, or stainless steel. The stabilizing structure 40 can stabilize the thin wafer carrier 10 to avoid bending while providing an accommodation space.

The pins 52 of the wafer 50 are respectively connected to the bonding pads 24, and the filling material 60 is filled into the accommodating space below the wafer 50, so that the connection of the pins 52 and the pads 24 of the wafer 50 is stabilized, so that the conventional glue is not required. Molding, after packaging, the total thickness of the package structure of the wafer and the carrier is 300-850 μm.

Referring to the third figure, a cross-sectional view of another embodiment of the package structure of the wafer and the carrier of the present invention. As shown in the third figure, the package structure 3 of the wafer and the carrier of the present invention is substantially the same as the package structure 2 of the wafer and the carrier of the previous embodiment, and a second solder resist is further disposed on the coplanar plane. Layer 22, the second solder mask 22 covers a portion of the coplanar surface, but does not cover the pad 24, the stabilizing structure 40 is disposed on the second solder mask 22, and the wafer 50 is under the wafer as shown in the second figure. The accommodating space is filled with the injection material 60 to stabilize the connection of the pins 52 of the wafer 50 and the pads 24.

The invention is characterized in that it does not require a conventional plastic seal (Molding), which can reduce the total thickness of the carrier and the wafer after packaging, and save cost. In addition, by stabilizing the structure to avoid bending of the thin wafer carrier, it is possible to design a finer, higher-density line arrangement without consideration. Because of the compensation required for bending.

The above is only a preferred embodiment for explaining the present invention, and is not intended to limit the present invention in any way, and any modifications or alterations to the present invention made in the spirit of the same invention. All should still be included in the scope of the intention of the present invention.

1‧‧‧Package structure of wafer and carrier

2‧‧‧Package structure of wafer and carrier

3‧‧‧Package structure of wafer and carrier

10‧‧‧Thin wafer carrier

16‧‧‧First line metal layer

18‧‧‧Second line metal layer filled

20‧‧‧ solder mask

22‧‧‧Second solder mask

24‧‧‧ solder pads

30‧‧‧ dielectric material layer

40‧‧‧Steady structure

42‧‧‧Adhesive layer

44‧‧‧ stable layer

50‧‧‧ wafer

52‧‧‧ pins

60‧‧‧Injected materials

90‧‧‧Branding sealing material

The first figure is a schematic cross-sectional view of a package structure of a prior art wafer and carrier.

The second figure is a schematic cross-sectional view of the package structure of the wafer and the carrier of the present invention.

FIG. 3 is a cross-sectional view showing a package structure of a wafer and a carrier according to another embodiment of the present invention.

2‧‧‧Package structure of wafer and carrier

10‧‧‧Thin wafer carrier

16‧‧‧First line metal layer

18‧‧‧Second line metal layer filled

20‧‧‧ solder mask

24‧‧‧ solder pads

30‧‧‧ dielectric material layer

40‧‧‧Steady structure

42‧‧‧Adhesive layer

44‧‧‧ stable layer

50‧‧‧ wafer

52‧‧‧ pins

60‧‧‧Injected materials

Claims (4)

A package structure of a wafer and a carrier, comprising: a thin wafer carrier having a first line metal layer, a second line metal layer, a plurality of pads, and a dielectric material layer, the first line metal layer inlay And exposing to form a coplanar surface with the dielectric material layer, the second wiring metal layer being formed on the other surface of the dielectric material layer and filling the dielectric material layer Corresponding to the plurality of holes of the first line metal layer, and connected to the first line metal layer, the pads protrude from the coplanar surface and connected to the first line metal layer; a stable material layer is disposed Forming an accommodating space on the two sides of the coplanar plane, the stabilizing material layer comprises a bonding layer and a stabilizing layer disposed on the bonding layer; a wafer having a plurality of pins, the pins Connected to the pads respectively; and an implant material is filled into the accommodating space under the wafer to stabilize the connection of the pins and the pads of the wafer, wherein the total thickness after packaging is 300 ~850μm. For example, in claim 1, wherein the thin wafer carrier further comprises a solder mask covering the other surface of the dielectric material layer and covering a portion of the second wiring metal layer. For example, in the scope of claim 1, wherein the stabilizing layer is glass fiber, plastic, or stainless steel. For example, in claim 1, wherein the thin wafer carrier further comprises a second solder mask, the second solder mask covers a portion of the coplanar surface, but does not cover the pads, and the stable structure is disposed On the second solder mask.