TW201351175A - Circuit layout method for printed circuit board, eletronic device and computer readable recording media - Google Patents

Abstract

The present disclosure illustrates a circuit layout method for printed circuit board which is adapted for an electronic device. The circuit layout method includes the following steps. A parameters configuration interface is provided for receiving corresponding stack-up parameters and a plurality of layout parameters. A radio frequency layer, a first keep out layer and a reference layer is determined based on the stack-up parameters. The first keep-out layer is placed between the radio frequency layer and the reference layer with the radio frequency layer having a first signal trace. A first keep-out region on the first keep-out layer is formed in corresponding to the first signal trace. Circuit layouts lying inside the keep-out region are removed. Consequently, the corresponding keep-out region may be automatically generated in accordance to the signal requirements of the signal trace while designing the circuit layout thereby increase circuit layout quality and efficiency thereof.

Description

Printed circuit board layout method, electronic device and computer readable recording medium body

The present invention relates to an electronic device for a circuit layout method, and more particularly to a circuit layout method for a printed circuit board, an electronic device thereof, and a computer readable recording medium.

Generally speaking, in the layout design of a printed circuit board (PCB), specific signal lines are required according to the design requirements of the product, for example, a single-end trace or A differential trace is used to perform corresponding impedance control (such as configuring the corresponding line width, line spacing, length, thickness, etc.) to obtain the desired signal transmission quality.

In the layout design of the circuit, the reference copper foil plane layer corresponding to the signal line has a decisive influence on the impedance value controlled by the signal line whether adjacent or non-adjacent. Therefore, when the reference layer corresponding to the signal line on the printed circuit board is incorrect, the impedance value of the specific signal line may be shifted or misdirected, thereby affecting the transmission quality and stability of the signal line, resulting in product operation. System instability or even inability to move. Therefore, the finished printed circuit becomes a scrap product, increasing the time and cost of product development.

However, the current printed circuit board design software suppresses the above problem by the operator's signal line for each impedance control, and manually suppresses the area on the non-corresponding copper foil plane to avoid variation of the signal line impedance value. In addition, whenever the layout of the circuit is changed, the designer needs to re-adjust the suppression region of one signal line and one signal line at a time, thereby reducing design efficiency and easily causing omission of the operator. In addition, The detection method also needs to be checked by the operator in order, so it is easy to cause misjudgment or missed inspection, which makes the designed product operate abnormally and increases the production cost of the product.

In view of this, embodiments of the present invention provide a circuit layout method for a printed circuit board. The circuit layout method of the printed circuit board can actively establish a corresponding suppression area in the line layout according to the requirement of the signal quality during the line design, thereby improving the design quality and efficiency of the line layout, thereby increasing the good quality of the finished product. rate.

Embodiments of the present invention provide a circuit layout method for a printed circuit board, which is applicable to an electronic device. The method includes the following steps. First, a parameter setting interface is provided to receive layout layer parameters as well as complex layout parameters. Secondly, the signal layer, the first limiting layer and the reference layer are determined according to the layout layer parameters. The first confinement layer is between the signal layer and the reference layer and the signal layer has a first signal line. Thereafter, a first suppression region corresponding to the first signal line is generated in the first confinement layer. Subsequently, the layout of the lines within the first suppression area is excluded.

In one embodiment of the present invention, the step of the first limiting layer generating a suppression region corresponding to the first signal line includes setting a range of the first suppression region according to the layout parameters, wherein the first suppression region covers the first signal line The orthographic projection area of the first confinement layer.

In one embodiment of the present invention, the method further includes providing a pin suppression region around the surface adhesion component pin on the first signal line. Next, the range of the pin suppression area is determined according to the layout parameters. Then, the layout of the lines in the pin suppression area is eliminated.

In one embodiment of the invention, the method further includes providing a perforation pin suppression region around the perforation pin on the first signal line. then The range of the punch pin suppression area is determined according to the layout parameters. Subsequently, the layout of the lines within the perforation pin suppression area is eliminated.

In one embodiment of the present invention, the method further includes providing a via suppression region around the via hole on the first signal line. Next, the range of the via suppression region is determined according to the layout parameters. Then, the layout of the lines in the via suppression region is eliminated.

In one embodiment of the invention, the method further includes providing a copper foil planar suppression region around the plane of the copper foil on the first signal line. Next, the range of the copper foil planar suppression region is determined according to the layout parameters. Then, the layout of the lines in the plane suppression area of the copper foil is excluded.

In one embodiment of the present invention, the method further includes providing a trace suppression region around the first signal line. Next, the range of the trace suppression area is determined according to the layout parameters. Subsequently, the layout of the lines within the trace suppression area is eliminated.

In one embodiment of the present invention, the method further includes adjusting the first confinement layer according to a range of a surface adhesion element pin, a perforation pin suppression area, a via hole suppression area, a copper foil plane suppression area, and/or a line suppression area. The range of the first suppression zone on the top.

Embodiments of the present invention provide an electronic device including a display unit, a storage unit, and an operation processing unit. The display unit can be used to display the parameter setting interface. The storage unit is configured to store a plurality of layout layer parameters and a plurality of layout parameters. The operation processing unit may be configured to perform the following steps: providing a parameter setting interface to receive layout layer parameters and the layout parameters; determining a signal layer, a first restriction layer and a reference layer according to the layout layer parameter, wherein the first restriction layer is located at the signal layer and the reference Between the layers and the signal layer having a first signal line; generating a first suppression region corresponding to the first signal line at the first limiting layer; And the layout of the lines excluded from the suppression area.

In addition, an embodiment of the present invention further provides a computer readable recording medium for recording a set of computer executable programs. When the computer readable recording medium is read by the processor, the processor may perform the steps in the foregoing method.

In summary, an embodiment of the present invention provides a circuit layout method for a printed circuit board. The circuit layout method of the printed circuit board can actively generate multiple correspondences in a line layout according to layout layer parameters and layout parameters set by a designer. The suppression region of the impedance control signal line, wherein the line layout designer can adjust the range of the configuration suppression region at any time so that the signal line in the line layout conforms to the signal quality requirement of the product. Accordingly, the line layout designer can shorten the design time of the line layout by using the line layout method, and increase the accuracy of the line layout, thereby improving the design efficiency of the overall line layout, and reducing product development time and manufacturing cost.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

[First Embodiment]

Please refer to FIG. 1. FIG. 1 is a functional block diagram of an electronic device according to a first embodiment of the present invention. The electronic device 1 includes a display unit 10, an arithmetic processing unit 20, and a storage unit 30. The display unit 10 and the storage unit 30 are respectively coupled to the arithmetic processing unit 20. In this embodiment, the electronic device 1 can be implemented by a computer device, such as a desktop computer, a notebook computer, or a tablet computer, but the embodiment is not limited thereto.

The display unit 10 can be used to display a parameter setting interface (not shown in FIG. 1). And for the designer to input the parameter data corresponding to the layout of the printed circuit board. The parameter data may include layout layer parameters as well as layout parameters. Further, the layout layer parameters include a controlled signal layer layer and a corresponding restricted layer layer. The layout parameters include the definition of the layout object laid on the signal line, such as the surface mount component (SMD pin), the through hole (thru pin), the via (trans) and the copper foil shape, and the range of the suppression region. parameter.

The operation processing unit 20 is an operation core of the electronic device 1 and is used to generate a parameter setting interface and perform various analysis and calculation operations according to layout layer parameters and layout parameters input by the designer. The arithmetic processing unit 20 can generate a corresponding line layout through operation analysis according to the setting of the parameter setting interface. The operation processing unit 20 may be a processing chip such as a central process unit (CPU), a microcontroller, or an embedded controller, but the embodiment is not limited.

The storage unit 30 is configured to store a plurality of layout layer parameters and a plurality of layout parameters. It should be noted that, in this embodiment, the storage unit 30 may be implemented by using a volatile or non-volatile memory chip such as a flash memory chip, a read-only memory chip, or a random access memory chip, but The embodiment is not limited thereto.

Further, in this embodiment, the operation processing unit 20 can be configured to generate corresponding multiple suppressions according to the selected signal line in the line layout according to the layout layer parameters and the layout parameters set by the designer in the parameter setting interface. Area, and exclude the line layout within the suppression area to ensure the impedance value of the selected signal line. Thereby, the variation of the impedance value of the signal line can be avoided, and the signal line does not meet the requirements of the product specification, so that the printed circuit board with the line layout is scrapped.

Referring to FIG. 2A to FIG. 2C, FIG. 2A to FIG. 2C respectively show schematic diagrams of a printed circuit board according to a first embodiment of the present invention. 2A is a schematic diagram of a printed circuit board corresponding to a six-layer board. The signal layer 41 is the first of the six-layer boards and has the first signal line 411. The reference layer 45 is the third layer of the six-layer board and is a reference plane layer to which the first signal line 411 should correspond. The first confinement layer 43 is the second layer of the six-layer board, because it is not the reference layer corresponding to the first signal line 411, so as to exclude the second layer (ie, the first confinement layer 43) from the first signal line 411. The influence, such as impedance, transmission quality, and the like, needs to be suppressed in the region of the first confinement layer 43 corresponding to the first signal line 411. The first limiting layer 43 and the reference layer 45 are, for example, a power layer, a ground layer, or a general circuit layout layer, and the embodiment is not limited thereto.

In detail, when the designer inputs the layout layer parameters and the layout parameters corresponding to FIG. 2A on the parameter setting interface displayed by the display unit 10. The layout layer parameters and layout parameters are then stored in the storage unit 30. The arithmetic processing unit 20 determines the signal layer 41, the first confinement layer 43, and the reference layer 45 according to the layout layer parameters set by the designer as shown in FIG. 2B. Then, a first suppression region 47 corresponding to the position of the first signal line 411 is generated on the first restriction layer 43, and the line layout in the first suppression region 47 is excluded, so that the first signal line 411 only corresponds to the reference layer 45. Referring to the copper foil plane, it is possible to avoid that the first signal line 411 corresponds to the wrong reference plane as described above.

More specifically, the arithmetic processing unit 20 sets the range of the first suppression region 47 in accordance with the layout parameters and the layout parameters of the first signal line 411 (eg, line width, line spacing, length, etc.) in the layout. In other words, the first suppression region 47 generated by the arithmetic processing unit 20 covers the orthographic projection area of the first signal line 411 at the first restriction layer 43. worth it Note that this embodiment is described by a single-end trace, but in practice, the signal layer 41 may have a differential trace, for example, the first and second signals. The line is composed, and the range of the first suppression region 47 simultaneously covers the orthographic projection regions of the first and second signal lines.

Incidentally, if there are multiple confinement layers (ie, non-corresponding reference plane layers) between the signal layer 41 and the reference layer 45, the operation processing unit 20 may determine the restriction layer according to the layout layer parameters, and actively follow the sequence. Generating an orthographic projection region of the first signal line 411 on the corresponding signal layer 41 on the non-corresponding reference plane layers produces a corresponding plurality of suppression regions. For example, when the first limiting layer and the second limiting layer are present between the signal layer 41 and the reference layer 45, the operation processing unit 20 sequentially forms the first suppression on the first limiting layer and the second limiting layer, respectively. The region and the second suppression region cause the reference layer 45 to become the reference plane of the first signal line 411 on the signal layer 41.

For another example, if the first signal line 411 on the signal layer 41 and one of the signal lines on the fourth layer of the six-layer board are broadside coupled differential pairs, then the six-layer board The second layer is the first confinement layer, and the third layer of the six-layer board is the second confinement layer. Accordingly, after the arithmetic processing unit 20 calculates, the first suppression region and the second suppression region are respectively formed on the second layer and the third layer of the six-layer board.

Next, referring to FIG. 2C, the operation processing unit 20 may further set the suppression region 49 around the first signal line 411 on the signal layer 41 according to the layout parameter input by the designer, so as to prevent the adjacent component from affecting the first signal line 411. The impedance value, in turn, affects the signal quality of the first signal line 411.

Further, according to the design of the circuit layout, the first signal line 411 may be provided with a surface adhesive component pin (SMD pin), a piercing pin (thru pin), Via and copper foil shape, etc. Therefore, the arithmetic processing unit 20 can set the corresponding suppression region 49 according to the suppression region range configured in the layout parameter according to the first signal line 411 and the components disposed on the first signal line 411, respectively.

Specifically, the operation processing unit 20 can be provided with a pin suppression area (not shown), a punch pin suppression area (not shown), a via hole suppression area (not shown), and a copper foil plane suppression area (not shown). ) and the trace suppression area (not shown). The pin suppression region is located around the surface adhesion component pin on the first signal line 411. The perforation pin suppression region is located around the perforation pin on the first signal line 411. The via suppression region is located around the via on the first signal line 411. The copper foil plane suppression region is located around the plane of the copper foil on the first signal line 411. The trace suppression region is located around the trace on the first signal line 411.

In detail, the arithmetic processing unit 20 determines the range of the pin suppression region, the punch pin suppression region, the via hole suppression region, the copper foil plane suppression region, and the trace suppression region in accordance with the layout parameters. Then, the arithmetic processing unit 20 excludes the line layout in the pin suppression region, the punch pin suppression region, the via hole suppression region, the copper foil plane suppression region, and the wiring suppression region. At the same time, the arithmetic processing unit 20 can further adjust the first restriction layer 43 shown in FIG. 2B according to the range of the pin suppression region, the perforation pin suppression region, the via suppression region, the copper foil plane suppression region, and the trace suppression region. A range of suppression regions 47. Therefore, the influence of adjacent layout objects or adjacent non-corresponding reference layers in the line layout on the first signal line 411 can be eliminated, thereby improving the design quality and efficiency of the line layout.

In addition, the arithmetic processing unit 20 can also actively perform a comprehensive check on the line layout when the establishment of all the suppression regions is completed in the line layout. Specifically, the operation processing unit 20 can detect the routing parameters (eg, line width, line spacing, etc.) of the first signal line 411 and the corresponding reference layer definition according to a stack table to detect and determine the variation of the signal line impedance value. Offset.

It is worth mentioning that, referring to FIG. 3, FIG. 3 is a schematic diagram of a portion of a printed circuit board according to a first embodiment of the present invention. The stack table shown in Figure 3 can be generated by the designer through the external circuit board design software and used to detect the line layout. The stacked table of the printed circuit board may include the number of layers of the circuit board, the type of the layer, the properties of the signal line (such as a characteristic impedance line or a differential impedance line), the reference layer corresponding to the signal line, the impedance value of the signal line, and the signal. The relevant line parameters of the line, such as the line width and the line spacing, etc., the person skilled in the art of the present invention should be able to infer the actual generation and operation mode of the stack table, and therefore will not be described herein.

In more detail, the operation processing unit 20 can determine whether the impedance value of the first signal line 411 exceeds a predetermined impedance range by comparing the impedance value of the first signal line 411 with the impedance value data of the superposition table of FIG. 3. In addition, when the impedance value of the first signal line 411 exceeds a predetermined impedance range, the operation processing unit 20 generates an impedance value error detection data and displays it on the display unit 10 for the designer to browse. At the same time, the impedance value error detection data is stored in the storage unit 30. The designer can modify the line layout according to the impedance value error detection data so that the first signal line 411 is within the preset impedance value range.

The operation processing unit 20 can further detect whether the reference layer definition corresponding to the first signal line 411 is correct according to the superposition table data of FIG. 3 described above. In other words, the arithmetic processing unit 20 can determine whether the reference plane layer corresponding to the first signal line 411 is identical to the definition in the superficial table data through the comparison. The operation processing unit 20 can output the reference plane detection data when the reference layer is incorrectly defined. And displayed on the display unit 10 for the designer to browse and store in the storage unit 30. The designer can correct the line layout according to the reference plane detection data.

In addition, the operation processing unit 20 can detect and detect the established suppression region, that is, the first suppression region 47 on the first restriction layer 43 shown in FIG. 2B and the suppression region 49 of the signal layer 41 shown in FIG. 2C. Whether the line layout in the first suppression area 47 and the suppression area 49 has been excluded. As described above, the suppression region 49 may include a trace suppression region corresponding to the first signal line 411, a pin suppression region corresponding to the surface adhesion component pin of the first signal line 411, and a perforation pin corresponding to the first signal line 411. The perforation pin suppression region, the via hole suppression region corresponding to the via hole on the first signal line 411, and the copper foil plane suppression region corresponding to the copper foil plane on the first signal line 411. If the line layout is still provided in the established suppression area, the suppression area detection data is output and displayed on the display unit 10 for browsing by the designer and stored in the storage unit 30. The designer can then correct the line layout by excluding the line layout within the suppression area detection data.

An embodiment of the present invention further provides an embodiment of a parameter setting interface. Referring to FIG. 4, FIG. 4 is a schematic diagram of a parameter setting interface of the electronic device 1 according to the first embodiment of the present invention. The parameter setting interface 101 includes a signal layer setting menu 103, a restriction layer setting menu 105, a suppression area range setting field 107, and a layout object selection field 109. The designer can generate layout layer parameters by setting the signal layer setting menu 103 and the restriction layer setting menu 105. The designer can generate layout parameters by setting the suppression area range setting field 107 and the layout object check field 109.

The signal layer setting menu 103 is a pull-down menu for providing a designer to select a signal layer name with an impedance control signal line, such as the signal layer 41. The Restriction Layer Setup Menu 105, also a drop-down menu, is used to provide design The name of the layer to be restricted is selected, for example, the first restriction layer 43. The contents of the signal layer setting menu 103 and the restriction layer setting menu 105 can be set according to the actual needs of the designer, but the embodiment is not limited. The signal layer setting menu 103 and the restriction layer setting menu 105 can be regarded as setting interfaces of the layout layer parameters, but the embodiment is not limited thereto.

The suppression region range setting field 107 is used to provide a range in which the designer sets the corresponding signal line (ie, the trace) and the suppression region of the layout component (eg, pin, via or copper foil plane, etc.) on the signal line. In other words, the designer can set the range of the wire suppression region, the pin suppression region, the perforation pin suppression region, the via hole suppression region, or the copper foil plane suppression region in the suppression region range setting field 107. It should be noted that the suppression range item provided by the suppression area range setting field 107 can be adjusted according to the actual line layout architecture, and the present invention is not limited thereto.

The layout object check field 109 allows the designer to select the layout objects (such as surface adhesive component pins, perforation pins, via holes, and copper foil planes) included on the signal line, and accordingly, the operation processing unit 20 can A corresponding suppression region is formed around the layout object selected on the signal line in accordance with the setting of the suppression region range setting field 107. It should be noted that the options provided by the layout object check field 109 can be adjusted according to the actual circuit layout architecture, and the present invention is not limited thereto. The suppression area range setting field 107 and the layout object selection field 109 can be regarded as the setting interface of the layout parameter, but the embodiment is not limited thereto.

For example, if the designer wants to set a suppression region on the non-corresponding reference plane layer, as shown in FIG. 2B, the designer can select the layer of the corresponding signal layer 41 in the signal layer setting menu 103 provided by the parameter setting interface 101. Name, such as L1 or top. Subsequently, the selection of the restriction layer setting menu 105 should be subject to The name of the layer is restricted, that is, the layer name corresponding to the first restriction layer 43, for example, L3. Thereafter, the designer can enter the desired range size on the suppression area range setting field 107. At the same time, the layout object arranged on the first signal line 411 is checked on the layout object check field 109. The arithmetic processing unit 20 forms the first suppression area 47 on the first restriction layer 43 in accordance with the designer's setting, and excludes the line layout in the first suppression area 47. The coverage of the first suppression area 47 is defined by the setting of the suppression area range setting field 107.

For example, if a suppression region is to be disposed around the signal line, as shown in FIG. 2C, the designer can select the layer name of the corresponding signal layer 41 in the signal layer setting menu 103 provided by the parameter setting interface 101, for example, L1 or Top. Subsequently, the same layer selected as the signal layer setting menu 103, that is, the layer name of the signal layer 41 is selected in the restriction layer setting menu 105. Thereafter, the designer can enter the desired range size on the suppression area range setting field 107. At the same time, the layout object arranged on the first signal line 411 is checked on the layout object check field 109. The arithmetic processing unit 20 sets the suppression region 49 around the layout object disposed on the first signal line 411 and the first signal line 411 on the signal layer 41 according to the designer's setting, wherein the coverage of the suppression region 49 is determined by the suppression region range setting column. The setting of bit 107 is defined.

Accordingly, the designer can quickly and accurately establish a suppression region corresponding to the selected signal line according to the demand for signal quality in the line layout according to the electronic device 1, and suppress the influence on the impedance value of the signal line. Factor, which improves the efficiency and stability of the line layout and reduces product development time and cost.

It is to be noted that FIG. 2A to FIG. 2C are only a schematic diagram of a stack of corresponding six-layer printed circuit boards provided by the first embodiment of the present invention, and are not intended to be limited. The invention is defined. FIG. 3 is a schematic view of a portion of a stacking table provided by the first embodiment of the present invention, and the content thereof may be changed according to the actual circuit layout design, and thus is not intended to limit the present invention. Similarly, FIG. 4 is only a schematic diagram of a parameter setting interface provided by the first embodiment of the present invention, and the content thereof may be determined according to actual circuit layout design requirements, and thus is not intended to limit the present invention. The invention also does not limit the type, physical architecture and/or implementation of the electronic device 1, the display unit 10, the arithmetic processing unit 20, and the storage unit 30.

[Second embodiment]

According to the above embodiment, the present invention can be summarized as a circuit layout method for a printed circuit board, which is applicable to the electronic device described in the above embodiments. Referring to FIG. 5-1 and FIG. 5-2 and referring to FIG. 1 simultaneously, FIG. 5-1 and FIG. 5-2 are schematic diagrams showing a flow chart of a circuit layout method for a printed circuit board according to a second embodiment of the present invention.

First, in step S101, the arithmetic processing unit 20 provides a parameter setting interface as shown in FIG. 4 through the display unit 10 to receive the layout layer parameters input by the designer to the plurality of layout parameters. The layout layer parameters include the signal layer layer and the restriction layer layer that the designer wants to control according to the line design requirements. The plural layout parameters include the definition of the layout object laid out by the designer on the signal line configured by the line layout architecture and the range parameter of the corresponding suppression area.

Next, in step S103, the operation processing unit 20 determines the signal layer, the first confinement layer and the reference layer according to the layout layer parameter, wherein the first confinement layer is located between the signal layer and the reference layer and the signal layer has the first signal line. The first limiting layer and the reference layer may be, for example, a power layer, a ground layer, or a general line layout layer, but the embodiment is not limited thereto.

Then, in step S105, after the arithmetic processing unit 20 is calculated, a first suppression region corresponding to the first signal line is generated on the first restriction layer. more Specifically, the arithmetic processing unit 20 sets the range of the first suppression region in accordance with the layout parameters of the designer in the configuration. The range of the first suppression region covers the orthographic projection area of the first signal line at the first confinement layer. That is, the first suppression region is located directly below the first signal line.

Then, in step S107, the arithmetic processing unit 20 excludes the line layout in the first suppression region, so that the reference layer becomes the reference plane of the first signal line on the signal layer.

Then, in step S109, the arithmetic processing unit 20 sets a trace suppression region corresponding to the periphery of the first signal line on the signal layer according to the layout parameter, wherein the operation processing unit 20 sets the range of the trace suppression region according to the designer configuration layout parameter. At the same time, the operation processing unit 20 may further adjust the range of the first suppression region on the first restriction layer according to the range of the suppression range of the line suppression region. Subsequently, in step S111, the arithmetic processing unit 20 excludes the line layout in the trace suppression area.

Next, in step S113, the arithmetic processing unit 20 determines whether the pin suppression region is disposed around the surface adhesive component pin (SMD pin) disposed on the first signal line according to the designer's setting of the parameter setting interface. In other words, it is judged whether the surface adhesive component pin is provided on the first signal line and whether the designer selects the surface adhesive component pin in the layout object check field 109 on the parameter setting interface shown in FIG. When the arithmetic processing unit 20 determines that the pin suppression region is provided around the surface adhesion element pin on the first signal line, steps S115 and S117 are sequentially performed. If the arithmetic processing unit 20 determines that it is not necessary to provide a pin suppression region around the surface adhesive element pins on the first signal line, step S119 is performed. The arithmetic processing unit 20 sets the range of the pin suppression region in accordance with the designer configuration layout parameter in step S115. Then in step S117, the arithmetic processing unit 20 excludes the pin. The layout of the lines within the area. Further, the arithmetic processing unit 20 may further adjust the range of the first suppression region on the first restriction layer according to the range of the pin suppression region.

Then, in step S119, the arithmetic processing unit 20 determines whether or not the perforation pin suppression region is provided around the piercing pin (thru pin) disposed on the first signal line, according to the designer's setting in the parameter setting interface. In other words, it is determined whether a perforation pin is provided on the first signal line and whether the designer selects the option of the perforation pin in the layout object check field 109 on the parameter setting interface shown in FIG. If the arithmetic processing unit 20 determines that a perforation pin suppression region is provided around the perforation pin on the first signal line, step S121 and step S123 are sequentially performed. If the arithmetic processing unit 20 determines that it is not necessary to provide a punch pin suppression region around the punch pin on the first signal line, step S125 is performed.

In step S121, the arithmetic processing unit 20 sets the range of the punch pin suppression region in accordance with the designer layout parameter. Then, in step S123, the arithmetic processing unit 20 excludes the line layout in the punch pin suppression area. In addition, the arithmetic processing unit 20 may further adjust the range of the first suppression region on the first restriction layer according to the range of the perforation pin suppression region.

Thereafter, in step S125, the arithmetic processing unit 20 determines whether or not the via hole suppression region is provided around the via that is disposed on the first signal line, according to the designer's setting of the parameter setting interface. In other words, it is judged whether or not the guide hole is provided on the first signal line and whether the designer selects the guide hole in the layout object check field 109 on the parameter setting interface shown in FIG. When the arithmetic processing unit 20 determines that a via hole suppressing region is provided around the via hole on the first signal line, steps S127 and S129 are sequentially performed. If the operation processing unit 20 determines that it is not necessary to provide a guide hole around the via hole on the first signal line If the area is suppressed, step S131 is directly executed. In step S127, the arithmetic processing unit 20 sets the range of the via hole suppression region in accordance with the designer layout parameter. Then, in step S129, the arithmetic processing unit 20 excludes the line layout in the via suppressing region. Further, the arithmetic processing unit 20 may further adjust the range of the first suppression region on the first restriction layer according to the range of the via suppression region.

Next, in step S131, the arithmetic processing unit 20 determines whether or not the copper foil plane suppression region is provided around the copper foil layout of the first signal line, based on the designer's setting of the parameter setting interface. In other words, it is determined whether the copper foil plane is provided on the first signal line and whether the designer selects the option of the copper foil plane in the layout object check field 109 on the parameter setting interface shown in FIG. When the arithmetic processing unit 20 determines that a copper foil plane suppression region is provided around the copper foil plane on the first signal line, steps S133 and S135 are sequentially performed. If the arithmetic processing unit 20 determines that it is not necessary to provide a copper foil plane suppression region around the copper foil plane on the first signal line, step S137 is directly executed. In step S133, the arithmetic processing unit 20 sets the range of the copper foil plane suppression region in accordance with the designer layout parameter. Then, in step S135, the arithmetic processing unit 20 excludes the line layout in the copper foil plane suppression region. Further, the arithmetic processing unit 20 may adjust the range of the first suppression region on the first restriction layer in accordance with the range of the copper foil plane suppression region.

Finally, after completing the plurality of suppression regions required for establishing the line layout, the operation processing unit 20 completes the first suppression region corresponding to the first signal line, the pin suppression region corresponding to the surface adhesion component pin, and corresponds to the perforation. After the piercing pin suppression region of the pin, the via hole suppression region corresponding to the via hole, the wire suppression region corresponding to the first signal line, and the copper foil plane suppression region corresponding to the copper foil plane, the overall circuit is detected. Layout (step S137). According to this, the layout of the line can be quickly and accurately checked, and the quality of the line layout can be ensured, thereby avoiding omission or misjudgment by manual operation.

The detection method of the above line layout further includes the following steps. Please refer to FIG. 6. FIG. 6 is a schematic flow chart of a method for detecting a line layout of a printed circuit board according to a second embodiment of the present invention.

In this method, the operation processing unit 20 can comprehensively detect the line layout according to the above-described stack table, layout layer parameters, and layout parameters. The stack table may be, for example, the stack table shown in FIG. 3, including the number of layers of the board, the type of the layer, the attribute of the signal line, the reference layer corresponding to the signal line, the impedance value of the signal line, and the relevant line parameter of the signal line. Etc. and can be generated by external stacking software. The operation processing unit 20 determines the attribute of the first signal line according to the layout parameter of the first signal line in the alignment line layout and the parameter of the first signal line in the stack table (for example, line width, line spacing, line length, etc.). (Step S201), for example, it is determined that the first signal line is a characteristic impedance line or a differential impedance line. Then, the operation processing unit 20 determines whether the impedance value of the first signal line exceeds a predetermined impedance range according to the layout parameter, the attribute of the first signal line, and the impedance data of the corresponding first signal line in the stack table (step S203). The predetermined impedance range may be determined by the actual application of the product to the signal impedance value. The arithmetic processing unit 20 can generate impedance value error detection data when the impedance value of the first signal line exceeds the preset impedance range (step S205). On the other hand, if the arithmetic processing unit 20 determines that the impedance value of the first signal line is within the preset impedance range, step S207 is performed. The arithmetic processing unit 20 then stores the impedance value error detection data in the storage unit 30 and displays it through the display unit 10 for the designer to browse.

Next, in step S207, the operation processing unit 20 further detects the reference plane definition of the first signal line in the line layout according to the data of the stack table. Whether it meets the reference plane set by the stack table data. In other words, the arithmetic processing unit 20 detects whether the reference plane corresponding to the first signal line is correct. When the operation processing unit 20 defines an error in the reference plane of the first signal line, the step S209 is performed, that is, the reference plane detection data is generated. When the operation processing unit 20 determines that the reference plane definition of the first signal line is correct, step S211 is performed. The operation processing unit 20 provides the reference plane detection data to the designer for browsing through the display unit 10, and also stores the data in the storage unit 30 for recording.

Then, in step S211, the arithmetic processing unit 20 determines whether or not the line layout is set in the plurality of established suppression regions. When the arithmetic processing unit 20 has a line layout in the suppression area, the data is detected corresponding to the output suppression area (step S213). On the other hand, if the arithmetic processing unit 20 determines that no line layout is provided in the suppression area, step S215 is executed. Subsequently, the designer determines whether to correct the current line layout based on the reference plane detection data, the suppression area detection data, and/or the impedance value error detection data. When it is determined that the line layout is incorrect, the arithmetic processing unit 20 corrects the line layout with reference to the reference plane detection data, the suppression area detection data, and/or the impedance value error detection data according to the designer's setting (step S217). On the other hand, the arithmetic processing unit 20 determines that the line layout is not required to be corrected, and then performs step S219 to re-determine the signal layer, the first restriction layer and the reference layer, and the step of establishing a corresponding suppression region.

Incidentally, when the operation processing unit 20 detects that the line is changed, it also actively detects the changed line layout, and determines whether the changed line layout still conforms to the designer's setting, so as to suppress the line layout. Instant correction of the area, in order to maintain the quality of the line layout and improve design efficiency.

More specifically, this embodiment further provides a practical application mode of the line layout method. Referring to FIG. 7 to FIG. 11 simultaneously, FIG. 7 to FIG. 11 respectively illustrate application diagrams of a line layout method according to a second embodiment of the present invention. Further, FIG. 7 is a schematic diagram of a line layout method according to a second embodiment of the present invention applied to a first signal layer plane of a line layout. FIG. 8 is a schematic diagram of a line layout method according to a second embodiment of the present invention applied to a restriction layer plane of a line layout. FIG. 9 is a schematic diagram of a line layout method according to a second embodiment of the present invention applied to a second signal layer plane of a line layout. The limiting layer of Figure 8 is between the first signal layer of Figure 7 and the second signal layer of Figure 9. FIG. 10 is another schematic diagram of a line layout method according to a second embodiment of the present invention applied to a second signal layer plane of a line layout. FIG. 11 is still another schematic diagram of a line layout method according to a second embodiment of the present invention applied to a second signal layer plane of a line layout.

As shown in FIG. 7, the first signal layer 51 has a first signal line 511, and the first signal line 511 is provided with a via hole 513. The layout object adjacent to the first signal line 511 includes a copper foil plane 515 and a plurality of differently sized via holes. According to the above-mentioned circuit layout method, the designer can set the above-mentioned parameter setting interface to respectively provide the line suppression region 5111 and the via suppression region around the first signal line 511 and the via 513 on the first signal layer 51. 5131, the line layout in the trace suppression region 5111 and the via suppression region 5131 is excluded.

Specifically, the trace suppression region 5111 surrounds the first signal line 511, and the trace suppression region 5111 is extended outward by a predetermined distance D1 from the edge of the first signal line 511. The via hole suppression region 5131 surrounds the periphery of the via hole 513 on the first signal line 511, and extends outward from the outer edge of the via hole by a predetermined distance D2. According to this, the preset distances D1 and D2 respectively define the line suppression zone. The range of the domain 5111 and the via suppression region 5131. The range of the line suppression region 5111 and the via suppression region 5131 can be configured as described above in accordance with the setting of the field of the signal line and the via hole in the suppression region range setting field 107 in the parameter setting interface of the designer.

Meanwhile, in this circuit layout, the corresponding reference layer of the first signal line 511 of the first signal layer 51 is the second signal layer 55 shown in FIG. Accordingly, the first suppression region 531a is to be formed in the first confinement layer 53 shown in FIG. 8 such that the reference layer of the first signal line 511 is the second signal layer 55 of FIG. Therefore, as shown in FIG. 8, the range of the first suppression region 531a covers the orthographic projection area of the first signal line 511 of the first signal layer 51, wherein the via 533 in the first suppression region 531a on the second signal layer 55, That is, it corresponds to the position of the via 513 on the first signal layer 51. In more detail, the second signal lines 551a, 551b are set in accordance with the layout parameters of the first signal line 511 on the first signal layer 51.

Similarly, the reference layer of the second signal lines 551a, 551b on the second signal layer 55 shown in FIG. 9 is the first signal layer 51. Therefore, when the second signal lines 551a, 551b on the second signal layer 55 are controlled, the first suppression region 531b corresponding to the second signal lines 551a, 551b is also established in the first limiting layer 53 to make the second signal line The reference layer of 551a, 551b is the first signal layer 51 of FIG. As shown in FIG. 8, the range of the first suppression region 531b covers the orthographic projection regions of the second signal lines 551a, 551b of the second signal layer 55.

Further, as shown in FIG. 9, the second signal lines 551a, 551b have a plurality of layout objects, such as a via 553, a plurality of via pins 555, a surface mount component pin 557, and the like. With the line office method provided in this embodiment, when the designer selects the layout object included in the second signal line 551a, 551b and the corresponding suppression range on the parameter setting interface of FIG. 4, the second signal is generated. A wiring suppression region 5511, a via suppression region 5531, and a via pin suppression region 5551 are respectively disposed around the second signal lines 551a and 551b, the via 553, the plurality of via pins 555, and the surface adhesive component pins 557 on the layer 55. And a pin suppression area 5571.

The range of the line suppression region 5511 is defined by a distance D3 extending outward from the edge of the second signal lines 551a, 551b. The range of the via hole suppression region 5531 is defined by a distance D4 that extends outward from the outer edge of the via hole 553. The range of perforation pin restraining regions 5551 is defined by the distance D5 that extends outwardly from the outer edge of the perforation pin 555. The range of the pin suppression region 5571 is defined by the distance D6 that extends outward from the edge of the surface adhesive component pin 557.

It is worth mentioning that the trace suppression region 5511, the via suppression region 5531, the via pin suppression region 5551, and the pin suppression region 5571 are selected by the designer in the layout object check field 109 of the parameter setting interface of FIG. The surface is attached to the component pin, the through hole and the via hole, and the suppression range (ie, the distance D3) of the corresponding second signal line 551a, 551b and the suppression range of the corresponding via 553 are input in the suppression region range setting field 107. (ie, distance D4), the suppression range of the corresponding perforation pin 555 (ie, the distance D5) and the corresponding range of the surface adhesion element pin 557 (ie, the distance D6) are formed.

In addition, when the layout of the line is changed, that is, when the designer changes the size of the via hole 553, the punch pin 555, and/or the corresponding suppression range provided on the second signal lines 551a, 551b on the second signal layer 55, The corresponding suppression range on the second signal layer 55 is also adjusted accordingly. As shown in FIG. 10, after the size of the via hole 553a and the via pin 555a on the second signal line 551a, 551b on the second signal layer 55a are adjusted, the corresponding via hole suppression region 5531, the via pin suppression region 5551, and The range of the pin suppression area 5571 is also adjusted.

Further, assuming that a copper foil plane is provided on the second signal line 551a of the second signal layer 55, a copper foil plane suppression region is provided around the plane of the copper foil. For example, as shown in FIG. 11, the second signal layer 55b is provided with a seven-corner copper foil plane 559 on the second signal line 551a, so that a copper foil plane suppression region 5591 is provided around the copper foil plane 559. More specifically, the copper foil plane suppression region 5591 is a line layout extending outward from the edge of the copper foil plane 559 by a predetermined distance D7 while being excluded from the copper foil plane suppression region 5591. The distance D7 can be set by the designer to select the copper foil plane in the layout object check field 109 of the parameter setting interface of FIG. 4, and input the range of the corresponding copper foil plane in the suppression area range setting field 107.

Incidentally, when the designer modifies the line layout of the second signal layer 55, 55a or 55b, the coverage of the first suppression region 531b corresponding to the second signal line 551a on the first restriction layer 53 of FIG. The adjustment is then made such that the first suppression region 531b covers the orthographic projection area of the second signal line 551a.

Accordingly, after the description of the above embodiments, those skilled in the art should be able to infer the establishment of the suppression region in the line layout and the range of the adjustment suppression region, and thus will not be described herein. It is to be noted that FIG. 5-1, FIG. 5-2, and FIG. 6 are only schematic flowcharts of the circuit layout method and the corresponding detection method provided by the embodiments of the present invention, and are not intended to limit the present invention. Similarly, FIG. 7 to FIG. 11 are only for explaining an application manner of the circuit layout method according to the second embodiment of the present invention, and the present invention is not limited thereto.

It should be noted that, in practice, the implementation of the line layout method provided by this embodiment may be, for example, a line layout design software commonly used by printed circuit board designers, such as the Allegro Layout Tool. Further, you can break into the installation source in the design software of Allegro Layout Tool. (installation source), and set shortcuts (shortcuts). According to this, the designer can start the circuit layout design by using the shortcut key of the operation setting by the electronic device installing the circuit layout design software, and simultaneously bring up the window of the parameter setting interface as shown in FIG. 4 to perform the line. The layout is designed, but this embodiment is not limited thereto.

In addition, the present invention can also utilize a computer readable recording medium to store a computer program of the aforementioned line layout method to perform the aforementioned steps. The computer readable medium can be a floppy disk, a hard disk, a compact disk, a flash drive, a magnetic tape, a database accessible by the network, or a storage medium that can be easily thought of by the person skilled in the art.

In summary, the line layout method provided by the embodiment of the present invention can actively generate a plurality of signal lines corresponding to the impedance control in the line layout according to the layout layer parameters and the layout parameters set by the designer. The suppression area, where the line layout designer can adjust the range of the configuration suppression area at any time so that the signal lines in the line layout meet the signal quality requirements of the product. Accordingly, the line layout designer can shorten the design time of the line layout by using the line layout method, improve the design efficiency of the overall line layout, and reduce product development time and manufacturing cost.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

1‧‧‧Electronic device

10‧‧‧Display unit

20‧‧‧Operation Processing Unit

30‧‧‧ storage unit

41‧‧‧Signal layer

411‧‧‧first signal line

43, 53‧‧‧ first restricted layer

45‧‧‧ reference layer

47‧‧‧First suppression zone

49‧‧‧Suppression area

101‧‧‧ parameter setting interface

103‧‧‧Signal layer setting menu

105‧‧‧Restriction layer setting menu

107‧‧‧Suppression area setting field

109‧‧‧ Layout object check field

51‧‧‧First signal layer

55, 55a, 55b‧‧‧ second signal layer

511‧‧‧first signal line

5111‧‧‧Wiring suppression area

513, 533, 553, 553a‧‧ ‧ guide holes

5131‧‧‧Guide hole suppression zone

515, 559‧‧‧ copper foil plane

531a‧‧‧First suppression zone

531b‧‧‧Second suppression zone

551a, 551b‧‧‧ second signal line

5511, 5511a‧‧‧Wiring suppression area

5531, 5531a‧‧‧Guide hole suppression area

555, 555a‧‧ ‧ piercing pin

5551, 5551a‧‧‧ Piercing pin suppression zone

557‧‧‧Surface adhesive component pins

5571‧‧‧ Surface adhesion component pin suppression area

5591‧‧‧copper foil plane suppression area

D1~D7‧‧‧Distance

S101~S137‧‧‧ Process steps

S201~S219‧‧‧ Process steps

1 is a functional block diagram of an electronic device according to a first embodiment of the present invention.

2A-2C are schematic diagrams showing the stacking of printed circuit boards according to the first embodiment of the present invention.

3 is a stack diagram of a printed circuit board according to a first embodiment of the present invention; Part of the schematic.

4 is a schematic diagram of a parameter setting interface of an electronic device according to a first embodiment of the present invention.

5-1 and FIG. 5-2 are schematic flowcharts of a circuit layout method of a printed circuit board according to a second embodiment of the present invention.

FIG. 6 is a schematic flow chart of a method for detecting a line layout of a printed circuit board according to a second embodiment of the present invention.

FIG. 7 is a schematic plan view showing a first signal layer applied to a line layout by a line layout method according to a second embodiment of the present invention.

FIG. 8 is a schematic plan view showing a restriction layer of a line layout method according to a second embodiment of the present invention.

9 is a schematic plan view showing a second signal layer applied to a line layout by a line layout method according to a second embodiment of the present invention.

FIG. 10 is another schematic diagram of a line layout method according to a second embodiment of the present invention applied to a second signal layer plane of a line layout.

FIG. 11 is still another schematic diagram of a signal layout plane applied to a line layout according to a second embodiment of the present invention.

S101~S137‧‧‧ Process steps

Claims (22)

A circuit layout method for a printed circuit board is applicable to an electronic device, the method comprising the steps of: providing a parameter setting interface to receive a layout layer parameter and a plurality of layout parameters; determining a signal layer according to the layout layer parameter a limiting layer and a reference layer, wherein the first limiting layer is located between the signal layer and the reference layer and the signal layer has a first signal line; and the first limiting layer generates a corresponding one of the first signal lines a first suppression region; and a line layout excluded from the first suppression region. The circuit layout method of claim 1, wherein the step of generating the suppression region corresponding to the first signal line in the first restriction layer comprises: setting a range of the first suppression region according to the layout parameters The first suppression region covers the orthographic projection area of the first signal line of the first confinement layer. The circuit layout method of claim 1, further comprising: determining a second limiting layer according to the layout layer parameter layout parameter, the second limiting layer being located between the signal layer and the reference layer; The second limiting layer generates a second suppression region corresponding to the first signal line; excluding the line layout in the second suppression region, so that the reference layer becomes the reference plane of the first signal line. For example, the line layout method described in claim 1 of the patent scope is further included. Included: a pin suppression region is disposed around a surface adhesive component pin on the first signal line; a range of the pin suppression region is determined according to the layout parameter; and a line layout in the pin suppression region is excluded. The circuit layout method of claim 4, further comprising: adjusting a range of the first suppression region on the first restriction layer according to a range of the pin suppression region. The circuit layout method of claim 1, further comprising: providing a perforation pin suppression area around a perforation pin on the first signal line; determining the perforation pin suppression area according to the layout parameter Range; and exclude the layout of the line within the perforated pin suppression area. The method according to claim 6, further comprising: adjusting a range of the first suppression region on the first confinement layer according to a range of the perforation pin suppression region. The circuit layout method of claim 1, further comprising: providing a via hole suppression region around a via hole on the first signal line; determining a range of the via hole suppression region according to the layout parameter; The layout of the lines in the via suppression region is excluded. The circuit layout method of claim 8, further comprising: adjusting a range of the first suppression region on the first restriction layer according to a range of the via suppression region. The circuit layout method of claim 1, further comprising: providing a copper foil plane suppression region around a copper foil plane on the first signal line; determining the copper foil plane suppression region according to the layout parameter Range; and exclude the layout of the line within the copper foil planar suppression region. The method of line layout according to claim 10, further comprising: adjusting a range of the first suppression region on the first confinement layer according to a range of the copper foil plane suppression region. The circuit layout method of claim 1, further comprising: setting a trace suppression region around the first signal line; determining a range of the trace suppression region according to the layout parameter; and excluding the trace Suppress the layout of the lines within the area. The circuit layout method of claim 12, further comprising: adjusting a range of the first suppression region on the first restriction layer according to a range of the trace suppression region. For example, the line layout method described in claim 1 of the patent scope further includes: And detecting an impedance of the first signal line according to a stack table; and outputting an impedance value error detecting data if the impedance of the first signal line exceeds a predetermined impedance range. The method for line layout according to claim 1, further comprising: generating a plurality of suppression regions according to the layout parameter; detecting whether line layouts in the suppression regions are excluded; and setting a line layout in the suppression regions , output a suppression area detection data. The circuit layout method of claim 15, wherein the suppression regions include the first suppression region corresponding to the first signal line, a pin suppression region corresponding to a surface adhesion component pin, corresponding to a perforation pin suppression region of a perforated pin, a via hole suppression region corresponding to a via hole, a trace suppression region corresponding to the first signal line, and a copper foil plane suppression corresponding to a copper foil plane region. The circuit layout method of claim 1, further comprising: setting a second signal line corresponding to the first signal line in the reference layer according to the layout parameter. An electronic device includes: a display unit for displaying a parameter setting interface; a storage unit for storing a plurality of layout layer parameters and a plurality of layout parameters; and an operation processing unit for performing the following steps: providing the parameter Setting an interface to receive the layout layer parameters and the layout parameters; Determining a signal layer, a first confinement layer and a reference layer according to the layout layer parameter, wherein the first confinement layer is located between the signal layer and the reference layer and the signal layer has a first signal line; A confinement layer produces a first suppression region corresponding to the first signal line; and a line layout excluded from the suppression region. The electronic device of claim 18, wherein the operation processing unit sets a range of the first suppression region according to the layout parameters, wherein the first suppression region is located directly below the first signal line, and the The range of the first suppression region covers the orthographic projection area of the first signal line at the first confinement layer. The electronic device of claim 18, wherein the arithmetic processing unit sets a pin suppression region, a perforation pin suppression region, a via suppression region, and a copper foil plane suppression region according to the layout parameters. And a trace suppression region, wherein the pin suppression region is located around a surface adhesion component pin on the first signal line, the perforation pin suppression region is located around a perforation pin on the first signal line, The via hole suppression region is located around a via hole on the first signal line, the copper foil plane suppression region is located around a copper foil plane on the first signal line, and the trace suppression region is located on the first signal line Around the line. The electronic device according to claim 20, wherein the arithmetic processing unit determines the pin suppression region, the perforation pin suppression region, the via suppression region, and the copper foil plane suppression region according to the layout parameters. And a range of the trace suppression region, and a line layout of the pin suppression region, the perforation pin suppression region, the via suppression region, the copper foil plane suppression region, and the trace suppression region are excluded. A computer readable recording medium, wherein the computer readable recording medium records a set of computer executable programs, and when the computer readable recording medium is read by a processor, the processor executes the computer executable program To carry out the steps as described in item 1 of the scope of the patent application.