TW201342526A - Piercing conductor structure and its preparation method - Google Patents

Abstract

The invention relates to a through-conducting conductor structure and a manufacturing method thereof, wherein after forming an interlayer dielectric layer, a via hole is formed, and the via hole penetrates the interlayer dielectric layer, and then a dielectric is formed in the via hole. a liner that extends over the interlayer dielectric layer. A conductive material is then filled into the via holes, and a chemical mechanical polishing process is performed to planarize the conductive material, and a dielectric liner over the interlayer dielectric layer is used as a stop layer for the chemical mechanical polishing process.

Description

Piercing conductor structure and its preparation method

The invention relates to a method for manufacturing a through silicon via (TSV) and a structure thereof.

In the semiconductor technology, the TSV structure is used to electrically connect the stacked crystal grains and the layer components between the crystal grains, thereby significantly reducing the connection distance of the components on the wafer, thereby effectively increasing the overall operation speed. Therefore, it is particularly suitable for use in components requiring wafer bonding processes such as better performance and higher density, such as in Wafer Level Package (WLP) structures such as MEMS, optoelectronics, and electronic components.

In the current TSV practice, a via hole is drilled on the front side of the wafer by etching or laser, and a conductive material such as polysilicon, copper, tungsten or the like is filled into the via holes to form a conductive layer. Channel (that is, an interconnect structure that connects internal and external). Finally, the wafer or die back is thinned to expose the vias. However, the via holes are formed on the front surface of the wafer, and after the conductive material is filled into the via holes, the excess conductive layer on the interlayer dielectric layer is usually removed by a chemical-mechanical polishing (CMP) process. The material, this step is prone to the loss of the interlayer dielectric layer, which in turn makes it difficult to integrate the TSV with other components (such as MOS) processes.

Therefore, there is still a need for a novel and simple method of manufacturing a TSV structure.

It is an object of the present invention to provide a method of fabricating a TSV structure and a TSV structure which have good yield and low cost.

In accordance with an embodiment of the present invention, a method of fabricating a TSV structure is provided that includes the following steps. First, a substrate is provided. The substrate includes a device region in which a device is disposed and a through-conducting region. Then, an interlayer dielectric layer covering device region and a through-hole via region are formed. Then, a via hole is formed in the substrate passing through the via region, and the via hole penetrates the interlayer dielectric layer. A dielectric liner is then formed in the via and the dielectric liner extends over the interlayer dielectric layer. A first conductive material is filled into the via holes. A chemical mechanical polishing process is performed on the substrate to planarize the first conductive material and a dielectric liner over the interlayer dielectric layer as a stop layer for the chemical mechanical polishing process.

In accordance with another embodiment of the present invention, a TSV structure is provided that includes a substrate, a device, an interlevel dielectric layer, a via, a conductive material, and a dielectric liner. The substrate includes a device region and a through-conductor region. The device is located on the substrate of the device area. The interlayer dielectric layer covers the substrate and the device and is planarized. The via holes penetrate the interlayer dielectric layer and are located in the substrate passing through the via region. The via hole includes a sidewall. The conductive material is disposed in the via hole. A dielectric liner is disposed between the conductive material and the sidewall and extends over the interlayer dielectric layer.

According to a specific embodiment of the present invention, prior to the fabrication of the contact plug of the device, the TSV is fabricated, and the dielectric liner of the TSV can be used as the overcoat layer formed on the interlayer dielectric layer in the prior art. This eliminates the need to form a re-covering step, thus reducing costs. Moreover, the dielectric liner can be used as a stop layer for the planarization process (for example, CMP process) for fabricating a TSV, and it is not necessary to form a dedicated stop layer. Furthermore, the interlayer dielectric layer is not lost due to the TSV CMP process. Furthermore, after the TSV is fabricated and the contact plug is fabricated, the contact plug does not suffer from the CMP process used in the fabrication of the TSV, and the contact plug can be prevented from being lowered by the polishing of the TSV CMP process. Thus, the use of the method of the present invention results in reduced cost and good yields in the fabrication of TSV structures.

Figures 1 through 2 show a method of fabricating a TSV structure. A device 4 is formed on a substrate 2. An interlevel dielectric layer 6 is then formed. The interlayer dielectric layer 6 is planarized. A re-cap layer 8 is formed on the interlayer dielectric layer 6 in consideration of the problem of interlayer dielectric loss in the subsequent process. The fabrication of the contact plug 10 is then performed. Next, a stop layer 12 (for example, a tantalum nitride layer) is formed. Then, via holes of the TSV are formed, and the dielectric liner 14, the barrier layer 16, and the conductive material 18 are sequentially filled. Then, a chemical-mechanical polishing (CMP) process is performed, as shown in FIG. 2, to re-cap layer 8 and excess barrier layer 16 and conductive material above contact plug 10. 18 removed. Then, the back thinning process is performed to complete the fabrication of the TSV structure. In the CMP process, the stop layer 12 provides a signal to stop the grinding preparation. Since the stop layer 12 above the contact plug 10 must be removed, the CMP process is stopped at the re-cover layer 8 and the re-cover layer 8 is lost a few thicknesses, as shown in Figure 2, the remaining over-cover layer 8a And the loss of thickness h; so that in designing the overall interlayer dielectric layer (which may include the interlayer dielectric layer and the heavy cover layer), the thickness of the overlay layer that may be removed must be counted, and there is a process Time and waste of materials.

Please refer to pictures 3 to 6. 3 is a flow chart illustrating a method of fabricating a TSV structure in accordance with an embodiment of the present invention, and FIGS. 4 through 6 are schematic cross-sectional views illustrating a method of fabricating a TSV structure in accordance with an embodiment of the present invention. It should be noted that the dimensions of the various figures herein are not to be construed as a true First, referring to FIG. 3 and FIG. 4, step 101 is performed to provide a substrate 20. Substrate 20 can be monocrystalline silicon, gallium arsenide (GaAs), or other materials well known in the art. The substrate thickness is approximately 600 to 1000 micrometers, but is not limited thereto. The substrate 20 includes a device region 201 and a through-via via region 202. The device area 201 is provided with a device 22 such as a metal-oxide-semiconductor MOS transistor or the like. Then, step 102 is performed to form an interlayer dielectric layer 24 on the substrate 20 to cover the device region 201 and the through-via via region 202. The interlayer dielectric layer 24 may be a single layer or a multilayer structure, and the material may be, for example, SiO ₂ , SiC, Si ₃ N ₄ , or a low dielectric constant material, and the deposition method may utilize CVD or SOG (spin-on-glass). Wait. The lowermost layer is preferably an oxide layer. The interlayer dielectric layer 24 can be further planarized, for example, using a CMP process. The final thickness can be determined according to the needs.

Then, referring to FIG. 3 and FIG. 5, step 103 is performed to provide a via hole 26 in the via region 202, which can be achieved by, for example, a lithography and etching process, and a patterned photoresist can also be used. The layer may be free of a hard mask (such as a tantalum nitride patterned layer). The size of the vias 26 can be, for example, about 6 microns (aperture) x about 40 microns (depth) to about 25 microns (aperture) x about 150 microns (depth), but is not limited thereto. Then, in step 104, a dielectric liner 28 is formed such that the dielectric liner 28 covers the sidewalls of the vias 26 and extends onto the interlayer dielectric layer 24. In the present invention, the dielectric liner 28 will be used as an interlayer dielectric layer in the integrated circuit together with the interlayer dielectric layer 24 in the completed TSV structure. Dielectric liner 28 can be fabricated using, for example, a CVD process. The material is considered to be a dielectric liner of the TSV structure, that is, it needs to have an insulating property to make the TSV structure conductive material and the substrate have good insulation; more preferably, it has moisture barrier property. To prevent moisture from invading the TSV structure. In the case where the dielectric liner 28 can serve as a dielectric liner for the TSV structure, it would also be suitable for use as an interlayer dielectric layer. Thus, for example, cerium oxide, cerium nitride, cerium oxynitride or other suitable materials may be suitable. It can be a single layer or a multilayer structure. Due to the step coverage effect of the CVD process, the thickness of the dielectric liner 28 formed varies slightly depending on the material, process, and location of the formation, and may be determined as needed. For example, a CVD process is performed at 300 ° C to 400 ° C using tetraethoxysilane (TEOS) as a source of lanthanum, and the resulting dielectric liner 28 is a ruthenium oxide layer on the sidewall of the via 26 (substantially The thickness in the vertical direction may be, for example, about 1000 angstroms to about 2000 angstroms, and may be, for example, 3,000 angstroms or more above the interlayer dielectric layer 24 (substantially horizontal). Considering the protective effect of the dielectric liner on the TSV structure and the desire to fabricate the interlayer dielectric layer quickly, the dielectric liner 28 has a relatively dense texture in the final structure, and immediately below the interlayer. The texture of the dielectric layer 24 is relatively loose. In other words, the density of the dielectric liner can be greater than the density of the interlayer dielectric layer.

Then, in step 105, the conductive material 32 is filled in the via hole 26. A barrier layer or seed layer 30 may be formed on the dielectric liner 28 in the vias 26 prior to filling the conductive material 32. The barrier layer or seed layer 30 can be made using conventional methods. For the copper conductive material, the barrier layer may include, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or a combination thereof. Conductive material 32 is then filled into vias 26, which may be, for example, copper, tungsten, aluminum, or other suitable electrically conductive material. It can be produced by, for example, electroplating, sputtering or chemical vapor deposition (CVD), electro-less plating/electro-less grabbing.

Then, referring to FIG. 3 and FIG. 6, step 106 is performed to perform a planarization process to polish the conductive material 32. For example, a CMP process is performed with the dielectric liner 28 as a stop layer, that is, the conductive material 32 and the barrier layer or seed layer 30 over the interlayer dielectric layer 24 are removed by grinding to expose the interlayer dielectric layer 24. Upper dielectric liner 28. The dielectric liner 28 may also be abraded to a certain thickness, but since there is still a remaining thickness to protect the interlayer dielectric layer 24 underneath, the interlayer dielectric layer 24 is not due to the planarization process in the TSV fabrication process. Injury or loss. The remaining thickness of the dielectric liner 28 can be used as a re-cover layer of the interlayer dielectric layer 24, with the height of the dielectric liner 28 being the height of the re-cover layer. After the planarization process, the dielectric liner 28 on the interlayer dielectric layer 24 presents a planarization plane along with the conductive material 32.

After step 106, the fabrication of the contact plug of device 22 can be further performed. The contact plug can be fabricated by a conventional technique, for example, forming a hard mask layer covering the dielectric liner 28, and etching the hard mask layer by a photoresist layer patterned by a lithography process to form at least An open pattern. The dielectric liner 28 and the interlayer dielectric layer 24 are etched through the opening to form at least one contact hole through the dielectric liner 28 and the interlayer dielectric layer 24 to expose the substrate 20 and/or the device 22 (eg, MOS transistor) Gate electrode and source/drain). Remove the hard mask layer. The contact hole is then filled with a conductive material, which may include, for example, copper, tungsten, aluminum, etc., which may be the same or different than the conductive material of the TSV. Further, a planarization process, such as a CMP process, can be performed as needed to complete the fabrication of the contact plugs 34. The contact plug 34 penetrates the dielectric liner 28 and the interlayer dielectric layer 24 to contact the device 22 and is capable of contacting the first metal layer of the metal interconnect during subsequent processing.

Then, see Figure 7. Figure 7 omits the components or devices produced by the wafer front-end process, such as multilayer metal interconnects and protective layers. As shown in Fig. 7, the back surface of the substrate 20 (i.e., the side on which the interlayer dielectric layer is not deposited) is further subjected to a thinning process to expose the conductive material 32 of the TSV to complete the fabrication of the TSV structure. The thinning process can be achieved by performing a grinding step, such as a CMP process, on the back side of the substrate 20.

Figure 8 illustrates a TSV structure in accordance with another embodiment of the present invention. It further includes a barrier layer 36 and a seed layer 38. The barrier layer 36 is formed between the conductive material 32 and the dielectric liner 28, and the seed layer 38 is formed between the barrier layer 36 and the conductive material 32.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

2, 20. . . Base

4, 22. . . Device

6, 24. . . Interlayer dielectric layer

8. . . Overlay

8a. . . Remaining cover

10, 34. . . Contact plug

12. . . Stop layer

14, 28. . . Dielectric liner

16, 36. . . Barrier layer

18, 32. . . Conductive material

26. . . Via

30. . . Barrier layer or seed layer

38. . . Seed layer

201. . . Device area

202. . . Piercing the body area

101, 102, 103, 104, 105, 106. . . step

Figures 1 through 2 are schematic cross-sectional views illustrating a method of fabricating a TSV structure.

3 is a flow chart illustrating a method of fabricating a TSV structure in accordance with an embodiment of the present invention.

4 through 6 are schematic cross-sectional views illustrating a method of fabricating a TSV structure in accordance with an embodiment of the present invention.

Figure 7 is a cross-sectional view showing the structure of a TSV in accordance with an embodiment of the present invention.

Figure 8 is a cross-sectional view showing the structure of a TSV in accordance with another embodiment of the present invention.

20. . . Base

twenty two. . . Device

twenty four. . . Interlayer dielectric layer

26. . . Via

28. . . Dielectric liner

30. . . Barrier layer or seed layer

32. . . Conductive material

201. . . Device area

202. . . Piercing the body area

Claims (17)

A method of fabricating a through-conductor via structure includes: providing a substrate comprising a device region having a device and a via conductor region; forming an interlayer dielectric layer overlying the device region and the through-via via region Forming a via hole in the substrate passing through the via region and penetrating the via hole through the interlayer dielectric layer; forming a dielectric liner in the via hole and extending the dielectric liner Up to the interlayer dielectric layer; filling a first conductive material into the via hole; and performing a chemical mechanical polishing process on the substrate to planarize the first conductive material and to be located in the interlayer dielectric layer The dielectric liner above is used as a stop layer for the CMP process. The method of fabricating a through-conductor via structure according to claim 1, further comprising: forming a barrier layer between the first conductive material and the dielectric liner in the via hole. The method of fabricating a through-conductor via structure according to claim 1, further comprising: forming a seed layer between the first conductive material and the dielectric liner in the via hole. The method of fabricating a through-conductor via structure according to claim 2, further comprising: forming a seed layer between the first conductive material and the barrier layer in the via hole. The method of fabricating a through-conductor via structure as claimed in claim 1 further comprising: penetrating the dielectric liner and the interlayer dielectric layer to form at least one contact plug to contact the device. The method of fabricating a through-conductor via structure according to claim 5, wherein the forming the at least one contact plug is formed by penetrating the dielectric liner and the interlayer dielectric layer by a lithography and etching process. A contact hole is formed by filling a second conductive material in the at least one contact hole and planarizing. A method of fabricating a through-conductor via structure as claimed in claim 5, wherein the step of forming the at least one contact plug is performed after planarizing the first conductive material. The method of fabricating a through-conductor via structure according to claim 1, wherein the via hole is formed in the substrate of the through-via via region by a lithography and etching process. A method of fabricating a through-conductor via structure as claimed in claim 1 wherein the dielectric liner has a density greater than a density of the interlayer dielectric layer. A through-conducting via structure includes: a substrate including a device region and a through-via via region; a device on the substrate of the device region; and an interlayer dielectric layer covering the substrate and The device is planarized; a via hole penetrating the interlayer dielectric layer and the substrate passing through the via region, the via hole includes a sidewall; and a conductive material disposed in the via hole And a dielectric liner disposed between the conductive material and the sidewall and extending to the interlayer dielectric layer. The through-conductor via structure of claim 10, further comprising a barrier layer between the conductive material and the dielectric liner in the via. The through-conductor via structure of claim 10, further comprising a seed layer between the conductive material and the dielectric liner in the via. The through-conductor via structure according to claim 11, further comprising a seed layer between the conductive material in the via hole and the barrier layer. The through-conductor via structure of claim 10, further comprising at least one contact plug penetrating the dielectric liner and the interlayer dielectric layer to contact the device. The through-conductor structure as claimed in claim 10, wherein the dielectric liner has a property of preventing moisture from blocking. The through-conductor via structure of claim 10, wherein the dielectric liner has a density greater than a density of the interlayer dielectric layer. The through-conductor via structure of claim 10, wherein the dielectric liner on the interlayer dielectric layer presents a planarization plane with the electrically conductive material.