TW201333947A - Magnetoresistive random access memories - Google Patents

Abstract

A magnetoresistive random access memory (MRAM) device and a method of manufacture are provided. The MRAM device comprises a magnetic pinned layer, a compound GMR structure acting as a free layer, and a non-magnetic barrier layer separating the pinned and GMR layers. The barrier layer is provided to reduce the magnetic coupling of the free layer and GMR structure, as well as provide a resistive state (high or low) for retaining binary data (0 or 1) in the device. The GMR structure provides physical electrode connectivity for set/clear memory functionality which is separated from the physical electrode connectivity for the read functionality for the memory device.

Description

Magnetoresistive random access memory

The present invention relates to a memory, and more particularly to a magnetoresistive random access memory (MRAM).

Magnetoresistive Random Access Memory (MRAM) is a non-volatile computer memory type that can store digital information (binary 0 or 1) bits. Magnetoresistive random access memory (MRAM) digital data is not stored as a charge in a conventional random access memory (RAM) component, but in a bit state (0 or 1) by a resistive state in a magnetic storage element (high Resistor or low resistance) storage, no need to fix power to maintain its state. For example, the magnetic storage element may include a fixed magnetic layer, a free (variable) magnetic layer and a non-magnetic conductive resistance barrier layer, wherein the non-magnetic conductive resistance barrier layer is interposed between the fixed magnetic layer and the free magnetic layer. The relative arrangement of the magnetic fields of the fixed layer and the free layer determines the resistance state (high resistance or low resistance) of the barrier layer interposed between the fixed magnetic layer and the free magnetic layer.

The change in the resistance state of the magnetoresistive random access memory (MRAM) device can be controlled by changing the magnetic state of the free layer to conform to the magnetic state of the fixed magnetic layer or to the magnetic state opposite to the fixed magnetic layer. If the magnetic direction of the free layer conforms to the magnetic direction of the fixed layer, a low resistance state can be created in the barrier layer, and the stored memory bit information is equal to a binary value of, for example, 1. If the magnetic free layer and the magnetic fixed layer have opposite magnetic directions (the magnetic direction of the free layer is opposite to the magnetic direction of the fixed layer), a high resistance state can be created in the barrier layer, and the stored memory bit information is stored. Equal to A binary value such as 0. Generally, a magnetoresistive random access memory (MRAM) device is formed by providing a pinned layer, a barrier layer, and a free layer between two electrodes in a semiconductor device.

Magnetoresistive random access memory (MRAM) components can be manipulated to set and retrieve data such as read, write 1 (set value is 1) and write 0 (clear set value to 0). A write operation, also known as a stylized operation, applies an electrical pulse to the electrodes to cause current to flow between the fixed and free layers of the element. Depending on the direction of current flow, the magnetic direction of the free layer will change to conform to or opposite the magnetic direction of the fixed layer. The read operation is also performed across the electrodes by measuring the resistance between the fixed layer and the free layer of the magnetoresistive random access memory (MRAM) device.

One embodiment of the present invention provides a magnetoresistive random access memory (MRAM). The magnetoresistive random access memory (MRAM) includes a fixed magnetic layer, a barrier layer adjacent to the fixed magnetic layer, and a giant magnetoresistance (GMR) structure adjacent to the barrier layer. The giant magnetoresistance (GMR) structure includes a first magnetic layer, a second magnetic layer and a conductive layer. The conductive layer is interposed between the first magnetic layer and the second magnetic layer. The size of the first magnetic layer is different from the size of the second magnetic layer.

Another embodiment of the present invention provides a magnetoresistive random access memory (MRAM). The magnetoresistive random access memory (MRAM) includes a fixed layer, a barrier layer adjacent to the fixed layer, and a giant magnetoresistance (GMR) junction. Constructed adjacent to the barrier layer. The giant magnetoresistance (GMR) structure includes a first magnetic layer, a second magnetic layer and a conductive layer, and the conductive layer is interposed between the first magnetic layer and the second magnetic layer. The magnetoresistive random access memory (MRAM) further includes a first write electrode coupled to the first magnetic layer and a second write electrode coupled to the second Magnetic layer.

Another embodiment of the present invention provides a magnetoresistive random access memory (MRAM). The magnetoresistive random access memory (MRAM) includes a fixed layer, a barrier layer adjacent to the fixed layer, a first magnetic layer, adjacent to the barrier layer, and a conductive layer adjacent to the first magnetic layer. A second magnetic layer adjacent to the conductive layer, a first electrode directly coupled to the first magnetic layer, and a second electrode directly coupled to the second magnetic layer.

The above described objects, features and advantages of the present invention will become more apparent and understood.

According to an embodiment, Figures 1 through 6B illustrate different intermediate stages of a memory device process. First, referring to FIG. 1, a portion of a structure of a wafer 100 having a dielectric layer 110 including a first electrode 124 is shown, in accordance with an embodiment. It should be noted that the first electrode 124 can be electrically coupled to an electronic circuit (not shown) and/or an external connection (not shown) formed on a lower substrate (not shown). For example, in the embodiment illustrated in FIG. 1, the first electrode 124 can be electrically coupled to a source/drain region of a transistor formed on a lower substrate by a contact window (not shown). according to In this manner, the transistor can be used to control the reading of the state of the subsequently formed memory component.

In an embodiment, the circuit can further include an electronic component formed on the substrate, the substrate having one or more dielectric layers covering the electronic component. A metal layer can be formed between the dielectric layers to transfer electronic signals between the electronic components. Electronic components can also be formed in one or more dielectric layers. In general, an interlayer dielectric layer (ILD), an inter-metal dielectric layer (IMD), and a bonded metallization layer are used to internally connect each electronic circuit formed on a lower substrate and provide an external electrical connection.

The dielectric layer 110 may be formed of, for example, a low-k dielectric material such as phosphorous-glass (PSG), borophosphorus glass (BPSG), fluorocarbon glass (FSG), SiOxCy, spin-on glass, spin-on polymer, carbon An anthraquinone material, a compound thereof, a composition thereof, or a combination or analog thereof. It can be formed by any suitable method, such as spin coating, chemical vapor deposition (CVD), and plasma assisted chemical vapor deposition (PECVD). It is noted that the dielectric layer 110 can include a plurality of dielectric layers.

The first electrode 124 can be formed in the dielectric layer 110 by any suitable process including a damascene process. Generally, the damascene process includes depositing a layer (e.g., dielectric layer 110) on a substrate and forming a mask (not shown) on the layer. The mask can be patterned using, for example, photolithography and etching techniques, including depositing a photoresist material, forming a mask, exposing and developing to expose portions of the dielectric layer 110 that will be removed. The residual photoresist material is used to protect the underlying material during subsequent processing steps such as etching. In one embodiment, the photoresist material is used to create a patterned mask to define the first electrode 124. The opening can be formed by an etching process, such as an anisotropic or isotropic etching process. Process, such as an anisotropic dry etch process. After the etching process, the residual photoresist is removed, and then, a conductive material is filled in the opening. The excess conductive material can be removed using a planarization process, such as a chemical mechanical polishing (CMP) process. Other processes such as electroplating, etching, dual damascene, and the like can also be used.

The first electrode 124 can be formed of any suitable electrically conductive material, such as a highly conductive, low resistance metal, elemental metal, transition metal, or the like, including a metal or metal alloy, including one or more of aluminum, aluminum copper, copper, titanium. , titanium nitride, tungsten and the like. In addition, the first electrode 124 can include a barrier/adhesion layer to avoid diffusion and provide better adhesion between the first electrode 124 and the surrounding dielectric layer. The first electrode 124 can be formed by, for example, physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on deposition, or other suitable method.

It should be noted that the position and shape of the first electrode 124 provided herein are for illustrative purposes only. Additionally, the first electrode 124 can include a wire and/or a redistribution line to laterally extend the first electrode 124 through the memory structure overlying it.

According to an embodiment, FIG. 2 illustrates a step of forming a fixed layer 120, a barrier layer 130, and a first ferromagnetic layer 140. The pinned layer 120 can be a single layer or a multilayer structure. For example, in one embodiment, the pinned layer 120 includes a layer of magnetic material such as cobalt iron, cobalt iron boron, nickel iron, cobalt, iron, nickel, or the like, which may have a thickness generally between 40 and 200 angstroms. In another embodiment, the pinned layer 120 can comprise multiple layers, such as a bottom layer formed of a suitable antiferromagnetic material such as platinum manganese, nickel manganese, lanthanum manganese, iron manganese or the like, and a magnetic material such as Cobalt iron, cobalt iron boron, nickel iron, cobalt, iron, nickel a cover layer formed by or the like. In this embodiment, the thickness of the antiferromagnetic layer at the bottom is generally between 40 and 200 angstroms, and the thickness of the magnetic layer overlying it is generally between 40 and 200 angstroms.

In another embodiment, the pinned layer 120 can include an antiferromagnetic layer and a giant magnetoresistance (GMR) structure overlying it. The antiferromagnetic layer may comprise a suitable antiferromagnetic material, such as platinum manganese, nickel manganese, lanthanum manganese, iron manganese or the like, having a thickness generally between 40 and 200 angstroms. The giant magnetoresistive structure covered thereon may comprise two magnetic layers having an intermediate conductive layer, for example, the two magnetic layers may be formed of any magnetic material, such as cobalt iron, cobalt iron boron, nickel iron, cobalt, iron, nickel, iron boron. , iron platinum or the like, the thickness of which is generally between 10 and 50 angstroms. The intermediate conductive layer may be formed of any suitable electrically conductive material, such as copper, tantalum, niobium or the like, having a thickness generally between 5 and 20 angstroms. However, other embodiments may use different materials, layers, thicknesses, and the like.

The barrier layer 130 can be, for example, a dielectric material such as magnesium oxide, aluminum oxide, and/or the like. In one embodiment, the thickness of the barrier layer 130 is generally between 5 and 30 angstroms.

In an embodiment, the first ferromagnetic layer 140 may be formed of any suitable magnetic material, such as cobalt iron boron, nickel iron, cobalt, iron, nickel, iron boron, iron platinum, and/or the like. The thickness is generally between 15 and 50 angstroms. The first ferromagnetic layer 140 can be formed using any suitable process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

According to an embodiment, FIG. 3 illustrates a patterning step of the pinned layer 120, the barrier layer 130, and the first ferromagnetic layer 140. Generally speaking, these layers are profitable. Patterning by photolithography, by forming a patterned mask to protect the portion of the pinned layer 120, the barrier layer 130 and the first ferromagnetic layer 140 to be retained, and then utilizing one or more acceptable techniques, for example, An anisotropic etch is performed to remove the exposed portions, after which a second dielectric layer 115 is formed on the wafer 100. The second dielectric layer 115 may include, for example, a low-k dielectric material such as phosphorous bismuth glass (PSG), borophosphoquinone glass (BPSG), fluorocarbon glass (FSG), SiOxCy, spin-on glass, spin-on polymer, Carbonium material, cerium oxide, tetraethyl decane (TEOS), compounds thereof, combinations thereof, or combinations or analogs thereof. It can be formed by any suitable method, such as spin coating, chemical vapor deposition (CVD), and plasma assisted chemical vapor deposition (PECVD). It should be noted that the second dielectric layer 115 may include a plurality of dielectric layers. A planarization process such as a chemical mechanical polishing (CMP) process may be performed to expose the upper surface of the first ferromagnetic layer 140, the structure of which is shown in FIG.

According to an embodiment, FIG. 4 illustrates the steps of forming a gap layer 220 and a second ferromagnetic layer 230. The gap layer 220 can be a conductive layer formed of any suitable electrically conductive material, including metallic materials such as copper, tantalum, niobium, combinations thereof, and/or the like. In one embodiment, the thickness of the gap layer 220 is generally between 5 and 20 angstroms. In an embodiment, the thickness of the gap layer 220 is less than the thickness of the first ferromagnetic layer 140. The second ferromagnetic layer 230 may be formed of any suitable ferromagnetic material, such as cobalt iron boron, nickel iron, cobalt, iron, nickel, iron boron, iron platinum, and/or the like, and has a thickness generally between 10 and 50 angstroms. .

According to an embodiment, FIG. 5 illustrates a patterning step of the gap layer 220 and the second ferromagnetic layer 230. The gap layer 220 and the second ferromagnetic layer 230 pattern the fixed layer 120, the barrier layer 130 and the first ferromagnetic layer in a manner similar to that shown in FIG. The way of 140 is patterned. For example, a mask layer is formed and patterned by photolithography to expose portions of the gap layer 220 and the second ferromagnetic layer 230 that are not desired to be retained, using one or more etching processes to remove the gap layer 220. With the exposed portion of the second ferromagnetic layer 230, a structure as shown in Fig. 5 is formed. A third dielectric layer 135 is formed using a similar material and process of the second dielectric layer 115 described above.

In one embodiment, the first ferromagnetic layer 140, the gap layer 220, and the second ferromagnetic layer 230 form a giant magnetoresistance (GMR) structure, which may be considered as an embodiment using a giant magnetoresistive structure instead of a magnetoresistive type. A free layer of random access memory (MRAM) components. It should be noted that in the embodiment illustrated in FIG. 5, the width of the second ferromagnetic layer 230 and the gap layer 220 after patterning is different from the width of the lower first ferromagnetic layer 140. In this manner, electrical contact to the first ferromagnetic layer 140 is readily formed, such as the description of Figures 6A and 6B below.

The fixed layer 120 may also include a giant magnetoresistive (GMR) structure. In this embodiment, the fixed layer 120 includes a first giant magnetoresistance (GMR) structure, and the first ferromagnetic layer 140, the gap layer 220 and the second layer The ferromagnetic layer 230 forms a second giant magnetoresistance (GMR) structure.

6A and 6B are respectively a cross-sectional view and a plan view showing a fourth dielectric layer 145, a second electrode 324 and a third electrode 224, wherein FIG. 6A is along the sixth A cross-sectional view taken from the section line A-A'. The fourth dielectric layer 145 can be formed using a material and process similar to the second dielectric layer 115 described above. Thereafter, the second electrode 324 may be formed through the fourth dielectric layer 145, and the third electrode 224 may be formed through the third dielectric layer 135 and the fourth dielectric layer 145, thereby respectively providing the second ferromagnetic layer 230 with Electrical contact of the first ferromagnetic layer 140.

According to an embodiment, Figures 6A and 6B illustrate the relative positions of the different electrodes and layers. For example, the distances D1, D2, and D3 illustrate the patterned layer (ie, the fixed layer 120, the barrier layer 130, and the first ferromagnetic layer 140) with respect to the upper patterned layer (ie, the gap layer 220 and the second ferromagnetic layer 230) and Relative to the position of the third electrode 224. 6B is a plan view illustrating the size of the elliptical pattern of the lower patterned layer (ie, the fixed layer 120, the barrier layer 130, and the first ferromagnetic layer 140), for example, having a length B and a width A, and an upper patterned layer (ie, a gap) The dimensions of the elliptical pattern of layer 220 and second ferromagnetic layer 230, for example, have a length b and a width a.

In one embodiment, the value of distance D1 (the distance from the edge of the lower patterned layer to the lateral edge of the upper patterned layer) is generally between 0 and (B-b) / 4 nm. The range of distance D2 (the lateral distance between the upper patterned layer and the third electrode 224) is generally in the range of 10 to (B-b) / 4 nm. The value of the distance D3 (the distance from the third electrode 224 to the lateral side of the lateral edge of the lower patterned layer) is generally between 0 and (B-b) / 4 nm. In an embodiment, the first electrode 124, the second electrode 324, and the third electrode 224 may be disposed along a centerline of the elliptical shape, such as along the centerline A/2. In an embodiment, the aspect ratios b/a and B/A may range from 1 to 3.5. In an embodiment, a may be between 10 and 100 nm.

It should be noted that the shapes, dimensions, distances, relative positions, and ratios provided above are for illustrative purposes only. Other embodiments may use different shapes (e.g., circular, square, rectangular, etc.), dimensions, relative positions, ratios, and the like.

According to another embodiment, the 7A and 7B drawings respectively illustrate a cross-sectional view and A plan view in which Fig. 7A is a cross-sectional view taken along line B-B' of Fig. 7B. In this embodiment, the orientation order of the pinned layer 120, the barrier layer 130, the first ferromagnetic layer 140, the gap layer 220, and the second ferromagnetic layer 230 in the layering process is reversed. This embodiment can utilize processes and materials similar to those described above.

According to an embodiment, Figures 7A and 7B also illustrate relative distances D1, D2, D3 and relative dimensions A, B, a, b. In an embodiment, the values of the distances and dimensions may be similar to the values described in the above FIGS. 6A and 6B, wherein in this embodiment, the lower patterned layer includes the first ferromagnetic layer 140, the gap layer 220, and The second ferromagnetic layer 230, and the upper patterned layer includes the fixed layer 120 and the barrier layer 130.

According to an embodiment, Figures 8A-8D illustrate the operation of the memory unit. It should be noted that this operational procedure is described with respect to the embodiments illustrated in Figures 6A and 6B. In this embodiment, the first electrode 124 serves as a read bit line (BL), and the second electrode 324 serves as a write source line (SL). 224 is written as a bit line (write bit-line (BL)).

Referring to FIG. 8A, a process of “writing to 0” is illustrated, in which the current flow direction flows from the third electrode 224 (electrically coupled to the first ferromagnetic layer 140) to the second electrode 324 (electricity). The second ferromagnetic layer 230 is coupled such that the magnetic direction of the giant magnetoresistance (GMR) structure changes from an anti-parallel alignment to a parallel alignment related to the magnetic direction of the fixed layer 120. Therefore, a low resistance element state is created. Due to this lower resistance giant magnetoresistance (GMR) structure, the required current for inverting the magnetization of the free layer (Giant Magnetoresistive (GMR) structure) can be effectively reduced. In addition, across the barrier The smaller voltage of layer 130 can reduce the chance of exceeding the breakdown voltage, resulting in reduced barrier damage opportunities.

Figure 8B illustrates a "write to 1" process in which the direction of current flow is opposite to the direction of current flow of the "write to 0" process. In the process of "write to 1", current flows from the second electrode 324 (electrically coupled to the second ferromagnetic layer 230) to the third electrode 224 (electrically coupled to the first ferromagnetic layer 140) The magnetic direction of the giant magnetoresistance (GMR) structure is changed from a parallel alignment to an anti-parallel alignment associated with the magnetic orientation of the fixed layer 120. Therefore, a high resistance element state is created. The process of this current through the giant magnetoresistance (GMR) structure bypasses the necessity of current to pass through the barrier layer 130 and the pinned layer 120. Due to this lower resistance giant magnetoresistance (GMR) structure, the required current for inverting the magnetization of the free layer (Giant Magnetoresistive (GMR) structure) can be effectively reduced. In addition, a smaller voltage across the barrier layer 130 can reduce the chance of exceeding the breakdown voltage, resulting in a reduced chance of damage to the barrier layer 130.

Figures 8C and 8D illustrate different embodiments of the component reading process. In an embodiment, for example, as shown in FIG. 8C, the reading process is performed by applying a small voltage to the first electrode 124 (electrically coupled to the pinned layer 120) and the second electrode 324 (electrically coupled to the second The current is sampled between the ferromagnetic layers 230) to detect the resistance state (low or high) of the magnetoresistive random access memory (MRAM) device. In another embodiment, as shown in FIG. 8D, the reading process is performed by applying a small voltage to the first electrode 124 (electrically coupled to the fixed layer 120) and the third electrode 224 (electrically coupled The current is sampled between a ferromagnetic layer 140) to detect the resistance state (low or high) of the spin torque transmitting magnetoresistive random access memory (STT-MRAM) component. Since only a small voltage is required to perform a read operation, The reading process has minimal impact on the barrier breakdown voltage. In addition, separate electrodes with read and write storage elements allow for higher speed read/write access to stored data in the elements.

The read/write process of the foregoing process like the elements of Figs. 6A and 6B can be applied to, for example, the embodiments shown in Figs. 7A and 7B. For example, referring to FIG. 7A, a writing process is induced by using the first electrode 124 of the component (electrically coupled to the second ferromagnetic layer 230) and the second electrode 324 (electrically coupling the pinned layer 120). In order to perform a read operation, an embodiment may utilize a first electrode 124 (electrically coupled to the second ferromagnetic layer 230) and a second electrode 324 (electrically coupled to the pinned layer 120). In another embodiment, the first electrode 124 (electrically coupled to the second ferromagnetic layer 230) and the third electrode 224 (electrically coupled to the first ferromagnetic layer 140) can be used to read the component.

According to an embodiment, FIG. 9 illustrates an array of magnetoresistive random access memory (MRAM) elements, such as described above. A write source line (SL) is connected to the second electrode 324 of the component shown in FIG. 6A, and a write bit line (BL) is connected to the component shown in FIG. The third electrode 224, and a read bit line (BL) are connected to the first electrode 124 of the element shown in Fig. 6A.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

100‧‧‧ wafer

110‧‧‧ dielectric layer

115‧‧‧Second dielectric layer

120‧‧‧Fixed layer

124‧‧‧First electrode

130‧‧‧Barrier layer

135‧‧‧ third dielectric layer

140‧‧‧First Ferromagnetic Layer

145‧‧‧fourth dielectric layer

220‧‧‧ gap layer

224‧‧‧ third electrode

230‧‧‧Second ferromagnetic layer

324‧‧‧second electrode

a‧‧‧The width of the elliptical pattern on the patterned layer

A‧‧‧The width of the elliptical pattern of the patterned layer

A/2‧‧‧ elliptical shape centerline

B‧‧‧ Length of the elliptical pattern on the patterned layer

B‧‧‧The length of the elliptical pattern of the patterned layer

D1‧‧‧From the side of the lower patterned layer to the lateral edge of the upper patterned layer

The lateral distance between the patterned layer and the third electrode on D2‧‧

D3‧‧‧One-way distance from the third electrode to the lateral edge of the lower patterned layer

FIGS. 1 to 5 and 6A-6B illustrate a method of forming a phase change memory according to an embodiment.

7A-7B illustrate another embodiment of a magnetoresistive random access memory (MRAM) device.

8A to 8D are diagrams illustrating a method of setting/clearing a memory state (writing) and reading a memory state, according to an embodiment.

Figure 9 illustrates a magnetoresistive random access memory (MRAM) array in accordance with an embodiment.

100‧‧‧ wafer

110‧‧‧ dielectric layer

115‧‧‧Second dielectric layer

120‧‧‧Fixed layer

124‧‧‧First electrode

130‧‧‧Barrier layer

135‧‧‧ third dielectric layer

140‧‧‧First Ferromagnetic Layer

145‧‧‧fourth dielectric layer

220‧‧‧ gap layer

224‧‧‧ third electrode

230‧‧‧Second ferromagnetic layer

324‧‧‧second electrode

D1‧‧‧From the side of the lower patterned layer to the lateral edge of the upper patterned layer

The lateral distance between the patterned layer and the third electrode on D2‧‧

D3‧‧‧One-way distance from the third electrode to the lateral edge of the lower patterned layer

Claims (12)

A magnetoresistive random access memory (MRAM) comprising: a fixed magnetic layer; a barrier layer adjacent to the fixed magnetic layer; and a giant magnetoresistance (GMR) structure, adjacent The barrier layer, the giant magnetoresistance (GMR) structure includes a first magnetic layer, a second magnetic layer and a conductive layer, the conductive layer is interposed between the first magnetic layer and the second magnetic layer, The size of the first magnetic layer is different from the size of the second magnetic layer. The magnetoresistive random access memory (MRAM) of claim 1, further comprising: a first electrode electrically coupled to the fixed magnetic layer; and a second electrode electrically coupled to the giant a first magnetic layer of a magnetoresistive (GMR) structure; and a third electrode electrically coupled to the second magnetic layer of the giant magnetoresistive (GMR) structure. The magnetoresistive random access memory (MRAM) according to claim 1, wherein the first magnetic layer is adjacent to the barrier layer than the second magnetic layer, and the thickness of the second magnetic layer is greater than the first The thickness of a magnetic layer. The magnetoresistive random access memory (MRAM) of claim 1, wherein the fixed magnetic layer, the barrier layer and the first magnetic layer have the same length and width, and the conductive layer The second magnetic layer has the same length and width. Reluctance random access memory as described in claim 1 The body (MRAM), wherein the fixed magnetic layer has the same length and width as the barrier layer, and the first magnetic layer, the conductive layer and the second magnetic layer have the same length and width. A magnetoresistive random access memory (MRAM) comprising: a fixed layer; a barrier layer adjacent to the fixed layer; a giant magnetoresistance (GMR) structure adjacent to the barrier a giant magnetoresistive (GMR) structure comprising a first magnetic layer, a second magnetic layer and a conductive layer, the conductive layer being interposed between the first magnetic layer and the second magnetic layer; a write electrode coupled to the first magnetic layer and a second write electrode coupled to the second magnetic layer. The magnetoresistive random access memory (MRAM) according to claim 6, wherein the length of the first magnetic layer is greater than the length of the second magnetic layer. The magnetoresistive random access memory (MRAM) according to claim 6, wherein the length of the first magnetic layer is greater than the length of the fixed layer. A magnetoresistive random access memory (MRAM) comprising: a fixed layer; a barrier layer adjacent to the fixed layer; a first magnetic layer adjacent to the barrier layer; a conductive layer adjacent to the first magnetic layer; a second magnetic layer adjacent to the conductive layer; a first electrode directly coupled to the first magnetic layer; and a second electrode directly coupled to the second magnetic layer . The magnetoresistive random access memory (MRAM) according to claim 9, wherein the fixed layer, the barrier layer and the first magnetic layer have the same length and width. The magnetoresistive random access memory (MRAM) according to claim 9, wherein the width of the first magnetic layer, the conductive layer and the second magnetic layer is greater than the width of the fixed layer. The magnetoresistive random access memory (MRAM) according to claim 9, further comprising a third electrode coupled to the fixed layer.