TW201336128A - Memory cell and integrated circuit with programmable metallization cell and operating method and manufacturing method of the same - Google Patents

Abstract

A programmable metallization device comprises a first electrode and a second electrode, and a first dielectric layer, a second dielectric layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the first dielectric layer to represent a data value. During read, a read bias is applied that is sufficient to cause formation of a transient conductive bridge in the second dielectric layer, and make a conductive path through the memory cell if the conductive bridge is present in the first dielectric layer. If the conductive bridge is not present in the first dielectric layer during the read, then the conductive path is not formed. Upon removal of the read bias voltage any the conductive bridge formed in the second dielectric layer is destructed while the conductive bridge in the corresponding other first dielectric layer, if any, remains.

Description

Memory device and integrated circuit with programmable metallization unit, operation method and manufacturing method thereof

This invention relates to a programmable metallization unit technique.

Programmable Metallization Cell (PMC) technology is being studied for non-volatile memory, reconfigurable logic systems, and other switching applications due to its low current, expandability, and high program speed. . The resistance switching of the programmable metallization unit device operates via electro-chemical (EC) or electrolytic generation or removal of a conductive bridge. Thus, a programmable metallization unit device also represents a conducting bridge (CB) device or an electrochemical device.

The programmable metallization cell device has an ON state and an OFF state. In the on state, the conductive bridge completes the conduction path between the electrodes. In the off state, the conductive bridge is reduced without completing the interelectrode. The pathway of transmission. When the configuration is placed in the memory array under the transistor, the diodes and other access devices need to prevent current from unselected cells interfering with the reading and other operations of the selected cells in the on state.

In order to achieve high density memory storage, many concepts of three-dimensional memory have been proposed. Li et al., published in the September 2004 issue of IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, Volume 3, Volume 4, "Evaluation of SiO ₂ Antifuse in a 3D-OTP Memory" describes a polycrystalline germanium diode and counter A memory unit configured by a fuse. Sasago et al., 2009, published in the journal "2009 Symposium on VLSI Technology Digest of Technical Papers", pages 24~25" Cross-point phase change memory with 4F ² cell size driven by low-contact-resistivity poly-Si diode A memory cell in which a polycrystalline germanium diode and a phase change element are configured is described. Kau et al., published in the publication "IEDM09-617" in 2009, pages 27.1.1~27.1.4 "A stackable cross point phase change memory" describes a memory unit including an ovonic threshold switch (OTS) ) as an isolation device and a phase conversion element. These techniques combine a separation device with a memory element to construct a memory unit. The separation device adds additional processing and thickness and/or area of the memory structure. Moreover, the manner in which the device/memory element is separated is not suitable for many three-dimensional memory structures, including the so-called BICS structure (Bit Cost Scalable) and other three-dimensional memory structures including a large number of memory layers.

In Chen et al., published in 2003 in the publication "IEDM 03-905", pages 37.4.1~37.4.4" An Access-Transistor-Free (0T/lR) Non-Volatile Resistance Random Access Memory (RRAM) Using A Novel Threshold Switching, Self-Rectifying Chalcogenide Device describes a so-called "zero transistor/one resistor" (0T/1R) in which phase conversion elements are used without a separate separation. Device.

Therefore, there is an urgent need to provide a memory technology with a high density structure and easy fabrication, which is suitable for, for example, a so-called "zero transistor/single resistance" array.

According to the present invention, a memory device is provided comprising a first electrode, a programmable metallization unit, and a second electrode. The programmable metallization cell has a first state in which a conductive bridge does not extend from the first electrode to an intermediate distance between the electrodes; a second state in which the conductive bridge extends from the first electrode to an intermediate distance between the electrodes; A third state wherein the conductive bridge extends from the first electrode to the second electrode. The memory structure may include a first dielectric layer electrically coupled to the first electrode and adapted to electrolytically form and destroy the conductive bridge therein, and a second dielectric layer electrically connected to the first dielectric layer and suitable for electrolysis And destroy the conductive bridges in them. The intermediate distance may correspond to a distance between the first electrode to the interface between the first dielectric layer and the second dielectric layer. An ion providing layer is between the second dielectric layer and the second electrode, and optionally, an additional intermediate ion providing layer is located between the first dielectric layer and the second dielectric layer. More than one ion providing layer includes more than one ion source, such that ions can diffuse into and out of the first dielectric layer and the second dielectric layer to support formation and destruction of a plurality of conducting bridges to establish first and second And the third state. The memory structure is characterized by a first bias state including a threshold voltage or current, necessary to switch the memory structure from the first state to the third state; and a second bias state including a threshold voltage or The current is necessary to switch the memory structure from the second state to the third state.

Memory devices of this type may be configured as an array, and circuitry may be coupled to the array to provide a bias voltage to the first and second electrodes, to set the memory structure in a first state to represent a first data value, and to set a memory structure In the second state to represent a second data value. To sense the data value, a read bias state is provided to induce a voltage or current level between the first state and the threshold of the second state. As such, the read bias is sufficient to transition the cell from the second state to the third state, but insufficient to transition the cell from the first state to the third state.

The array can be presented in a cross-point array manner, and the memory cells are formed on the interface of the intersection of the plurality of word lines and the plurality of bit lines. The array can include a plurality of two-dimensional arrays of intersections stacked into a three-dimensional array.

Other aspects and advantages of the present invention can be seen in the following figures, embodiments, and claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the embodiments will be described in detail with reference to the drawings 1 to 11 of the drawings.

1 is a cross-sectional view of a programmable metallization cell having two dielectric layers in accordance with an embodiment of the present invention. The programmable metallization cell includes a first electrode 100. In an embodiment, the first electrode 100 includes a plug in a via of the interlayer dielectric 111. This unit includes a first dielectric layer 102 stacked and contacting the first electrode 100. The second dielectric layer 104 is stacked on the first dielectric layer 102 and has an intermediate distance between the first electrode 100 and the second electrode 110. The first dielectric layer 102 and the second dielectric layer 104 can comprise any dielectric material adapted to allow conductive ions to diffuse through the layers and to form the conductive bridges in the programmable metallization unit. Such a dielectric layer can be yttrium oxide. The first dielectric layer 102 and the second dielectric layer 104 can be of different materials such that the metal ions have different diffusion rates in these layers. Moreover, the thickness of the second dielectric layer 104 may be less than the thickness of the first dielectric layer 102.

The ion providing layer 108 is stacked on the second dielectric layer 104 to provide an ion source to form a conductive bridge in the first dielectric layer 102 and the second dielectric layer 104. The ion providing layer 108 may include a chalcogenide layer such as a diterpene diselenide compound (Ge ₂ Se ₂ Te ₅ ), and may further include a metal ion such as copper. Copper can react with ruthenium in the chalcogenide to form a Cu-Te compound. Such a copper beryllium compound can be easily dissolved to release copper ions to diffuse into the first dielectric layer 102 and the second dielectric layer 104, so that a conductive bridge can be formed in the memory cell.

The second electrode 110 is stacked on the ion supply layer 108. The second electrode 110 can be composed of a patterned copper-containing metallization element, or any other metallization technique that is compatible with adjacent layers.

Providing a biasing state having a first polarity to a programmable metallization cell between the first electrode 100 and the second electrode 110 such that ions provided by the ion providing layer 108 migrate to the first dielectric layer 102 and the second dielectric layer 104 And establish a conductive bridge via, for example, electroplating. The resulting conductive bridge may be sufficient to join the first electrode 100 to the ion providing layer 108 such that the conductive bridge extends through both the first dielectric layer 102 and the second dielectric layer 104. The conductive bridge establishes the third state described above and establishes a conductive state in the programmable metallization cell. Changing the bias state of the programmable metallization cell, including, for example, changing to a neutral bias in another embodiment, can stop the formation of the conductive bridge in the programmable metallization cell and cause the conductive bridge to dissolve until only extended to The intermediate distance between the first electrode 100 and the second electrode 110, for example, extends to the interface 106. The conductive bridge remains in the second dielectric layer 102 to establish the second state described above. In the second state, the memory cell has a high resistance. A bias state having a second polarity is provided such that the conductive bridge extends from the first electrode 100 to an intermediate distance and further dissolves, or is completely dissolved, establishing the first state described above. In the first state, the memory cell has a high resistance. The bias state required to establish the third state has a first threshold and a second threshold that is higher than the first threshold. The first threshold is used to transition the cell from the second state to the third state, the second threshold being used to transition the cell from the first state to the third state. In the third state, the memory cell has a low resistance. The difference in these threshold values is used to provide information for reading the memory unit.

In another embodiment, the memory structure can be configured to be stored in a cell by forming a plurality of conductive bridges to an intermediate distance between more than one of the electrodes, and matching a plurality of threshold levels corresponding to the third state of the low resistance. More than one bit.

2 is a cross-sectional view showing a configuration of a programmable metallization unit having two dielectric layers and an intermediate ion supply layer 124 at an intermediate distance between the first electrode and the second electrode in accordance with another embodiment of the present invention. Figure. As with the previous configuration, the programmable metallization cell can include the first electrode 120 extending through the interlayer dielectric 121. The first dielectric layer 122 is in contact with the first electrode 120. The second dielectric layer 126 is stacked on the intermediate ion providing layer 124 such that the intermediate ion providing layer 124 is located at the interface 125 of the first dielectric layer 122 and the second dielectric layer 126. The first dielectric layer 122 and the second dielectric layer 126 can be any dielectric material suitable to allow diffusion of metal ions through the dielectric layer. In particular, the first dielectric layer 122 and the second dielectric layer 126 may be hafnium oxide. Also, the first dielectric layer 122 and the second dielectric layer 126 can be of different materials such that the metal ions have different diffusion rates in the layers.

The programmable metallization cell as shown in FIG. 2 includes a first ion providing layer 128 overlying the second dielectric layer 126. The first ion providing layer 128 may include a chalcogenide layer as described above, for example, a diterpene diselenium quinone compound (Ge ₂ Se ₂ Te ₅ ), and may further include a metal ion source such as copper, which may be A conductive bridge is formed in the memory unit. In an embodiment, the intermediate ion providing layer 124 is disposed between the first dielectric layer 122 and the second dielectric layer 126.

The intermediate ion providing layer 124 can include any material suitable for generating metal ions that can diffuse into the first dielectric layer 122 and the second dielectric layer 126. The intermediate ion supply layer 124 may include a chalcogenide layer such as a bismuth diselenium ruthenium compound (Ge ₂ Se ₂ Te ₅ ), and may further include a metal ion source such as copper. Copper can react with ruthenium in the chalcogenide to form a Cu-Te compound. Such a copper ruthenium compound can be easily dissolved to release copper ions from diffusing into the first dielectric layer 122 and the second dielectric layer 126, so that a conductive bridge can be formed in the memory cell. Additionally, the intermediate ion providing layer 124 can include metal ions that are suitable for forming into the first dielectric layer 122 and the second dielectric layer 126 when current is applied. In particular, the second ion providing layer may include a refractory metal.

The memory unit may also include the second electrode 130 in contact with the first ion providing layer 128. The second electrode 130 can be any electrically conductive material that can conduct current to create a bias across the memory cell.

The configuration operation mode of the programmable metallization unit as shown in Fig. 2 is the same as that of the first figure. Increasing the intermediate ion providing layer 124 promotes formation and dissolution of the conductive bridge in the second dielectric layer, corresponding to the transition of the second state and the third state described above. Moreover, the intermediate ion providing layer 124 promotes formation and dissolution of the conductive bridge in the first dielectric layer, corresponding to the transition of the first state and the third state described above, or the transition of the first state and the second state.

3A to 3C are diagrams showing a series of states of the memory cell that is switched back and forth from the first state to the third state during the "set" operation of the programmable metallization unit shown in Fig. 2 of the present invention. Figure 3 illustrates the programmable metallization cell having a high resistance, i.e., the first state, prior to the formation of the conductive bridge. The first state corresponds to the first data value of the unit. The programmable metallization cell includes a first dielectric layer 131 and a second dielectric layer 132 in accordance with the configuration of the programmable metallization cell shown in FIG. The first dielectric layer 131 is stacked and in contact with the first electrode 138. The first ion supply layer 134 is stacked on the second dielectric layer 132. The intermediate ion supply layer 136 is disposed between the first dielectric layer 131 and the second dielectric layer 132. The second electrode 139 is stacked and electrically in contact with the first ion providing layer 134. The cell as shown in FIG. 3A is in a first state in which the conductive bridge is absent either in the first dielectric layer 131 or in the second dielectric layer 132.

FIG. 3B illustrates a state in which a set bias state is provided to the cell, indicated by arrow 150, having a first polarity during the "set" operation to transition the first state as shown in FIG. 3A to a conductive third state. A bias is provided between the first electrode 138 and the second electrode 139 to form a conductive bridge 140 across the first dielectric layer 131, and a conductive bridge 141 spans the second dielectric layer 132. In operation, conductive bridges 140 and 141 are generated, for example, by electrochemical or electroplating migration of metal ions into first dielectric layer 131 and second dielectric layer 132. These conductive bridges are generated sufficient to contact the conductive bridge 140 in the first dielectric layer 131 with the intermediate ion providing layer 136 and the conductive bridge 141 in the second dielectric layer 132 to contact the first ion providing layer 134. As a result, the unit assumes the third state and has a low resistance state.

FIG. 3C illustrates a unit that transitions from a collective operation to a neutral bias state after providing a collective bias state. In the neutral bias state, ions forming the conductive bridge 141 in the second dielectric layer 132 migrate out as indicated by the arrow 160 to enter the first ion supply layer or the intermediate ion supply layer, thereby damaging the conductive bridge 141. As such, the conductive bridge 141 can be considered temporary or transient. When ions migrate out of one of the first dielectric layer 131 and the second dielectric layer 132, the ions do not migrate out of the first dielectric layer 131. The second dielectric layer 132 may have a higher solubility for metal ions, and the thickness of the second dielectric layer 132 is less than the thickness of the first dielectric layer 131. Also, in the embodiment, both sides of the second dielectric layer are in contact with the ion providing layer. The above features promote rapid dissolution of the conductive bridge 141 in a neutral bias or low bias state. After the conductive bridge 141 is broken, the conductive bridge 140 remains in the first dielectric layer 131. As such, the cell as shown in FIG. 3C is in the second state of high resistance, corresponding to the second data value of the cell.

FIGS. 4A and 4B illustrate operational applications of the read bias state, as indicated by arrow 151. FIG. 4A illustrates the second state (or set state) as shown in FIG. 3C at the time of the read operation. Figure 4B illustrates the first state (or reset state) of the unit as shown in Figure 3A during the read operation.

FIG. 4A illustrates that when the cell begins with the second state of the conductive bridge 140 in the dielectric layer 131, a read bias is applied as indicated by arrow 151, and a temporary filament 146 is formed in the dielectric layer 132. , causing the memory cell to switch to the third state of conduction. After the read bias is removed, the temporary filament is broken as in the above-described FIG. 3C.

4B illustrates the application of a read bias 151 as indicated by arrow 151, any filament formed in the dielectric layer 131, starting from a first state in which the conductive layer is not present in the dielectric layer 131. For example, the filament 140a) cannot complete the connection with the interface of the intermediate ion supply layer 136, and even if a temporary filament (not shown) is formed in the dielectric layer 132, the memory cell is maintained in a high resistance state. Also, any temporary filaments formed during the read state are destroyed by the read bias, at least substantially destroyed.

Therefore, during a read operation, the sense amplifier can detect the presence of current to determine whether the cell is in an aggregate state or a reset state.

Figure 5 illustrates the application of a reverse polarity biased cell in the reset state as indicated by arrow 155 to destroy any switchable cell as a conductive bridge representing a second state of the second data value, establishing a first data value. The unit of the first state. After the reset bias state is removed, the cell will remain in the first state of high resistance.

Figure 6 is a graph showing the voltage corresponding to the current applied to the programmable metallization cell, such as the cell shown in Figure 2. Line 170 represents the characteristics of the current voltage starting from the cell of the high resistance first state as shown in FIG. 3A, the applied bias state including a positive voltage at the top electrode and ground to the bottom electrode. When the voltage rises, the current through the cell remains very low until reaching the inversion point 172 at the threshold Vt2. When a voltage of the threshold value Vt2 is applied to the cell, the conductive bridge is simultaneously formed in the first dielectric layer and the second dielectric layer, thereby reaching a second state of conduction (collective state) in the cell, which is presented in FIG. Area 177. At this threshold, in the embodiment, the current intensity in the cell is increased by approximately three orders.

For cells starting from the second state, the conductive bridge is present in the first dielectric layer but not in the second dielectric layer, and the current-voltage characteristics of the reaction as indicated by the pattern 174 are shown as the voltage rises. When the voltage rises, the current through the cell remains very low until reaching the inversion point 173 at the threshold Vt1. When a voltage of the threshold value Vt1 is applied to the cell, a conductive bridge is formed in the second dielectric layer, thereby achieving a conductive state in the cell starting at region 175 in the graph.

When the voltage of the cell in the conductive third state as exhibited by region 177 drops, the current drops toward pattern 176 until region 175, corresponding to the disappearance of the conductive bridge in the second dielectric layer as shown in FIG. 3C. At region 175, the current drops again to a very low extent such that the cell is set to a second state of high resistance, wherein the conductive bridge remains in the first dielectric layer and not in the second dielectric layer.

Applying a bias having the opposite polarity as shown in pattern 179 turns the cell starting in the high resistance second state to a high resistance first state. When the negative voltage rises, the conductive bridge in the first dielectric layer is destroyed, and the cell is reset back to the high resistance first state as shown in FIG.

FIG. 6 also shows a reversal point 178 between the threshold values Vt1 and Vr2 at the read bias level VR. In the read operation, as shown in FIGS. 4A and 4B, a read bias state (such as arrows 151 shown in FIGS. 4A and 4B) is provided to generate a voltage of approximately VR across the cell. . This voltage is sufficient to cause the cell to transition from the second state along the pattern 174, but insufficient to cause the cell of the first state to transition along the line 170 to a conductive state. Therefore, the material can be represented via the state of the sensing unit. Also, both the first state and the second state used to represent the data value have a high resistance state in a neutral or low bias state, which allows operation to be performed without the need for an active access device.

Figure 7 is a schematic diagram of a cross-point memory array constructed with a "single-resistance" memory cell and that does not require a transistor or other active access device. As shown in FIG. 7, each memory cell in array 700 is represented by a resistive memory element along a current path between corresponding word lines 710a-710c and corresponding bit lines 720a-720c.

The array includes a plurality of word lines 710a, 710b, and 710c extending in parallel in a first direction, and a plurality of bit lines 720a, 720b, and 720c extending in parallel in a second direction, the first direction being perpendicular to the second direction. The array 700 is referred to as a cross-point array because the word lines 710a-710c and the bit lines 720a-720c cross each other but are not physically intersected, and the memory cells are at the intersection.

Memory unit 740 represents a plurality of memory cells in array 700 and is disposed at the intersection of word line 710b and bit line 720b. Memory unit 740 is passively coupled to word line 710b and passively coupled to bit line 720b.

Appropriate voltage pulses are applied to the corresponding word line 710b and bit line 720b to generate a collective bias state, a reset bias state, or a read bias state at the selected memory cell 740, and to apply an appropriate suppression voltage to The memory cells 740 of the array 700 can be read or written to the unselected word lines and bit lines. The extent and duration of voltage application depends on the operation, such as a read operation or a stylized operation. Current path 750 is formed in the selected cell (eg, cell 740). The leakage current to other cells of the array, such as shown by the leakage current path 751, is blocked by the position indicated by "X" because the cell is in the set state and the reset state (the first state and the second state) With high resistance, the current can be blocked in the bias state of the unselected unit. Thus, the combination of the voltage of the selected bit line 720a and the unselected word line 710c forms a bias voltage that is insufficient to cause current to pass back through the unselected cell 740 via path 751 to the selected bit line 720a. Moreover, the voltage from the selected word line 710b combined with the unselected bit line 720b forms a bias voltage that is insufficient to pass current through the unselected cell 742. Finally, the voltage from the unselected word line 710c is combined with the unselected bit line 720b to form a bias voltage that is insufficient to pass current through the unselected cell 743.

In an embodiment, at the read bias arrangement and the first and second reset bias arrangements, a pulse corresponding to a full voltage (eg, read voltage VR) is applied to the selected word line (eg, On word line 710b), a pulse corresponding to a half voltage V/2 (half voltage) is applied to unselected word lines (e.g., word lines 710a and 710c). Also, a zero voltage is applied to the selected bit line (e.g., bit line 720b), and a pulse corresponding to the half voltage V/2 is applied to the unselected bit lines (e.g., bit lines 720a and 720c). . This causes the selected cell 740 to receive a full pulse height V, and the unselected cell has a V/2 bias. In the embodiment, V/2 should be lower than Vt1 shown in Fig. 6.

In another embodiment, at the read bias arrangement and the first and second reset bias arrangements, a pulse corresponding to a full voltage V (eg, read voltage VR) is applied to the selected word line (eg, a word) On line 710b), a pulse corresponding to a third voltage V/3 is applied to the unselected word lines (e.g., word lines 710a and 710c). Also, a zero voltage is applied to the selected bit line (e.g., bit line 720b), and a pulse corresponding to two thirds of voltage 2V/3 is applied to the unselected bit line (for example, Bit lines 720a and 720c). This causes the selected unit 740 to receive the full pulse height V, and the unselected cells that are not in the selected word line or the selected bit line receive a +V/3 bias, share the selected word line or select The unselected cell of one of the bit lines receives a bias of -V/3. In this state, the degree of -V/3 should be low enough to prevent resetting or preventing interference of the conductive bridges in the cells having the second state in the cell.

A similar bias arrangement can be applied to the three-dimensional configuration of the memory device.

Figure 8 is a perspective view of a single cross point memory unit that can be built into the array of intersections as previously described. The array of intersections is characterized by a first access line 901, such as a word line, and a second access line 902, such as a bit line, the second access line 902 being stacked and generally orthogonal to the first Access line 901. The memory unit is formed at the intersection, and includes a four-layer structure as shown in FIG. Such layers include a first dielectric layer 903, an ion source layer 904, a second dielectric layer 905, and another ion source layer 906. The first dielectric layer 903 and the top ion source layer 906 of the cross-point unit are passively coupled to a plurality of access lines. It can also be described herein that the first component is "passively coupled" to the second component, and that there is electrical current flow communication between the first component and the second component, without being affected by, for example, a transistor or a diode. , or / and interference of the rectifying device or switching device of the bidirectional limit switch.

Fig. 9 is a cross-sectional view showing the structure shown in Fig. 8 in the X-Z plane. As described above, the memory unit 910 includes a four-layer structure including a first dielectric layer 903, an ion source layer 904, a second dielectric layer 905, and another ion source layer 906.

An array constructed with cross-point cells having configurations as shown in Figures 8 and 9 can have many layers, and each layer can have many bit lines and word lines to form a very high density memory device. Other three-dimensional configurations including three-dimensional arrays can also be implemented in which a plurality of word lines and a plurality of bit lines are configured to access multiple layers of a plurality of memory cells.

Figure 10 is a simplified manufacturing flow diagram of the programmable metallization unit as shown in Figure 2. In an embodiment, one word line acts as a plurality of bottom electrodes along the line of word lines. Thus, the process includes depositing a layer of word line material, a first dielectric material, an intermediate ion providing layer, a second dielectric material, and a top ion providing layer, as described in relation to Figure 2 (step 190). Next, the multilayer stack is patterned to form a plurality of columns (step 191). A filler material is provided and the filler material is planarized, followed by deposition of the bit line material over the entire structure (step 192). Following the next step, the bit line material in the multilayer stack is patterned (step 193). The bit line generated at this time is coupled to the rows of the plurality of memory cells, and the separated plurality of cells are stacked at the intersection of the word line and the bit line. Finally, a filler material is provided to complete the memory plane and the above operations are repeated to form a multi-layer memory plane (step 194).

The process technology provides an embodiment for: forming a plurality of bottom electrodes; forming a plurality of memory cell stacks, the memory cells including at least a first dielectric layer, a second dielectric layer, an ion supply layer arranged in series; and then forming a top electrode. In the foregoing embodiments, the process further includes forming an intermediate ion providing layer on the interface between the first dielectric layer and the second dielectric layer.

The second dielectric layer is characterized in particular by the ability to form a temporary conductive bridge or filament in a read bias state, while the temporary conductive bridge or filament may break or dissolve, for example, when the read bias state is removed, for example, Neutral bias. In order to achieve the characteristics of the above second dielectric layer, the material forming the second dielectric layer may be more soluble for metal ions than the first dielectric layer to form a conductive bridge or filament. For example, the first dielectric layer may be hafnium oxide (HfO), zirconium oxide (ZrO), tantalum oxide (TaO), hafnium oxide (GdO) or titanium oxide (TiO), and the second dielectric layer may be hafnium oxide (SiO). ), tantalum nitride (SiN) or bismuth oxynitride (SiON). Also, the first dielectric layer and the second dielectric layer may be the same material but have different thicknesses. For example, the first dielectric layer has a thickness in the range of 30 to 100 angstroms, and the second dielectric layer has a small thickness ranging from 10 to 30 angstroms.

11 is a simplified block flow diagram including an integrated circuit 300 having a memory array constructed with a "single resistance" programmable metallization cell array, the "single resistance" programmable metallization cell including a first dielectric layer And a second dielectric layer. The word line decoder 302 is coupled and electrically coupled to a plurality of word lines 304 disposed along a plurality of rows of the memory array 306. When reading, assembling, and resetting a plurality of memory cells in array 306, planar/bit line decoder 308 is electrically coupled to multiple rows along memory array 306 and along multiple planes Bit line 310. A plurality of addresses are provided by bus bars to word line decoder 302 and plane/bit line decoder 308. The sense circuit (sense amplifier) and input data structure in block 314 are coupled to the planar/bit line decoder 308 via data bus 316. The data is provided to the input/output port of the integrated circuit 300 via the input data line 318, or to the input data structure in block 314 via a data source internal or external to the other integrated circuit 300. The integrated circuit 300 can include other circuits 320, such as a general purpose processor, or a special purpose application circuit, or a single wafer system comprised of multiple modules that can be supported by the array 306. The data is provided by the sense amplifier in block 314 via the output data line 322 to the input/output ports of the integrated circuit 300, or to other data destinations internal or external to the integrated circuit 300.

The array 306 of memory cells can be comprised of a plurality of cells passively coupled to a plurality of bit lines and a plurality of word lines in the cross-point configuration, wherein the plurality of memory cells in the array respectively comprise a first dielectric layer The second dielectric layer and the ion supply layer are connected in series between the corresponding plurality of word lines and bit lines.

The integrated circuit 300 includes a sensing circuit in block 314 passively coupled to the plurality of memory cells to sense whether the selected memory cell has a threshold below a read threshold, wherein the threshold can cause the cell to transition to the aforementioned temporary Or transient state of conduction. Control circuit 324 is coupled to the plurality of bit lines and word lines to provide a plurality of biasing arrangements for memory cell operations, including: reading a bias arrangement to provide a read threshold to the selected memory cell; first write (collecting) a biasing arrangement to induce formation of a conducting bridge in the first dielectric layer of the selected memory cell, establishing a first threshold to cause the selected memory cell to transition to a conducting state, the first threshold being lower than reading a threshold value; and a second write (reset) bias arrangement to induce destruction of the conductive bridge in the first dielectric layer of the selected memory cell, establishing a second threshold to cause the selected memory cell to transition to a conductive state The second threshold is higher than the read threshold.

Moreover, in the memory technology of one embodiment described herein, the memory cell array includes a three-dimensional array, and a plurality of word lines and bit lines are configured to access a plurality of levels of memory cells in the three-dimensional array.

The controller 324 implemented in the embodiment uses a biasing arrangement state machine to control the application of the bias circuit voltage and current source 326 to apply these bias arrangements including set, reset, and read voltage and/or current. Up to multiple word lines and bit lines. Controller 324 can be constructed using special purpose logic circuitry well known in the art. In another embodiment, the controller 324 includes a general purpose processor built into the same integrated circuit to perform the operation of the computer software control device. In still another embodiment, the controller 324 can be constructed using a combination of special purpose logic circuitry and a general purpose processor.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 120, 138. . . First electrode

102, 122, 131, 903. . . First dielectric layer

104, 126, 132, 905. . . Second dielectric layer

106. . . interface

108, 128. . . Ion supply layer

110, 130, 139. . . Second electrode

111, 121. . . Interlayer dielectric

124, 136. . . Intermediate ion supply layer

128, 134. . . First ion supply layer

140, 141. . . Conductive bridge

140a. . . Silk

146. . . Temporary filament

150, 151, 155, 160. . . arrow

170. . . line

172, 173, 178. . . Reversal point

174, 176, 179. . . Graphics

175,177. . . region

190~194. . . step

300. . . Integrated circuit

302. . . Character line decoder

304, 710a~710c. . . Word line

306, 700. . . Array

308. . . Planar/bit line decoder

310, 720a~720c. . . Bit line

314. . . Square

316. . . Busbar

318. . . Input data line

320. . . Other circuit

322. . . Output data line

324. . . Control circuit

326. . . Bias circuit voltage and current source

740, 910. . . Memory unit

742, 743. . . Unselected memory unit

750. . . Current path

751. . . Leakage current path

901. . . First access line

902. . . Second access line

903, 904. . . Ion source layer

906. . . Top ion source layer

VR. . . Read bias

Vt1, Vt2. . . Threshold

X. . . position

1 is a cross-sectional view of a programmable metallization cell having two dielectric layers in accordance with an embodiment of the present invention.

2 is a cross-sectional view showing the configuration of a programmable metallization cell having two dielectric layers and an intermediate ion supply layer in accordance with another embodiment of the present invention.

3A to 3C are schematic views showing the collective operation of the programmable metallization unit shown in Fig. 2 of the present invention.

4A-4B are schematic diagrams respectively showing the read operation of the programmable metallization unit starting from the assembled state and the reset state according to the second embodiment of the present invention.

Figure 5 is a schematic diagram showing the reset operation of the programmable metallization unit shown in Figure 2 of the present invention.

6 is a graph showing a voltage corresponding current applied to a programmable metallization cell having two dielectric layers, the cell having a plurality of resistance states corresponding to the conductive bridge passing through the first dielectric layer, in accordance with an embodiment of the present invention. Multiple configurations of the second dielectric layer.

FIG. 7 is a circuit diagram showing the configuration of a programmable metallization unit in a planar array structure of a single-resistance cross-point according to an embodiment of the invention.

Figure 8 is a perspective view of a programmable metallization unit configuration for execution in an array of intersections in accordance with an embodiment of the present invention.

Figure 9 is a cross-sectional view showing the unit shown in Figure 8 of the present invention.

Figure 10 is a flow chart showing the fabrication of the configuration of the programmable metallization unit shown in Figure 2 of the present invention.

11 is a simplified block flow diagram of an integrated circuit 300 including a memory array constructed with programmable metallization cells in accordance with an embodiment of the present invention.

100. . . First electrode

102. . . First dielectric layer

104. . . Second dielectric layer

106. . . interface

108. . . Ion supply layer

110. . . Second electrode

111. . . Interlayer dielectric

Claims (19)

A memory device includes a programmable metallization unit, the programmable metallization unit comprising:
a first electrode and a second electrode; and a first dielectric layer, a second dielectric layer, and an ion supply layer are disposed in series between the first electrode and the second electrode, the ion providing layer including An ion source has a material adapted to form a plurality of electrically conductive bridges between the first dielectric layer and the second dielectric layer. The memory device of claim 1, wherein the first dielectric layer or the second dielectric layer comprises one or more materials that support electrolytic formation and destruction of the electrically conductive bridges. The memory device of claim 1, comprising a circuit for providing a bias state to the first electrode and the second electrode to induce the conductance in the first dielectric layer and the second dielectric layer Electrolysis of the bridge forms and destroys. The memory device of claim 1, wherein the first dielectric layer has a first thickness, and the second dielectric layer has a second thickness, the second thickness being less than the first thickness. The memory device of claim 1, comprising a conductive layer on one of the interfaces between the first dielectric layer and the second dielectric layer. The memory device of claim 5, wherein the interface comprises an intermediate ion providing layer. The memory device of claim 1, wherein the first dielectric layer and the second dielectric layer comprise different materials, and the second dielectric layer has an ion solubility higher than the first dielectric layer It has ion solubility. The memory device of claim 1, wherein the memory device comprises a plurality of units including the programmable metallization unit, the units being configured as an array of intersections. An integrated circuit comprising:
a plurality of bit lines and a plurality of word lines; and an array of memory cells is passively coupled to the bit lines and the word lines, each of the memory cells in the array Each of the first dielectric layer, a second dielectric layer, and an ion supply layer are respectively disposed in series between the corresponding bit lines and the word lines. The integrated circuit as described in claim 9 of the patent scope includes:
a sensing circuit coupled to the array of memory cells to sense whether a selected memory cell has a threshold value below a read threshold; and a control circuit coupled to the bit lines and the The word lines are provided to provide a plurality of bias arrangements to operate the memory units, including:
a read bias arrangement to provide the read threshold to the selected memory unit;
a first write bias arrangement for inducing formation of a conductive bridge in the first dielectric layer of the selected memory cell, establishing a first threshold to cause the selected memory cell to transition to a conductive state (conductive The first threshold is lower than the read threshold; and a second write bias is arranged to induce destruction of the bridge in the first dielectric layer of the selected memory cell to establish a The second threshold is such that the selected memory cell transitions to the conductive state, the second threshold being above the read threshold. The integrated circuit of claim 9, wherein the array of memory cells comprises a three-dimensional array, and the word lines and the bit lines are configured to access the three-dimensional array Multiple levels of the memory cells. A method of operating a programmable metallization cell array, comprising:
In a read mode, a read bias arrangement is provided to provide a read threshold to a selected memory unit;
In a first write mode, a first write bias arrangement is provided to induce formation of a conductive bridge in the first dielectric layer of the selected memory cell to establish a first threshold to enable the selection The memory cell transitions to a conductive state, the first threshold is below the read threshold; and in a second write mode, a second write bias arrangement is provided to induce the selected memory cell Destruction of the conductive bridge in the first dielectric layer establishes a second threshold to cause the selected memory cell to transition to the conductive state, the second threshold being below the read threshold. The method of claim 12, the programmable metallization cell array comprising the first dielectric layer, a second dielectric layer, and an ion supply layer are disposed in series corresponding to the bit lines and Between the word lines, and the conductive state corresponding to the conductive bridges forming a conductive path extending between the first dielectric layer and the second dielectric layer. The method of claim 12, wherein one of the first high resistance state and the second high resistance state corresponds to destruction of a portion of the conductive bridge such that the conduction path extends only through the selected memory One part of the unit. A method of fabricating a device including a programmable metallization memory cell, comprising:
Forming a first electrode;
Forming a first dielectric layer, a second dielectric layer, and an ion providing layer in series, the ion providing layer comprising an ion source having a conductive bridge material; and forming a second electrode contact The ion is provided with a layer. The method of claim 15, wherein the first dielectric layer and the second dielectric layer comprise a material suitable for electrolytic formation and destruction of a conductive bridge in the dielectric layers. The method of claim 15, further comprising forming an intermediate ion providing layer on one of the interfaces between the first dielectric layer and the second dielectric layer. The method of claim 15, wherein the first dielectric layer and the second dielectric layer comprise different materials, and one of the second dielectric layer and the first dielectric layer is for the conductive bridge The material has a solubility higher than the other of the second dielectric layer and the first dielectric layer. The method of claim 18, further comprising forming a plurality of memory cells configured as an array of intersections, the memory cells including the programmable metallization memory cells.