[go: up one dir, main page]

TW201320429A - Method for manufacturing display device, and display device - Google Patents

Method for manufacturing display device, and display device Download PDF

Info

Publication number
TW201320429A
TW201320429A TW101135184A TW101135184A TW201320429A TW 201320429 A TW201320429 A TW 201320429A TW 101135184 A TW101135184 A TW 101135184A TW 101135184 A TW101135184 A TW 101135184A TW 201320429 A TW201320429 A TW 201320429A
Authority
TW
Taiwan
Prior art keywords
layer
transparent electrode
electrode layer
sub
pixel
Prior art date
Application number
TW101135184A
Other languages
Chinese (zh)
Inventor
Shoji Okazaki
Tohru Sonoda
Hiromitsu Katsui
Tetsunori Tanaka
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Publication of TW201320429A publication Critical patent/TW201320429A/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621Providing a shape to conductive layers, e.g. patterning or selective deposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10Transparent electrodes, e.g. using graphene
    • H10K2102/101Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/103Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising indium oxides, e.g. ITO

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

An a-ITO layer (112) is formed above a reflection electrode layer (111) and the layers are etched together; the a-ITO layer (112) is then converted to a p-ITO layer (114); and the difference in etching resistance between the p-ITO layer (114) and a transparent electrode layer formed above the p-ITO layer is used to layer the transparent electrode layer and to vary the thickness of the transparent electrode layer (121) between subpixels (71R, 71G, 71B).

Description

顯示裝置之製造方法及顯示裝置 Display device manufacturing method and display device

本發明係關於一種於各子像素中之反射電極層上積層有透明電極層,並且於顯示色不同之子像素間使透明電極層之合計膜厚不同的顯示裝置之製造方法及此種顯示裝置。 The present invention relates to a method of manufacturing a display device in which a transparent electrode layer is laminated on a reflective electrode layer in each sub-pixel, and a total thickness of the transparent electrode layers is different between sub-pixels having different display colors, and such a display device.

近年來,於多種商品及領域中活用有平板顯示器,而要求平板顯示器之進一步之大型化、高畫質化、低耗電化。 In recent years, flat panel displays have been used in various products and fields, and further increase in size, high image quality, and low power consumption of flat panel displays are required.

於如上所述之狀況下,設有利用有機材料之電場發光(Electro Luminescence:電致發光、以下記作「EL」)之有機EL元件之有機EL顯示裝置係作為全固體型且於低電壓驅動、快速響應性、自發光性、視角廣闊特性等方面優異之平板顯示器而受到高度關注。 In the above-described situation, an organic EL display device having an organic EL element using electroluminescence (Electro Luminescence, hereinafter referred to as "EL") of an organic material is used as an all-solid type and is driven at a low voltage. Flat panel displays with excellent responsiveness, self-illumination, and wide viewing angles are highly regarded.

有機EL顯示裝置具有例如如下之構成:於包含設置有TFT(Thin Film Transistor:薄膜電晶體)之玻璃基板等之基板上,設置有電性連接於TFT之有機EL元件。 The organic EL display device has, for example, a configuration in which an organic EL element electrically connected to a TFT is provided on a substrate including a glass substrate provided with a TFT (Thin Film Transistor).

有機EL元件係可利用低電壓直流驅動進行高亮度發光之發光元件,其具有依序積層有第1電極、有機EL層、第2電極之構造。 The organic EL element is a light-emitting element that emits high-intensity light by low-voltage direct current driving, and has a structure in which a first electrode, an organic EL layer, and a second electrode are laminated in this order.

作為用以使利用如上所述之有機EL元件之有機EL顯示裝置全彩化之方式,已知有例如(1)將發出紅(R)、綠(G)、藍(B)之光之有機EL元件作為子像素而排列於基板上之方式、(2)組合白色發光之有機EL元件與濾光片而選擇各子像素中之發光色之方式。 As a method for fully coloring the organic EL display device using the organic EL element as described above, for example, (1) organic light emitting red (R), green (G), and blue (B) is known. The EL element is arranged as a sub-pixel on the substrate, and (2) the white-emitting organic EL element and the filter are combined to select the luminescent color in each sub-pixel.

近年來,於該等方式中,提出有利用微空腔效應而使發光色度或發光效率提高之方法(例如參照專利文獻1、2)。 In recent years, there has been proposed a method of improving luminescence chromaticity or luminescence efficiency by using a microcavity effect (see, for example, Patent Documents 1 and 2).

所謂微空腔,係指藉由發出之光於陽極與陰極之間進行多次反射並發生共振,而發射光譜變陡,且峰波長之發光強度放大之現象。 The term "microcavity" refers to a phenomenon in which the emitted light is reflected by the light emitted from the anode and the cathode and resonated, and the emission spectrum becomes steep, and the luminous intensity of the peak wavelength is amplified.

微空腔效應可藉由將例如陽極或陰極之反射率及膜厚、有機層之層厚等設計為最佳而獲得。 The microcavity effect can be obtained by designing, for example, the reflectance and film thickness of the anode or the cathode, the layer thickness of the organic layer, and the like as optimum.

作為對有機EL元件導入如上所述之共振構造即微空腔構造之方法,已知有例如針對每一發光色改變各子像素中之有機EL元件之光徑長之方法。 As a method of introducing the above-described resonant structure, that is, a microcavity structure, to the organic EL element, for example, a method of changing the optical path length of the organic EL element in each sub-pixel for each luminescent color is known.

作為針對每一發光色改變各子像素中之有機EL元件之光徑長之方法,可列舉於反射電極與半透明電極之間積層包含發光層之有機EL層與透明電極層之方法。 As a method of changing the optical path length of the organic EL element in each sub-pixel for each luminescent color, a method of laminating an organic EL layer including a light-emitting layer and a transparent electrode layer between a reflective electrode and a semi-transparent electrode is exemplified.

即,例如,於頂部發光型之有機EL元件之情形時,可列舉如下之方法:將陽極設為反射電極層與透明電極層之積層構造,針對每一子像素,改變陽極之反射電極層上之透明電極層之膜厚。 That is, for example, in the case of the top emission type organic EL element, a method in which the anode is a laminated structure of a reflective electrode layer and a transparent electrode layer, and the reflective electrode layer of the anode is changed for each sub-pixel The film thickness of the transparent electrode layer.

於頂部發光型之有機EL元件之情形時,如此般將陽極設為反射電極層與透明電極層之積層構造,適當積層有機EL層之後,對陰極使用例如製成薄膜之半透明之銀等而作為半透明電極,藉此可對有機EL元件導入微空腔構造。 In the case of the top emission type organic EL device, the anode is set as a laminated structure of the reflective electrode layer and the transparent electrode layer, and after the organic EL layer is appropriately laminated, for example, a semitransparent silver or the like which is formed into a thin film is used for the cathode. As the translucent electrode, the organic EL element can be introduced into the microcavity structure.

當如此般對有機EL元件導入微空腔構造時,自發光層發出,並通過陰極而射出之光之光譜較有機EL元件不具有微空腔構造之情形變陡,且朝向正面之出射強度大幅度增 大。 When the organic EL element is introduced into the microcavity structure as described above, the spectrum of the light emitted from the light-emitting layer and emitted through the cathode becomes steeper than the case where the organic EL element does not have the microcavity structure, and the emission intensity toward the front surface is large. Increase in amplitude Big.

專利文獻1、2中揭示有藉由針對每一子像素改變積層數而積層同一材料之透明電極層,而對有機EL元件導入微空腔構造之有機EL顯示裝置。 Patent Literatures 1 and 2 disclose an organic EL display device in which an organic EL element is introduced into a microcavity structure by laminating a transparent electrode layer of the same material by changing the number of layers for each sub-pixel.

[先前技術文獻] [Previous Technical Literature] [專利文獻] [Patent Literature]

[專利文獻1]日本公開專利公報「日本專利特開2007-280677號公報(2007年10月25日公開)」 [Patent Document 1] Japanese Laid-Open Patent Publication No. 2007-280677 (published on October 25, 2007)

[專利文獻2]日本公開專利公報「日本專利特開2005-116516號公報(2005年4月28日公開)」 [Patent Document 2] Japanese Laid-Open Patent Publication No. 2005-116516 (published on Apr. 28, 2005)

[專利文獻3]日本公開專利公報「日本專利特開2009-129604號公報(2009年6月11日公開)」 [Patent Document 3] Japanese Laid-Open Patent Publication No. 2009-129604 (published on June 11, 2009)

然而,於如上述般藉由改變透明電極層之膜厚而改變微空腔效應,調整發光色之方式之有機EL顯示裝置中,針對各色之每一子像素恰當地變更透明電極層之膜厚之方法尚不清楚。 However, in the organic EL display device in which the luminescence color is changed by changing the film thickness of the transparent electrode layer as described above, the film thickness of the transparent electrode layer is appropriately changed for each sub-pixel of each color. The method is still unclear.

再者,於專利文獻1中未揭示用以針對各色之每一子像素而變更透明電極之膜厚之方法。 Further, Patent Document 1 does not disclose a method for changing the film thickness of a transparent electrode for each sub-pixel of each color.

另一方面,於專利文獻2中,作為對積層之透明電極層使用同一材料而針對各色之每一子像素變更透明電極之膜厚之方法,揭示有以下之方法。 On the other hand, in Patent Document 2, as a method of changing the film thickness of the transparent electrode for each sub-pixel of each color by using the same material for the laminated transparent electrode layer, the following method is disclosed.

首先,一面按照B→G→R之順序變更積層抗蝕圖案之子 像素,一面於反射電極層上交替地積層透明電極層與抗蝕圖案。 First, the sub-layer resist pattern is changed in the order of B → G → R The pixels are alternately laminated with a transparent electrode layer and a resist pattern on the reflective electrode layer.

繼而,對R之子像素積層抗蝕圖案之後,將R之子像素之抗蝕圖案作為遮罩而對最上層之透明電極層進行蝕刻,使G之子像素之抗蝕圖案露出,此時以R及G之子像素之抗蝕圖案為遮罩,對從上至下第2個透明電極層進行蝕刻。 Then, after the resist pattern of the sub-pixel of R is laminated, the resist pattern of the sub-pixel of R is used as a mask to etch the uppermost transparent electrode layer, and the resist pattern of the sub-pixel of G is exposed. In this case, R and G are used. The resist pattern of the sub-pixels is a mask, and the second transparent electrode layer is etched from top to bottom.

然後,使B之子像素之抗蝕圖案露出,此時以R、G、B之子像素之抗蝕圖案為遮罩,對最下層之透明電極層進行蝕刻,藉此圖案形成所有透明電極層。 Then, the resist pattern of the sub-pixels of B is exposed. At this time, the resist pattern of the sub-pixels of R, G, and B is used as a mask, and the transparent electrode layer of the lowermost layer is etched to form all the transparent electrode layers.

最後,以R、G、B之子像素之抗蝕圖案為遮罩,對反射電極層進行蝕刻而將其圖案化。 Finally, the resist pattern of the sub-pixels of R, G, and B is used as a mask, and the reflective electrode layer is etched and patterned.

然而,於專利文獻2中,為了於抗蝕圖案上積層透明電極層,若抗蝕劑與透明電極層之密接性不充分,則有於處理中發生透明電極層之膜剝落,而導致圖案不良或步驟污染之危險性。 However, in Patent Document 2, in order to laminate a transparent electrode layer on a resist pattern, if the adhesion between the resist and the transparent electrode layer is insufficient, film peeling of the transparent electrode layer occurs during the process, resulting in poor pattern. Or the danger of step contamination.

又,當將積層有抗蝕劑之基板投入於濺鍍裝置內時,有垃圾等異物附著,而良率降低之虞,並且有引起缺陷或膜厚不均、膜質不均(光學性質之面內分佈)之可能性。 In addition, when a substrate in which a resist is laminated is placed in a sputtering apparatus, foreign matter such as garbage adheres, and the yield is lowered, and defects or film thickness unevenness and film quality unevenness (optical properties) are caused. The possibility of distribution within.

又,如專利文獻2中記載般,於在抗蝕圖案上積層透明電極之情形時,若抗蝕圖案之厚度較厚,則有成為抗蝕圖案之暗影之部分變大,而於該成為暗影之部分透明電極層中產生缺陷,或產生膜厚不均之虞。因此,難以將透明電極層設定為最適於各色之子像素之膜厚,且無法以高精細之圖案形成子像素。 Further, as described in Patent Document 2, when a transparent electrode is laminated on a resist pattern, if the thickness of the resist pattern is thick, the portion of the shadow of the resist pattern becomes large, and the shadow is formed. A defect occurs in a part of the transparent electrode layer, or a film thickness unevenness is generated. Therefore, it is difficult to set the transparent electrode layer to be the film thickness suitable for the sub-pixels of the respective colors, and it is not possible to form the sub-pixels in a high-definition pattern.

因此,若僅單純地積層透明電極層,則難以針對各色之每一子像素變更透明電極之膜厚。 Therefore, if only the transparent electrode layer is simply laminated, it is difficult to change the film thickness of the transparent electrode for each sub-pixel of each color.

作為針對各色之每一子像素變更透明電極之膜厚之方法,考慮例如以下之方法。 As a method of changing the film thickness of the transparent electrode for each sub-pixel of each color, for example, the following method is considered.

圖13(a)~(f)係按步驟表示針對每一子像素,變更陽極之反射電極層上之透明電極層之膜厚之方法之一例的剖面圖。 13(a) to (f) are cross-sectional views showing, in order, an example of a method of changing the film thickness of the transparent electrode layer on the reflective electrode layer of the anode for each sub-pixel.

以下,參照圖13(a)~(f),對如上述般針對每一子像素,變更陽極之反射電極層上之透明電極層之膜厚之方法進行說明。 Hereinafter, a method of changing the film thickness of the transparent electrode layer on the reflective electrode layer of the anode for each sub-pixel as described above will be described with reference to FIGS. 13(a) to 13(f).

首先,如圖13(a)所示,利用濺鍍法等於支撐基板301上成膜含有銀(Ag)等反射電極材料之反射電極層302。 First, as shown in FIG. 13(a), a reflective electrode layer 302 containing a reflective electrode material such as silver (Ag) is formed on the support substrate 301 by sputtering.

繼而,針對各色之每一子像素,藉由光微影術於上述反射電極層302上形成未圖示之抗蝕圖案,將該等抗蝕圖案作為遮罩而對反射電極層302進行蝕刻之後,藉由抗蝕劑剝離液而剝離清洗該等抗蝕圖案。 Then, for each sub-pixel of each color, a resist pattern (not shown) is formed on the reflective electrode layer 302 by photolithography, and the reflective electrode layer 302 is etched by using the resist pattern as a mask. The resist patterns are peeled off by the resist stripping solution.

藉此,如圖13(b)所示,以針對各色之每一子像素將反射電極層302分離之方式進行圖案化。 Thereby, as shown in FIG. 13(b), the reflective electrode layer 302 is patterned for each sub-pixel of each color.

繼而,如圖13(c)所示,於反射電極層302上成膜例如IZO(Indium Zinc Oxide:氧化銦鋅)而形成IZO層303作為透明電極層,藉由光微影術,僅於R之子像素形成抗蝕劑311。 Then, as shown in FIG. 13(c), for example, IZO (Indium Zinc Oxide) is formed on the reflective electrode layer 302 to form the IZO layer 303 as a transparent electrode layer, and by photolithography, only R The sub-pixels form a resist 311.

繼而,如圖13(d)所示,藉由草酸,對露出之IZO層303進行蝕刻而將其去除之後,將抗蝕劑311剝離,藉此僅於R 之子像素形成經圖案化之IZO層303作為第1 IZO層。 Then, as shown in FIG. 13(d), the exposed IZO layer 303 is etched by oxalic acid to remove it, and then the resist 311 is peeled off, thereby only R The sub-pixels form the patterned IZO layer 303 as the first IZO layer.

然後,如圖13(e)所示,以覆蓋R之子像素之IZO層303以及G及B之子像素之反射電極層302之方式再次成膜IZO而形成IZO層304,進而,藉由光微影術,僅於R及G之子像素形成抗蝕劑312。 Then, as shown in FIG. 13(e), IZO is formed again by covering the IZO layer 303 of the sub-pixels of R and the reflective electrode layer 302 of the sub-pixels of G and B to form the IZO layer 304, and further, by photolithography The resist 312 is formed only on the sub-pixels of R and G.

然後,如圖13(f)所示,將抗蝕劑312作為遮罩而藉由草酸對IZO層304進行蝕刻,並將抗蝕劑312剝離,藉此於子像素R及G形成經圖案化之IZO層304作為第2 IZO層。 Then, as shown in FIG. 13(f), the IZO layer 304 is etched by oxalic acid using the resist 312 as a mask, and the resist 312 is peeled off, thereby forming patterned patterns on the sub-pixels R and G. The IZO layer 304 serves as a second IZO layer.

如此般,若為了獲得微空腔效應,而針對每一子像素改變透明電極層之積層數,則於例如子像素包含R、G、B之子像素之情形時,至少需要3次光微影術及蝕刻、抗蝕劑剝離。 In this way, if the number of layers of the transparent electrode layer is changed for each sub-pixel in order to obtain the microcavity effect, at least three times of photolithography is required when, for example, the sub-pixel includes sub-pixels of R, G, and B. And etching, resist stripping.

換言之,為了針對每一子像素變更陽極之反射電極層上之透明電極層之膜厚,如圖13之(a)~(f)所示,需要3次光微影術。再者,若包含反射電極層之圖案化,則需要4次光微影術。又,於圖13(f)中,於對B之像素進而形成透明電極層之情形時,需要更多1次光微影術。 In other words, in order to change the film thickness of the transparent electrode layer on the reflective electrode layer of the anode for each sub-pixel, as shown in (a) to (f) of FIG. 13, three times of photolithography is required. Furthermore, if the patterning of the reflective electrode layer is included, four photolithography is required. Further, in Fig. 13 (f), in the case where the pixel of B is further formed into a transparent electrode layer, more photolithography is required.

因此,如上述般,若為了獲得微空腔效應,使用同一材料之透明電極層而針對每一子像素改變電極之厚度,則需要用以進行至少3次(若包含用以反射電極層之圖案化之光微影術,則為至少4次)光微影術及蝕刻、抗蝕劑剝離之裝置。因此,製造線上所需之用以進行上述處理之光微影術裝置(黃光製程(photo process)裝置)之數量變多。 Therefore, as described above, if the thickness of the electrode is changed for each sub-pixel using a transparent electrode layer of the same material in order to obtain a microcavity effect, it is necessary to perform at least 3 times (if a pattern for reflecting the electrode layer is included) Huaguang lithography, at least 4 times) photolithography and etching, resist stripping device. Therefore, the number of photolithography apparatuses (photo process apparatuses) required for the above processing required on the manufacturing line is increased.

於光微影術中,需要高價之裝置或材料。因此,若如上 述般針對每一子像素改變電極之厚度,則導致整個裝置之成本提高及佔據面積增加。 In photolithography, expensive devices or materials are required. Therefore, if above Changing the thickness of the electrode for each sub-pixel generally results in an increase in cost and an increase in footprint of the entire device.

進而,由於光微影術需要進行固定時間之顯影處理或烘烤處理等,故難以縮短處理節拍。 Further, since photolithography requires development processing or baking treatment for a fixed period of time, it is difficult to shorten the processing tempo.

因此,理想的是使光微影術之次數儘可能地少。 Therefore, it is desirable to make the number of photolithography as small as possible.

又,於如上述般重複進行抗蝕劑之剝離及烘烤之情形時,若上述重複次數變多,則反射電極層之表面粗糙或發生氧化而反射效率降低。又,有因反射電極之表面粗糙而發生電極間漏電,而導致像素缺陷之虞。 Further, when the resist is peeled off and baked as described above, when the number of repetitions is increased, the surface of the reflective electrode layer is rough or oxidized, and the reflection efficiency is lowered. Further, there is a problem that pixel leakage occurs due to surface roughness of the reflective electrode and leakage between the electrodes.

又,根據反射電極材料之種類,若上述反射電極層處於暴露狀態(即露出狀態),則有當例如為了提高抗蝕劑之濕潤性而進行紫外線照射時發生氧化而反射特性降低,或耐溶劑性較低而溶劑滲入之可能性。因此,於如上所述之反射電極層含有如上所述之反射電極材料之情形時,不理想的是反射電極層成為暴露狀態。 Further, depending on the type of the reflective electrode material, when the reflective electrode layer is in an exposed state (that is, in an exposed state), for example, when ultraviolet light is irradiated to improve the wettability of the resist, oxidation occurs, and reflection characteristics are lowered, or solvent resistance is caused. The possibility of low solubility and solvent penetration. Therefore, in the case where the reflective electrode layer as described above contains the reflective electrode material as described above, it is not preferable that the reflective electrode layer is in an exposed state.

因此,若欲於各子像素之反射電極層上積層透明電極層,則為此需要光微影術,從而光微影術之次數進一步增加。 Therefore, if a transparent electrode layer is to be laminated on the reflective electrode layer of each sub-pixel, photolithography is required for this, and the number of photolithography is further increased.

再者,於專利文獻3中揭示有如下之方法:藉由積層結晶性不同之ITO,而於經圖案化之反射電極層上成膜具有結晶性之ITO並將其圖案化之後,積層非晶質之ITO,藉此利用2次光微影術針對每一子像素變更透明電極層之膜厚。即,於專利文獻3中,若包含反射電極層之圖案化,則光微影術之次數為3次。 Further, Patent Document 3 discloses a method of forming a crystalline amorphous ITO on a patterned reflective electrode layer by patterning and forming a patterned amorphous reflective layer. The ITO of the quality is used to change the film thickness of the transparent electrode layer for each sub-pixel by secondary photolithography. That is, in Patent Document 3, when the patterning of the reflective electrode layer is included, the number of photolithography is three times.

然而,於專利文獻3中,於第1及第3子像素成膜具有結晶性之ITO並將其圖案化之後,於第1子像素與第2子像素積層非晶質之ITO並將其圖案化,藉此針對每一子像素變更透明電極層之膜厚。 However, in Patent Document 3, after the crystalline ITO is formed in the first and third sub-pixels and patterned, the amorphous ITO is laminated on the first sub-pixel and the second sub-pixel and patterned. Thereby, the film thickness of the transparent electrode layer is changed for each sub-pixel.

即,專利文獻3係每當光微影術時於2個子像素形成相同膜厚之透明電極層之圖案,針對每次光微影術變更形成透明電極層之圖案之子像素,藉此減少光微影術之次數,因此,對具有結晶性之ITO進行蝕刻而於2個子像素形成相同膜厚之透明電極層之圖案。 That is, Patent Document 3 forms a pattern of a transparent electrode layer having the same film thickness in two sub-pixels every time the photolithography is performed, and changes the sub-pixels forming the pattern of the transparent electrode layer for each photolithography, thereby reducing the light micro-pattern. Since the number of times of shadowing is performed, the crystalline ITO is etched to form a pattern of transparent electrode layers having the same film thickness in two sub-pixels.

因此,於專利文獻3中,利用2個透明電極層之膜厚之組合而決定各子像素之光徑長。因此,光徑長之設定存在制約,而難以任意地變更光徑長。 Therefore, in Patent Document 3, the optical path length of each sub-pixel is determined by the combination of the film thicknesses of the two transparent electrode layers. Therefore, there is a restriction on the setting of the optical path length, and it is difficult to arbitrarily change the optical path length.

本發明係鑒於上述問題點而完成,本發明之目的在於提供一種於各子像素中之反射電極層上積層有透明電極層,並且可於顯示色不同之子像素間任意地變更反射電極層上之透明電極層之膜厚之實用之顯示裝置之製造方法,並且削減光微影術之次數。又,本發明之進一步之目的在於提供一種針對顯示色不同之每一子像素而透明電極層之膜厚不同,並且可利用實用之方法製造之顯示裝置。 The present invention has been made in view of the above problems, and an object of the present invention is to provide a transparent electrode layer laminated on a reflective electrode layer in each sub-pixel, and to arbitrarily change a reflective electrode layer between sub-pixels having different display colors. A method of manufacturing a practical display device for film thickness of a transparent electrode layer, and reducing the number of photolithography. Further, it is a further object of the present invention to provide a display device which can be manufactured by a practical method with respect to a film thickness of a transparent electrode layer for each sub-pixel having a different display color.

為了解決上述課題,本發明之顯示裝置之製造方法之特徵在於:該顯示裝置中各子像素中之形成電場之成對電極中,一個電極包含反射電極層及形成於該反射電極層上之至少一層透明電極層,並且於至少1個子像素中之反射電 極層上形成有複數層上述透明電極層,於顯示色不同之子像素間上述透明電極層之整體之膜厚不同,該顯示裝置之製造方法包含如下步驟:成膜反射電極層;第1透明電極層成膜步驟,其係於上述反射電極層之上層成膜含有非晶質之透明電極材料之第1透明電極層;圖案化步驟,其係藉由光微影術對上述含有非晶質之透明電極材料之第1透明電極層及上述反射電極層統括地進行蝕刻而將其等圖案化;第1透明電極層結晶化步驟,其係使上述圖案化步驟中進行圖案化所得之上述含有非晶質之透明電極材料之第1透明電極層結晶化而將其轉化為含有多晶之透明電極材料之第1透明電極層;及第2透明電極層積層步驟,其係於上述含有多晶之透明電極材料之第1透明電極層上,成膜含有耐蝕刻性低於上述含有多晶之透明電極材料之第1透明電極層之透明電極材料的第2透明電極層,藉由光微影術選擇性地對上述第2透明電極層進行蝕刻而將其圖案化。 In order to solve the above problems, a method of manufacturing a display device according to the present invention is characterized in that, among the pair of electrodes forming an electric field in each sub-pixel of the display device, one of the electrodes includes a reflective electrode layer and at least a reflective electrode layer formed thereon a transparent electrode layer and reflected in at least one sub-pixel a plurality of layers of the transparent electrode layer are formed on the electrode layer, and the film thickness of the transparent electrode layer is different between sub-pixels having different display colors. The method for manufacturing the display device comprises the steps of: forming a reflective electrode layer; and forming a first transparent electrode a layer forming step of forming a first transparent electrode layer containing an amorphous transparent electrode material on the upper surface of the reflective electrode layer; and a patterning step of the amorphous layer by photolithography The first transparent electrode layer and the reflective electrode layer of the transparent electrode material are collectively etched and patterned, and the first transparent electrode layer crystallization step is performed by patterning the patterning step. a first transparent electrode layer in which a first transparent electrode layer of a crystalline transparent electrode material is crystallized and converted into a polycrystalline transparent electrode material; and a second transparent electrode layer lamination step is performed on the polycrystalline layer containing On the first transparent electrode layer of the transparent electrode material, the second transparent electrode material containing the first transparent electrode layer having a lower etching resistance than the polycrystalline transparent electrode material is formed. The transparent electrode layer is selectively patterned by photolithography to etch the second transparent electrode layer.

如上所述,根據本發明,於反射電極層之上層成膜含有非晶質之透明電極材料之第1透明電極層,對上述反射電極層及含有非晶質之透明電極材料之第1透明電極層統括地進行蝕刻,藉此,不會增加光微影術之次數,且可於上述反射電極層上,積層上述含有多晶之透明電極材料之第1透明電極層。 As described above, according to the present invention, the first transparent electrode layer containing the amorphous transparent electrode material is formed on the upper surface of the reflective electrode layer, and the reflective electrode layer and the first transparent electrode containing the amorphous transparent electrode material are formed. The layers are collectively etched, whereby the first transparent electrode layer containing the polycrystalline transparent electrode material may be laminated on the reflective electrode layer without increasing the number of photolithography.

又,根據上述方法,將含有非晶質之透明電極材料之第1透明電極層轉化為含有多晶之透明電極材料之第1透明電 極層,利用其與成膜於其之上方之第2透明電極層之耐蝕刻性之差異而積層透明電極層。 Further, according to the above method, the first transparent electrode layer containing the amorphous transparent electrode material is converted into the first transparent electric material containing the polycrystalline transparent electrode material. In the electrode layer, the transparent electrode layer is laminated by the difference in etching resistance between the second transparent electrode layer formed thereon and the second transparent electrode layer formed thereon.

根據上述方法,藉由如此般於上述第2透明電極層之下層積層有耐蝕刻性高於上述第2透明電極層之含有多晶之透明電極材料的第1透明電極層,而當對成為上層之第2透明電極層進行蝕刻時,下層之第1透明電極層不被蝕刻。 而且,根據上述方法,藉由成膜上述第2透明電極層之前,於各子像素積層有上述含有多晶之透明電極材料之第1透明電極層,可於任意之子像素積層上述第2透明電極層。 According to the above method, the first transparent electrode layer having a polycrystalline transparent electrode material having higher etching resistance than the second transparent electrode layer is laminated under the second transparent electrode layer, and the upper layer is formed as an upper layer. When the second transparent electrode layer is etched, the lower first transparent electrode layer is not etched. Further, according to the above method, before the second transparent electrode layer is formed, the first transparent electrode layer containing the polycrystalline transparent electrode material is laminated on each sub-pixel, and the second transparent electrode can be laminated in any sub-pixel. Floor.

因此,根據上述方法,於各子像素之反射電極層上形成有透明電極層,並且作為為了變更各子像素中之透明電極層之合計膜厚而所需之光微影術之次數,可利用2次光微影術而針對每一子像素任意地變更上述透明電極層之合計膜厚。又,根據上述方法,即便包含反射電極層之蝕刻,亦可將光微影術之次數抑制為3次。 Therefore, according to the above method, the transparent electrode layer is formed on the reflective electrode layer of each sub-pixel, and the number of photolithography required to change the total film thickness of the transparent electrode layers in each sub-pixel can be utilized. The total film thickness of the transparent electrode layer is arbitrarily changed for each sub-pixel by secondary photolithography. Further, according to the above method, even if the etching of the reflective electrode layer is included, the number of photolithography can be suppressed to three times.

因此,根據上述方法,即便如上述般減少了光微影術之次數,亦可使任意之子像素中之第2透明電極層之膜厚獨立於其他子像素中之第2透明電極層之膜厚而設定。 Therefore, according to the above method, even if the number of photolithography is reduced as described above, the film thickness of the second transparent electrode layer in any of the sub-pixels can be made independent of the film thickness of the second transparent electrode layer in the other sub-pixels. And set.

即,即便不如專利文獻3般,為了堆積透明電極層而另外成膜具有結晶性之ITO層並將其圖案化,並且每當光微影術時於2個子像素形成相同膜厚之透明電極層之圖案,亦可利用2次光微影術而於各子像素之反射電極層上形成透明電極層,並且可針對顯示色不同之每一子像素而形成 上述反射電極層上之透明電極層之合計膜厚不同之電極。 That is, even if it is not as in the case of the patent document 3, in order to deposit a transparent electrode layer, a crystalline ITO layer is formed and patterned, and a transparent electrode layer of the same film thickness is formed in two sub-pixels every time photomicrography. The pattern can also form a transparent electrode layer on the reflective electrode layer of each sub-pixel by using 2 times photolithography, and can be formed for each sub-pixel having different display colors. An electrode having a total thickness of the transparent electrode layers on the reflective electrode layer.

因此,根據上述方法,可任意且容易地調整各子像素中之光徑長,而不會如專利文獻3般受光徑長之制約。因此,根據上述方法,可利用次數少於先前之光微影術,針對顯示色不同之子像素而任意地變更反射電極層上之透明電極層之膜厚。 Therefore, according to the above method, the optical path length in each sub-pixel can be arbitrarily and easily adjusted without being restricted by the optical path length as in Patent Document 3. Therefore, according to the above method, the film thickness of the transparent electrode layer on the reflective electrode layer can be arbitrarily changed for the sub-pixels having different display colors by using less than the previous photolithography.

其結果,可實現較先前成本降低及佔據面積減少。 As a result, a reduction in cost and a reduction in occupied area can be achieved.

又,於先前之方法中,由於抗蝕劑之剝離及烘烤步驟變多,故有反射電極層之表面粗糙或發生氧化而反射效率降低,或者因反射電極層之表面粗糙而發生電極間漏電而導致像素缺陷之虞。 Further, in the prior method, since the peeling and baking steps of the resist are increased, the surface of the reflective electrode layer is rough or oxidized to lower the reflection efficiency, or leakage between the electrodes occurs due to the surface roughness of the reflective electrode layer. The result is a flaw in pixel defects.

然而,根據上述方法,由於可使曝光、顯影、抗蝕劑剝離處理等之次數減少,故不存在如上所述之擔憂。又,可縮短處理節拍。 However, according to the above method, since the number of times of exposure, development, resist stripping treatment, and the like can be reduced, there is no fear as described above. Also, the processing beat can be shortened.

又,根據反射電極材料之種類,若上述反射電極層處於暴露狀態(即露出狀態),則有當例如為了提高抗蝕劑之濕潤性而進行紫外線照射時發生氧化而反射特性降低,或耐溶劑性較低而溶劑滲入之可能性。因此,於如上所述之反射電極層含有如上所述之反射電極材料之情形時,不理想的是反射電極層成為暴露狀態。 Further, depending on the type of the reflective electrode material, when the reflective electrode layer is in an exposed state (that is, in an exposed state), for example, when ultraviolet light is irradiated to improve the wettability of the resist, oxidation occurs, and reflection characteristics are lowered, or solvent resistance is caused. The possibility of low solubility and solvent penetration. Therefore, in the case where the reflective electrode layer as described above contains the reflective electrode material as described above, it is not preferable that the reflective electrode layer is in an exposed state.

然而,根據上述方法,藉由於製造步驟中之早期階段,如上述般於各子像素中之反射電極層上形成上述多晶之透明電極層,可保護上述反射電極層免受有損壞該反射電極層之品質之虞之上述要因的影響。 However, according to the above method, by forming the polycrystalline transparent electrode layer on the reflective electrode layer in each sub-pixel as described above in the early stage of the manufacturing step, the reflective electrode layer can be protected from damage to the reflective electrode. The influence of the above factors on the quality of the layer.

又,於專利文獻3中,將反射電極層圖案化之後,於第1及第3子像素成膜具有結晶性之ITO並將其圖案化。 Further, in Patent Document 3, after patterning the reflective electrode layer, crystalline ITO is formed on the first and third sub-pixels and patterned.

具有結晶性之ITO相對於反射電極層之蝕刻中使用之蝕刻液之溶解性較高。因此,當於反射電極層上直接成膜具有結晶性之ITO層並藉由光微影術而將其圖案化時,有反射電極層不為錐狀之虞。 The solubility of the crystalline ITO with respect to the etching liquid used for etching the reflective electrode layer is high. Therefore, when a crystalline ITO layer is directly formed on the reflective electrode layer and patterned by photolithography, the reflective electrode layer is not tapered.

然而,根據上述方法,成膜含有非晶質之透明電極材料之第1透明電極層,並將其與反射電極層一併圖案化之後,將其轉化為多晶之透明電極層,藉此,亦不會產生如上所述之問題。 However, according to the above method, the first transparent electrode layer containing the amorphous transparent electrode material is formed and patterned together with the reflective electrode layer, and then converted into a polycrystalline transparent electrode layer, whereby Nor will it cause the problems described above.

如此,根據上述方法,提供一種於各子像素中之反射電極層上積層有透明電極層,並且可於顯示色不同之子像素間任意地變更反射電極層上之透明電極層之膜厚之實用之顯示裝置之製造方法,並且可削減光微影術之次數。 According to the above method, it is possible to provide a transparent electrode layer on the reflective electrode layer in each sub-pixel, and to arbitrarily change the film thickness of the transparent electrode layer on the reflective electrode layer between sub-pixels having different display colors. The manufacturing method of the display device and the number of times of photolithography can be reduced.

又,為了解決上述課題,本發明之顯示裝置之特徵在於:各子像素中之形成電場之成對電極中,一個電極包含反射電極層及形成於該反射電極層上之至少一層透明電極層,並且於至少1個子像素中之反射電極層上形成有複數層上述透明電極層,於顯示色不同之子像素間上述透明電極層之整體之膜厚不同,上述複數之透明電極層具有互不相同之組成,下層之透明電極層之耐蝕刻性高於上層之透明電極層之耐蝕刻性。 Further, in order to solve the above problems, a display device according to the present invention is characterized in that, among the pair of electrodes forming an electric field in each sub-pixel, one of the electrodes includes a reflective electrode layer and at least one transparent electrode layer formed on the reflective electrode layer. Further, a plurality of the transparent electrode layers are formed on the reflective electrode layer of at least one of the sub-pixels, and the thickness of the transparent electrode layer is different between the sub-pixels having different display colors, and the plurality of transparent electrode layers are different from each other. The etch resistance of the lower transparent electrode layer is higher than that of the upper transparent electrode layer.

如上所述之顯示裝置可不將含有非結晶之透明電極材料之透明電極層轉化為含有多晶之透明電極材料之透明電極 層,而利用下層之透明電極層與上層之透明電極層之耐蝕刻性之差異所致之蝕刻選擇性之差異,進行透明電極層之堆積。 The display device as described above may not convert a transparent electrode layer containing an amorphous transparent electrode material into a transparent electrode containing a polycrystalline transparent electrode material. In the layer, the deposition of the transparent electrode layer is performed by utilizing the difference in etching selectivity due to the difference in etching resistance between the transparent electrode layer of the lower layer and the transparent electrode layer of the upper layer.

因此,與如先前般堆積含有相同之透明電極材料之透明電極層之情形相比,可以較短之處理節拍任意且容易地調整各子像素中之光徑長。 Therefore, the optical path length in each sub-pixel can be arbitrarily and easily adjusted in a shorter processing tempo than in the case where the transparent electrode layer containing the same transparent electrode material is stacked as before.

因此,根據本發明,可提供一種針對顯示色不同之每一子像素而透明電極層之膜厚不同並且可利用實用之方法製造之顯示裝置。 Therefore, according to the present invention, it is possible to provide a display device in which the thickness of the transparent electrode layer is different for each sub-pixel having a different display color and can be manufactured by a practical method.

如上所述,於本發明之顯示裝置之製造方法中,於反射電極層之上層成膜含有非晶質之透明電極材料之第1透明電極層,對上述反射電極層及含有非晶質之透明電極材料之第1透明電極層統括地進行蝕刻。 As described above, in the method of manufacturing a display device of the present invention, the first transparent electrode layer containing an amorphous transparent electrode material is formed on the upper surface of the reflective electrode layer, and the reflective electrode layer and the amorphous layer are transparent. The first transparent electrode layer of the electrode material is collectively etched.

因此,根據上述製造方法,不會增加光微影術之次數,且可於上述反射電極層上積層上述含有多晶之透明電極材料之第1透明電極層。 Therefore, according to the above manufacturing method, the first transparent electrode layer containing the polycrystalline transparent electrode material can be laminated on the reflective electrode layer without increasing the number of photolithography.

又,於本發明之顯示裝置之製造方法中,將含有非晶質之透明電極材料之第1透明電極層轉化為含有多晶之透明電極材料之第1透明電極層,利用其與成膜於其之上方之第2透明電極層之耐蝕刻性之差異而積層透明電極層。 Further, in the method of manufacturing a display device of the present invention, the first transparent electrode layer containing an amorphous transparent electrode material is converted into a first transparent electrode layer containing a polycrystalline transparent electrode material, and is formed and formed thereon. A transparent electrode layer is laminated on the difference in etching resistance of the second transparent electrode layer above it.

根據上述製造方法,藉由如此般於上述第2透明電極層之下層積層有耐蝕刻性高於上述第2透明電極層之含有多晶之透明電極材料的第1透明電極層,而當對成為上層之 第2透明電極層進行蝕刻時,下層之第1透明電極層不被蝕刻。而且,根據上述製造方法,於成膜上述第2透明電極層之前,於各子像素積層有上述含有多晶之透明電極材料之第1透明電極層,藉此,可於任意之子像素積層上述第2透明電極層。 According to the above manufacturing method, the first transparent electrode layer containing the polycrystalline transparent electrode material having higher etching resistance than the second transparent electrode layer is laminated under the second transparent electrode layer as described above. Upper layer When the second transparent electrode layer is etched, the lower first transparent electrode layer is not etched. Further, according to the above manufacturing method, the first transparent electrode layer containing the polycrystalline transparent electrode material is laminated in each sub-pixel before the formation of the second transparent electrode layer, whereby the above-described first sub-pixel can be laminated 2 transparent electrode layer.

因此,根據上述製造方法,於各子像素之反射電極層上形成有透明電極層,並且作為為了變更各子像素中之透明電極層之合計膜厚而所需之光微影術之次數,可利用2次光微影術,針對每一子像素任意地變更上述透明電極層之合計膜厚。又,根據上述製造方法,即便包含反射電極層之蝕刻,亦可將光微影術之次數抑制為3次。 Therefore, according to the above manufacturing method, the transparent electrode layer is formed on the reflective electrode layer of each sub-pixel, and the number of photolithography required to change the total film thickness of the transparent electrode layer in each sub-pixel can be The total film thickness of the transparent electrode layer was arbitrarily changed for each sub-pixel by secondary photolithography. Further, according to the above production method, even if the etching of the reflective electrode layer is included, the number of photolithography can be suppressed to three times.

因此,根據上述製造方法,即便如上述般減少了光微影術之次數,亦可使任意之子像素中之第2透明電極層之膜厚獨立於其他子像素中之第2透明電極層之膜厚而設定。 Therefore, according to the above manufacturing method, even if the number of photolithography is reduced as described above, the film thickness of the second transparent electrode layer in any of the sub-pixels can be made independent of the film of the second transparent electrode layer among the other sub-pixels. Thick and set.

因此,根據上述製造方法,可任意且容易地調整各子像素中之光徑長,而不會如專利文獻3般受光徑長之制約。因此,根據上述製造方法,可利用次數少於先前之光微影術,針對顯示色不同之每一子像素任意地變更反射電極層上之透明電極層之膜厚。 Therefore, according to the above-described manufacturing method, the optical path length in each sub-pixel can be arbitrarily and easily adjusted without being restricted by the optical path length as in Patent Document 3. Therefore, according to the above-described manufacturing method, the film thickness of the transparent electrode layer on the reflective electrode layer can be arbitrarily changed for each sub-pixel having a different display color than the previous photolithography.

又,如上所述,本發明之顯示裝置係於反射電極層上設置有複數之透明電極層,且針對顯示色不同之每一子像素而上述透明電極層之整體之膜厚不同者,上述複數之透明電極層具有互不相同之組成,下層之透明電極層之耐蝕刻性高於上層之透明電極層之耐蝕刻性。 Further, as described above, the display device of the present invention is characterized in that a plurality of transparent electrode layers are provided on the reflective electrode layer, and the film thickness of the entire transparent electrode layer is different for each sub-pixel having a different display color. The transparent electrode layers have mutually different compositions, and the etching resistance of the lower transparent electrode layer is higher than that of the upper transparent electrode layer.

如上所述之顯示裝置可不將含有非結晶之透明電極材料之透明電極層轉化為含有多晶之透明電極材料之透明電極層,而利用下層之透明電極層與上層之透明電極層之耐蝕刻性之差異所致之蝕刻選擇性之差異,進行透明電極層之堆積。 The display device as described above can convert the transparent electrode layer containing the amorphous transparent electrode material into the transparent electrode layer containing the polycrystalline transparent electrode material, and utilize the etching resistance of the lower transparent electrode layer and the upper transparent electrode layer. The difference in etching selectivity due to the difference is caused by the deposition of the transparent electrode layer.

因此,與如先前般堆積含有相同之透明電極材料之透明電極層之情形相比,可以較短之處理節拍任意且容易地調整各子像素中之光徑長。 Therefore, the optical path length in each sub-pixel can be arbitrarily and easily adjusted in a shorter processing tempo than in the case where the transparent electrode layer containing the same transparent electrode material is stacked as before.

因此,根據本發明,可提供一種針對顯示色不同之每一子像素而透明電極層之膜厚不同並且可利用實用之方法製造之顯示裝置。 Therefore, according to the present invention, it is possible to provide a display device in which the thickness of the transparent electrode layer is different for each sub-pixel having a different display color and can be manufactured by a practical method.

以下,對本發明之一實施形態進行詳細說明。 Hereinafter, an embodiment of the present invention will be described in detail.

[實施形態1] [Embodiment 1]

若根據圖1(a)~(i)至圖9(a).(b)對本實施形態進行說明,則如下所述。 According to Figure 1 (a) ~ (i) to Figure 9 (a). (b) The present embodiment will be described below.

<有機EL顯示裝置之概略構成> <Schematic Configuration of Organic EL Display Device>

首先,對有機EL顯示裝置之概略構成進行說明。 First, a schematic configuration of an organic EL display device will be described.

圖2係表示本實施形態之有機EL顯示裝置100之主要部分之概略構成的分解剖面圖。 FIG. 2 is an exploded cross-sectional view showing a schematic configuration of a main part of the organic EL display device 100 of the present embodiment.

如圖2所示,本實施形態之有機EL顯示裝置100包含像素部101與電路部102。 As shown in FIG. 2, the organic EL display device 100 of the present embodiment includes a pixel portion 101 and a circuit portion 102.

像素部101包含有機EL顯示面板1(顯示面板)。又,電路部102包含設置有驅動有機EL顯示裝置100之驅動電路等之 電路基板或IC(積體電路:Integrated Circuits)晶片等。 The pixel portion 101 includes an organic EL display panel 1 (display panel). Further, the circuit unit 102 includes a drive circuit or the like that drives the organic EL display device 100. A circuit board or an IC (Integrated Circuits) wafer or the like.

有機EL顯示面板1具有於支撐基板10(被成膜基板、TFT基板)上依序設置有有機EL元件20及密封樹脂層41、填充樹脂層42、密封基板50之構成。 The organic EL display panel 1 has a configuration in which the organic EL element 20, the sealing resin layer 41, the filling resin layer 42, and the sealing substrate 50 are sequentially provided on the support substrate 10 (film formation substrate, TFT substrate).

支撐基板10包含TFT基板等半導體基板,具有於例如絕緣基板11上設置有TFT(薄膜電晶體:Thin Film Transistor)12(參照圖5)等作為主動元件(驅動元件)之構成。 The support substrate 10 includes a semiconductor substrate such as a TFT substrate, and has, for example, a TFT (Thin Film Transistor) 12 (see FIG. 5) or the like as an active device (driving element).

有機EL元件20連接於TFT12。於有機EL元件20上形成有含有乾燥劑之具有接著性之填充樹脂層42。構成填充樹脂層42之填充樹脂係填充於由支撐基板10、密封基板50及密封樹脂層41所包圍之空間內。 The organic EL element 20 is connected to the TFT 12. A filling resin layer 42 having an adhesive property containing a desiccant is formed on the organic EL element 20. The filling resin constituting the filled resin layer 42 is filled in a space surrounded by the support substrate 10, the sealing substrate 50, and the sealing resin layer 41.

再者,有機EL顯示裝置100既可為自支撐基板10側射出光之底部發光型,亦可為自密封基板50側射出光之頂部發光型。 In addition, the organic EL display device 100 may be a bottom emission type that emits light from the side of the self-supporting substrate 10 or a top emission type that emits light from the side of the self-sealing substrate 50.

作為支撐基板10及密封基板50中使用之基底基板,可使用例如玻璃或塑膠等。作為一例,可使用例如無鹼玻璃基板等玻璃基板。 As the base substrate used in the support substrate 10 and the sealing substrate 50, for example, glass, plastic, or the like can be used. As an example, a glass substrate such as an alkali-free glass substrate can be used.

然而,並不限定於此,作為不射出光之側之基板,亦可使用金屬板等不透明材料。 However, the present invention is not limited thereto, and an opaque material such as a metal plate may be used as the substrate on the side where the light is not emitted.

於頂部發光型之情形時,作為密封基板50,亦可使用形成有CF(濾光片:Color Filter)層之基板。又,於底部發光型之情形時,亦可於支撐基板10側形成CF層。 In the case of the top emission type, as the sealing substrate 50, a substrate on which a CF (Color Filter) layer is formed may be used. Further, in the case of the bottom emission type, the CF layer may be formed on the side of the support substrate 10.

於如此般併用CF層之情形時,可藉由CF層而對自有機EL元件20射出之光之光譜進行調整。 When the CF layer is used in combination as described above, the spectrum of the light emitted from the organic EL element 20 can be adjusted by the CF layer.

以下,於本實施形態中,列舉有機EL顯示裝置100為頂部發光型之情形為例進行說明。然而,本實施形態並不限定於此,如上所述,亦可為例如底部發光型。 Hereinafter, in the present embodiment, a case where the organic EL display device 100 is of a top emission type will be described as an example. However, the present embodiment is not limited thereto, and may be, for example, a bottom emission type as described above.

如圖2所示,本實施形態之密封基板50具有於例如絕緣基板51上設置有CF層52及BM(黑矩陣:Black Matrix)53(參照圖5)等之構成。 As shown in FIG. 2, the sealing substrate 50 of the present embodiment has a configuration in which, for example, a CF layer 52 and a BM (Black Matrix) 53 (see FIG. 5) are provided on the insulating substrate 51.

有機EL元件20係藉由使積層有該有機EL元件20之支撐基板10經由設置於框狀之密封區域L之密封樹脂層41及填充樹脂層42而與密封基板50貼合,而封入於該等一對基板(支撐基板10、密封基板50)間,以使該有機EL元件20不因水分或氧而受損。 In the organic EL element 20, the support substrate 10 in which the organic EL element 20 is laminated is bonded to the sealing substrate 50 via the sealing resin layer 41 and the filling resin layer 42 provided in the frame-shaped sealing region L, and is sealed in the sealing substrate 50. The pair of substrates (the support substrate 10 and the sealing substrate 50) are disposed such that the organic EL element 20 is not damaged by moisture or oxygen.

有機EL顯示面板1係藉由如此般將有機EL元件20封入於支撐基板10與密封基板50之間,可防止氧或水分自外部滲入有機EL元件20。 In the organic EL display panel 1 , the organic EL element 20 is sealed between the support substrate 10 and the sealing substrate 50 in such a manner as to prevent oxygen or moisture from penetrating into the organic EL element 20 from the outside.

又,於支撐基板10中之框狀之密封區域L之外側設置有形成有電氣配線端子2(電性連接部、連接端子)等之端子部區域R3。 Further, a terminal portion region R3 in which an electric wiring terminal 2 (electrical connection portion, connection terminal) or the like is formed is provided on the outer side of the frame-shaped sealing region L in the support substrate 10.

電氣配線端子2係連接電路部102之連接端子103之連接端子,由金屬等配線材料所形成。 The electric wiring terminal 2 is a connection terminal to which the connection terminal 103 of the circuit portion 102 is connected, and is formed of a wiring material such as metal.

於電路部102設置有例如撓性薄膜電纜(film cable)等配線或驅動器等驅動電路等。 The circuit unit 102 is provided with, for example, a wiring such as a flexible film cable or a drive circuit such as a driver.

如圖2所示,電路部102係經由設置於端子部區域R3之電氣配線端子2而與有機EL顯示面板1連接。 As shown in FIG. 2, the circuit portion 102 is connected to the organic EL display panel 1 via the electric wiring terminal 2 provided in the terminal portion region R3.

<支撐基板10之構成> <Configuration of Support Substrate 10>

此處,以下參照圖3對包含端子部區域R3之支撐基板10中之各區域進行說明。 Here, each region in the support substrate 10 including the terminal portion region R3 will be described below with reference to FIG. 3.

圖3係表示有機EL顯示裝置100中之支撐基板10之概略構成之俯視圖。 FIG. 3 is a plan view showing a schematic configuration of the support substrate 10 in the organic EL display device 100.

如圖3所示,於作為支撐基板10之主動面(主動元件形成面)之一個主面設置有顯示區域R1、第2電極連接區域R2、端子部區域R3及框狀之密封區域L。 As shown in FIG. 3, a display region R1, a second electrode connection region R2, a terminal portion region R3, and a frame-shaped sealing region L are provided on one main surface of the active surface (active element forming surface) of the support substrate 10.

<顯示區域R1> <display area R1>

顯示區域R1(顯示部)設置於支撐基板10之中央部,形成為例如矩形狀。於顯示區域R1形成有包含複數之子像素71(參照圖4及圖5)之像素陣列。再者,以下對顯示區域R1之構成進行詳細敍述。 The display region R1 (display portion) is provided at a central portion of the support substrate 10, and is formed, for example, in a rectangular shape. A pixel array including a plurality of sub-pixels 71 (see FIGS. 4 and 5) is formed in the display region R1. In addition, the configuration of the display region R1 will be described in detail below.

<第2電極連接區域R2> <Second electrode connection region R2>

第2電極連接區域R2係連接有機EL元件20中之第2電極31(參照圖5)之區域。例如,第2電極連接區域R2係於顯示區域R1之2組成對之邊中一組成對之邊之外側,分別沿著對向之邊而形成。 The second electrode connection region R2 is connected to a region of the second electrode 31 (see FIG. 5) of the organic EL element 20. For example, the second electrode connection region R2 is formed on the outer side of the pair of the pair of the pair of the display regions R1, and is formed along the opposite sides.

於該等第2電極連接區域R2分別形成有連接部60(連接電極)。連接部60係連接第2電極31之部分,由金屬材料所形成。 A connection portion 60 (connection electrode) is formed in each of the second electrode connection regions R2. The connecting portion 60 is a portion that connects the second electrode 31 and is formed of a metal material.

<密封區域L> <Sealing area L>

如上所述,於密封區域L形成有用以將支撐基板10與密封基板50貼合之密封樹脂層41。 As described above, the sealing resin layer 41 for bonding the support substrate 10 and the sealing substrate 50 is formed in the sealing region L.

如圖3所示,密封區域L係以包圍顯示區域R1及第2電極 連接區域R2之方式形成為框狀。 As shown in FIG. 3, the sealing region L surrounds the display region R1 and the second electrode. The form of the connection region R2 is formed in a frame shape.

<端子部區域R3> <terminal portion area R3>

如上所述,端子部區域R3係用於像素部101與電路部102之連接之區域。端子部區域R3係於框狀之密封區域L之外側,沿著該框狀之密封區域L而設置。 As described above, the terminal portion region R3 is a region for connecting the pixel portion 101 and the circuit portion 102. The terminal portion region R3 is provided on the outer side of the frame-shaped sealing region L, and is provided along the frame-shaped sealing region L.

具體而言,如圖3所示,端子部區域R3係於各第2電極連接區域R2之外側,沿著各第2電極連接區域R2而形成。又,端子部區域R3係於顯示區域R1中之未設置有上述第2電極連接區域R2之另一組成對之邊之外側,分別沿著對向之邊而形成。 Specifically, as shown in FIG. 3, the terminal portion region R3 is formed on the outer side of each of the second electrode connection regions R2, and is formed along each of the second electrode connection regions R2. Further, the terminal portion region R3 is formed on the outer side of the other side of the display region R1 where the second electrode connection region R2 is not provided, and is formed along the opposite side.

再者,端子部區域R3無需存在於所有邊,例如,亦可僅集中形成於任一邊。 Further, the terminal portion region R3 does not need to exist on all sides, and for example, it may be formed only on one side.

<顯示區域R1之構成> <Configuration of display area R1>

繼而,對顯示區域R1之構成進行說明。 Next, the configuration of the display region R1 will be described.

圖4係表示支撐基板10中之顯示區域R1之主要部分之構成的俯視圖,圖5係表示沿著圖4所示之A-A線切斷有機EL顯示面板1時之有機EL顯示面板1之概略構成的剖面圖。 4 is a plan view showing a configuration of a main portion of the display region R1 in the support substrate 10, and FIG. 5 is a view showing a schematic configuration of the organic EL display panel 1 when the organic EL display panel 1 is cut along the AA line shown in FIG. Sectional view.

如圖4及圖5所示,顯示區域R1係由形成有有機EL元件20之複數之像素70構成。 As shown in FIGS. 4 and 5, the display region R1 is composed of a plurality of pixels 70 in which the organic EL element 20 is formed.

各像素70各自包含複數之子像素71。有機EL顯示裝置100係全彩之主動矩陣型之有機EL顯示裝置,例如如圖5所示,由發出紅(R)色之光之子像素71(以下,記作「子像素71R」)、發出綠(G)色之光之子像素71(以下,記作「子像素71G」)、發出藍(B)色之光之子像素71(以下,記作「子 像素71B」)之3個子像素71R.71G.71B構成1個像素70。 Each of the pixels 70 includes a plurality of sub-pixels 71. The organic EL display device 100 is a full-color active matrix type organic EL display device. For example, as shown in FIG. 5, a sub-pixel 71 (hereinafter referred to as "sub-pixel 71R") that emits red (R) light is emitted. Sub-pixel 71 of green (G) color light (hereinafter referred to as "sub-pixel 71G") and sub-pixel 71 emitting light of blue (B) color (hereinafter, referred to as "sub 3 sub-pixels 71R of the pixel 71B"). 71G. 71B constitutes one pixel 70.

於顯示區域R1中,包含具有該等R、G、B之各色之發光色之有機EL元件20的各色之子像素71呈矩陣狀排列。於本實施形態中,各子像素71R.71G.71B係以如下之方式排列:於支撐基板10之主動面中之X軸方向(橫向)及Y軸方向(縱向)中之一個方向(例如X軸方向)上,相同發光色之子像素71相鄰,於另一個方向(例如Y軸方向)上,不同發光色之子像素71相鄰。 In the display region R1, the sub-pixels 71 of the respective colors including the organic EL elements 20 having the luminescent colors of the respective colors of R, G, and B are arranged in a matrix. In this embodiment, each sub-pixel 71R. 71G. 71B is arranged in such a manner that sub-pixels 71 of the same luminescent color are adjacent to one of the X-axis direction (lateral direction) and the Y-axis direction (longitudinal direction) in the active surface of the support substrate 10 (for example, the X-axis direction). In the other direction (for example, the Y-axis direction), the sub-pixels 71 of different illuminating colors are adjacent.

如圖4及圖5所示,於顯示區域R1中,於X軸方向及Y軸方向上配置有複數之信號線14(配線)。 As shown in FIGS. 4 and 5, in the display region R1, a plurality of signal lines 14 (wiring) are arranged in the X-axis direction and the Y-axis direction.

信號線14包含例如選擇像素之複數根線(閘極線)、寫入資料之複數根線(源極線)、對有機EL元件20供給電力之複數根線(電源線)等。 The signal line 14 includes, for example, a plurality of lines (gate lines) for selecting pixels, a plurality of lines (source lines) for writing data, and a plurality of lines (power lines) for supplying electric power to the organic EL element 20.

再者,閘極線係沿著例如X軸方向敷設,源極線係以與閘極線交叉之方式,沿著例如Y軸方向敷設。 Further, the gate line is laid along the X-axis direction, for example, and the source line is laid along the Y-axis direction so as to intersect the gate line.

又,於閘極線連接有驅動閘極線之未圖示之閘極線驅動電路,於源極線連接有驅動源極線之未圖示之資料線驅動電路。 Further, a gate line driving circuit (not shown) for driving a gate line is connected to the gate line, and a data line driving circuit (not shown) for driving the source line is connected to the source line.

各子像素71排列於由該等信號線14所包圍之區域中。即,由該等信號線14所包圍之區域為1個子像素71,針對每一子像素71,形成有各色之發光區域72。 Each of the sub-pixels 71 is arranged in a region surrounded by the signal lines 14. That is, the area surrounded by the signal lines 14 is one sub-pixel 71, and the light-emitting area 72 of each color is formed for each sub-pixel 71.

該等信號線14係於顯示區域R1外,與電路部102之外部電路連接。藉由自電路部102對信號線14輸入電氣信號,可使配置於信號線14之交叉部之有機EL元件20驅動(發 光)。 The signal lines 14 are connected to the external circuit of the circuit unit 102 outside the display region R1. By inputting an electrical signal to the signal line 14 from the circuit unit 102, the organic EL element 20 disposed at the intersection of the signal line 14 can be driven (transmitted) Light).

於各子像素71R.71G.71B分別設置有連接於有機EL元件20中之第1電極21之TFT12。 In each sub-pixel 71R. 71G. Each of the 71B is provided with a TFT 12 connected to the first electrode 21 of the organic EL element 20.

信號線14連接於設置於該等各子像素71之TFT12。於主動矩陣型之情形時,於各子像素71配置有至少1個TFT12。 The signal line 14 is connected to the TFT 12 provided in each of the sub-pixels 71. In the case of the active matrix type, at least one TFT 12 is disposed in each sub-pixel 71.

再者,亦可進而於各子像素71形成保持所寫入之電壓之電容器或用以補償TFT12之特性變動之補償電路。 Further, a capacitor for holding the written voltage or a compensation circuit for compensating for variations in the characteristics of the TFT 12 may be formed in each of the sub-pixels 71.

各子像素71之發光強度係由信號線14及TFT12之掃描及選擇而決定。有機EL顯示裝置100係使用TFT12,選擇性地使有機EL元件20以所期望之亮度發光,藉此實現圖像顯示。 The light emission intensity of each sub-pixel 71 is determined by scanning and selection of the signal line 14 and the TFT 12. The organic EL display device 100 uses the TFT 12 to selectively cause the organic EL element 20 to emit light at a desired luminance, thereby realizing image display.

<支撐基板10之剖面構成> <Sectional Structure of Support Substrate 10>

如圖4及圖5所示,支撐基板10包含絕緣基板11作為基底基板。 As shown in FIGS. 4 and 5, the support substrate 10 includes an insulating substrate 11 as a base substrate.

如圖5所示,於顯示區域R1中,支撐基板10具有於玻璃基板等透明之絕緣基板11上形成有TFT12(開關元件)及信號線14、層間絕緣膜13(平坦化膜)、邊罩(edge cover)15等之構成。 As shown in FIG. 5, in the display region R1, the support substrate 10 has a TFT 12 (switching element), a signal line 14, an interlayer insulating film 13 (planarizing film), and a side cover formed on a transparent insulating substrate 11 such as a glass substrate. (edge cover) 15 and so on.

於絕緣基板11上設置有信號線14,並且對應於各子像素71R.71G.71B而分別設置有TFT12。再者,先前已熟知TFT之構成。又,TFT12係利用既知之方法而製作。因此,省略TFT12中之各層之圖示以及說明。 A signal line 14 is disposed on the insulating substrate 11 and corresponds to each sub-pixel 71R. 71G. The TFT 12 is provided separately for 71B. Furthermore, the composition of the TFT is well known previously. Further, the TFT 12 is fabricated by a known method. Therefore, the illustration and description of each layer in the TFT 12 are omitted.

層間絕緣膜13係以覆蓋各子像素71R.71G.71B及信號線14之方式,遍及絕緣基板11之整個區域而積層於絕緣基板 11上。 The interlayer insulating film 13 is covered to cover each sub-pixel 71R. 71G. 71B and signal line 14 are laminated on the insulating substrate over the entire area of the insulating substrate 11. 11 on.

於層間絕緣膜13上形成有有機EL元件20中之第1電極21。 The first electrode 21 of the organic EL element 20 is formed on the interlayer insulating film 13.

又,於層間絕緣膜13設置有用以將有機EL元件20中之第1電極21電性連接於TFT12之接觸孔13a。藉此,TFT12係經由接觸孔13a而電性連接於有機EL元件20。 Further, the interlayer insulating film 13 is provided with a contact hole 13a for electrically connecting the first electrode 21 of the organic EL element 20 to the TFT 12. Thereby, the TFT 12 is electrically connected to the organic EL element 20 via the contact hole 13a.

邊罩15係用以防止於第1電極21之端部(圖案端部),因下述之有機EL層43變薄或發生電場集中而有機EL元件20中之第1電極21與第2電極31發生短路的絕緣層(障壁)。 The side cover 15 is used to prevent the first electrode 21 and the second electrode of the organic EL element 20 from being thinned or concentrated by the organic EL layer 43 described later at the end portion (pattern end portion) of the first electrode 21 31 Short-circuited insulation (barrier).

邊罩15係以被覆第1電極21之端部(圖案端部)之方式形成於層間絕緣膜13上。 The side cover 15 is formed on the interlayer insulating film 13 so as to cover the end portion (pattern end portion) of the first electrode 21.

於邊罩15,針對每一子像素71R.71G.71B而設置有開口部15R.15G.15B。藉此,第1電極21係如圖5所示,於不存在邊罩15之部分(開口部15R.15G.15B)露出。該露出部分成為各子像素71R.71G.71B之發光區域72。 In the side cover 15, for each sub-pixel 71R. 71G. 71B is provided with an opening 15R. 15G. 15B. Thereby, as shown in FIG. 5, the first electrode 21 is exposed in a portion (opening portion 15R.15G.15B) where the side cover 15 is not present. The exposed portion becomes each sub-pixel 71R. 71G. Illumination area 72 of 71B.

<有機EL元件20之構成> <Configuration of Organic EL Element 20>

於本實施形態中,藉由使用發光色為白(W)色之發光層,對各子像素71導入微空腔構造,而如上所述,實現全彩之圖像顯示。 In the present embodiment, a microcavity structure is introduced into each sub-pixel 71 by using a light-emitting layer having a white (W) color of luminescent color, and as described above, full-color image display is realized.

此時,藉由如上述般併用CF層52,而可利用CF層52對自有機EL元件20射出之光之光譜進行調整。 At this time, by using the CF layer 52 in combination as described above, the spectrum of the light emitted from the organic EL element 20 can be adjusted by the CF layer 52.

有機EL元件20係可利用低電壓直流驅動進行高亮度發光之發光元件,其依序積層有第1電極21、有機EL層43、第2電極31。 The organic EL element 20 is a light-emitting element that emits high-intensity light by low-voltage direct current driving, and the first electrode 21, the organic EL layer 43, and the second electrode 31 are laminated in this order.

第1電極21係具有對上述有機EL層43注入(供給)電洞之功能之層。第1電極21係經由接觸孔13a而與TFT12連接。 The first electrode 21 has a function of injecting (supplying) a hole into the organic EL layer 43. The first electrode 21 is connected to the TFT 12 via the contact hole 13a.

又,第2電極31係具有對上述有機EL層43注入(供給)電子之功能之層。 Further, the second electrode 31 has a function of injecting (supplying) electrons into the organic EL layer 43.

於如此般組合W發光之發光層與CF層52之情形時,經由載子產生層而積層載子傳輸層(電洞傳輸層、電子傳輸層)及發光層。 When the light-emitting layer of the W light-emitting layer and the CF layer 52 are combined as described above, the carrier transport layer (hole transport layer, electron transport layer) and the light-emitting layer are laminated via the carrier generation layer.

具體而言,於第1電極21與第2電極31之間,如圖5所示,作為有機EL層43,而自第1電極21側起,依序形成有電洞注入層22、電洞傳輸層23、第1發光層24、電子傳輸層25、載子產生層26、電洞傳輸層27、第2發光層28、電子傳輸層29及電子注入層30。再者,第1發光層24及第2發光層28之發光色不同,藉由其等發光色之重合,而獲得W發光。 Specifically, as shown in FIG. 5, the organic EL layer 43 is formed between the first electrode 21 and the second electrode 31, and the hole injection layer 22 and the hole are sequentially formed from the first electrode 21 side. The transport layer 23, the first light-emitting layer 24, the electron transport layer 25, the carrier-generating layer 26, the hole transport layer 27, the second light-emitting layer 28, the electron transport layer 29, and the electron injection layer 30. Further, the first luminescent layer 24 and the second luminescent layer 28 have different luminescent colors, and the luminescent colors are superimposed to obtain W luminescence.

作為上述發光色之組合,可列舉例如藍色光與黃色(更佳為使綠色與紅色具有峰值強度之黃色(橙色))光之組合、藍色光與黃色光之組合等。又,如下所述,於除第1發光層24及第2發光層28以外,亦積層第3發光層,藉此利用3色之發光色之重合而獲得W發光之情形時,作為上述發光色之組合,可列舉紅色光、藍色光、綠色光之組合。 Examples of the combination of the above-described luminescent colors include a combination of blue light and yellow (more preferably yellow (orange) having green and red peak intensity), a combination of blue light and yellow light, and the like. Further, as described below, when the third light-emitting layer is laminated in addition to the first light-emitting layer 24 and the second light-emitting layer 28, when the light emission is obtained by the overlapping of the three color light colors, the light-emitting color is obtained. A combination of red light, blue light, and green light can be cited.

再者,於本實施形態中,形成藍色之發光色之發光層作為第1發光層24,形成橙色之發光色之發光層作為第2發光層28。 Further, in the present embodiment, the light-emitting layer of the blue luminescent color is formed as the first luminescent layer 24, and the luminescent layer of the orange luminescent color is formed as the second luminescent layer 28.

於如此般積層第1發光層24及第2發光層28作為發光層之 情形時,藉由有機EL元件20而獲得對自第1發光層24及第2發光層28射出之光之混合添加微空腔效應所得之光。又,藉由利用設置於密封基板50之CF層52調整上述光,可將具有所期望之光譜之光提取至外部。藉由如此般組合W發光之發光層、微空腔效應及CF層52,可提高色純度。 The first light-emitting layer 24 and the second light-emitting layer 28 are laminated as a light-emitting layer In the case of the organic EL element 20, light obtained by adding a microcavity effect to the mixture of the light emitted from the first light-emitting layer 24 and the second light-emitting layer 28 is obtained. Further, by adjusting the light by the CF layer 52 provided on the sealing substrate 50, light having a desired spectrum can be extracted to the outside. By combining the light-emitting layer of W light, the microcavity effect, and the CF layer 52 in this manner, the color purity can be improved.

電洞注入層22係具有提高自第1電極21向有機EL層43之電洞注入效率之功能之層。另一方面,電子注入層30係具有提高自第2電極31向有機EL層43之電子注入效率之功能之層。 The hole injection layer 22 has a function of increasing the efficiency of injection of holes from the first electrode 21 to the organic EL layer 43. On the other hand, the electron injection layer 30 has a function of increasing the efficiency of electron injection from the second electrode 31 to the organic EL layer 43.

又,電洞傳輸層23係具有提高對於第1發光層24之電洞傳輸效率之功能之層,電洞傳輸層27係具有提高對於第2發光層28之電洞傳輸效率之功能之層。 Further, the hole transport layer 23 has a function of improving the hole transport efficiency of the first light-emitting layer 24, and the hole transport layer 27 has a function of improving the hole transport efficiency of the second light-emitting layer 28.

另一方面,電子傳輸層25係具有提高對於第1發光層24之電子傳輸效率之功能之層,電子傳輸層29係具有提高對於第2發光層28之電子傳輸效率之功能之層。 On the other hand, the electron transport layer 25 has a function of improving the electron transport efficiency of the first light-emitting layer 24, and the electron transport layer 29 has a function of improving the electron transport efficiency of the second light-emitting layer 28.

第1發光層24及第2發光層28分別為具有使自第1電極21側注入之電洞與自第2電極31側注入之電子再結合而射出光之功能之層。第1發光層24及第2發光層28分別由低分子螢光色素、金屬錯合物等發光效率較高之材料所形成。 Each of the first light-emitting layer 24 and the second light-emitting layer 28 has a function of recombining a hole injected from the first electrode 21 side with electrons injected from the second electrode 31 side to emit light. Each of the first light-emitting layer 24 and the second light-emitting layer 28 is formed of a material having high light-emitting efficiency such as a low molecular weight fluorescent dye or a metal complex.

又,載子產生層26係用以對第1發光層24側供給電子,且對第2發光層28側供給電洞之層。 Further, the carrier generating layer 26 is for supplying electrons to the first light-emitting layer 24 side and supplying a layer of holes to the second light-emitting layer 28 side.

即,若將電洞傳輸層、發光層及電子傳輸層考慮為1個單元,則第1發光層24側之單元與第2發光層28側之單元經由載子產生層26而連接。 In other words, when the hole transport layer, the light-emitting layer, and the electron transport layer are considered as one unit, the unit on the first light-emitting layer 24 side and the unit on the second light-emitting layer 28 side are connected via the carrier generation layer 26 .

於如此般組合有W發光之發光層(例如第1發光層24及第2發光層28)與CF層52之有機EL顯示裝置100中,由於利用微空腔效應、CF層52或其他方法而變更各子像素71之發光色,故無需針對每一子像素71分塗發光層。 In the organic EL display device 100 in which the light-emitting layers (for example, the first light-emitting layer 24 and the second light-emitting layer 28) and the CF layer 52 are combined in this manner, the microcavity effect, the CF layer 52, or other methods are utilized. Since the luminescent color of each sub-pixel 71 is changed, it is not necessary to apply a luminescent layer to each sub-pixel 71.

因此,於本實施形態中,如圖5所示,電洞注入層22、電洞傳輸層23、第1發光層24、電子傳輸層25、載子產生層26、電洞傳輸層27、第2發光層28、電子傳輸層29、電子注入層30及第2電極31係以覆蓋第1電極21及邊罩15之方式,遍及支撐基板10中之顯示區域R1之整個表面同樣地形成。 Therefore, in the present embodiment, as shown in FIG. 5, the hole injection layer 22, the hole transport layer 23, the first light-emitting layer 24, the electron transport layer 25, the carrier-generating layer 26, the hole transport layer 27, and the The light-emitting layer 28, the electron-transport layer 29, the electron-injecting layer 30, and the second electrode 31 are formed in the same manner over the entire surface of the display region R1 in the support substrate 10 so as to cover the first electrode 21 and the side cover 15.

再者,於圖5中,列舉於將電洞傳輸層、發光層及電子傳輸層設為1個單元時第1發光層24側之單元與第2發光層28側之單元經由載子產生層26而連接之情形為例進行了說明,但本實施形態並不限定於此。 In addition, in the case where the hole transport layer, the light-emitting layer, and the electron transport layer are one unit, the unit on the first light-emitting layer 24 side and the unit on the second light-emitting layer 28 side pass through the carrier generation layer. Although the case of connection is described as an example, the present embodiment is not limited to this.

例如,亦可同樣地積層包含第3發光層之單元,亦可積層4個以上之單元。 For example, a unit including the third light-emitting layer may be laminated in the same manner, or four or more units may be laminated.

又,亦可具有直接積層有第2發光層與第3發光層之積層構造。 Further, a laminated structure in which the second light-emitting layer and the third light-emitting layer are directly laminated may be provided.

進而,雖未進行圖示,但亦可視需要,插入阻止電洞、電子等載子之流動之載子阻擋層。例如,藉由在發光層與電子傳輸層之間追加電洞阻擋層作為載子阻擋層,可阻止電洞穿過電子傳輸層,而提高發光效率。同樣地,藉由在發光層與電洞傳輸層之間追加電子阻擋層作為載子阻擋層,可阻止電子穿過電洞傳輸層。 Further, although not illustrated, a carrier blocking layer that blocks the flow of carriers such as holes and electrons may be inserted as needed. For example, by adding a hole blocking layer between the light-emitting layer and the electron-transporting layer as a carrier blocking layer, it is possible to prevent the holes from passing through the electron-transporting layer, thereby improving luminous efficiency. Similarly, by adding an electron blocking layer between the light-emitting layer and the hole transport layer as a carrier blocking layer, electrons can be prevented from passing through the hole transport layer.

又,亦可於電子傳輸層與載子產生層之間插入電子注入層。 Further, an electron injecting layer may be interposed between the electron transporting layer and the carrier generating layer.

作為有機EL元件20之構成之一例,例如,可採用如下述(1)~(8)所示之層構成及該等層之組合。 As an example of the configuration of the organic EL element 20, for example, a layer configuration as shown in the following (1) to (8) and a combination of the layers can be employed.

(1)第1電極/電洞注入層/電洞傳輸層/發光層(第1發光層)/電子傳輸層/載子產生層/電洞傳輸層/發光層(第2發光層)/電子傳輸層/電子注入層/第2電極 (1) First electrode/hole injection layer/hole transport layer/light-emitting layer (first light-emitting layer)/electron transport layer/carrier generation layer/hole transport layer/light-emitting layer (second light-emitting layer)/electron Transport layer / electron injection layer / second electrode

(2)第1電極/電洞注入層/電洞傳輸層/發光層(第1發光層)/電子傳輸層/電子注入層/載子產生層/電洞傳輸層/發光層(第2發光層)/電子傳輸層/電子注入層/第2電極 (2) First electrode/hole injection layer/hole transmission layer/light-emitting layer (first light-emitting layer)/electron transport layer/electron injection layer/carrier generation layer/hole transport layer/light-emitting layer (second light-emitting layer) Layer) / electron transport layer / electron injection layer / second electrode

(3)第1電極/電洞注入層/電洞傳輸層/發光層(第1發光層)/電洞阻擋層/電子傳輸層/載子產生層/電洞傳輸層/發光層(第2發光層)/電洞阻擋層/電子傳輸層/電子注入層/第2電極 (3) First electrode/hole injection layer/hole transmission layer/light-emitting layer (first light-emitting layer)/hole barrier layer/electron transport layer/carrier generation layer/hole transport layer/light-emitting layer (second Light-emitting layer) / hole barrier layer / electron transport layer / electron injection layer / second electrode

(4)第1電極/電洞注入層/電洞傳輸層/電子阻擋層/發光層(第1發光層)/電洞阻擋層/電子傳輸層/電子注入層/載子產生層/電洞傳輸層/電子阻擋層/發光層(第2發光層)/電洞阻擋層/電子傳輸層/電子注入層/第2電極 (4) First electrode/hole injection layer/hole transmission layer/electron barrier layer/light-emitting layer (first light-emitting layer)/hole barrier layer/electron transport layer/electron injection layer/carrier generation layer/hole Transport layer/electron barrier layer/light emitting layer (second light emitting layer)/hole blocking layer/electron transport layer/electron injection layer/second electrode

(5)第1電極/電洞注入層/電洞傳輸層/發光層(第1發光層)/電子傳輸層/載子產生層/電洞傳輸層/發光層(第2發光層)/電子傳輸層/載子產生層/電洞傳輸層/發光層(第3發光層)/電子傳輸層/電子注入層/第2電極 (5) First electrode/hole injection layer/hole transport layer/light-emitting layer (first light-emitting layer)/electron transport layer/carrier generation layer/hole transport layer/light-emitting layer (second light-emitting layer)/electron Transport layer/carrier generation layer/hole transport layer/light-emitting layer (third light-emitting layer)/electron transport layer/electron injection layer/second electrode

(6)第1電極/電洞注入層/電洞傳輸層/電子阻擋層/發光層(第1發光層)/電洞阻擋層/電子傳輸層/電子注入層/載子產生層/電洞傳輸層/電子阻擋層/發光層(第2發光層)/電洞阻 擋層/電子傳輸層/電子注入層/載子產生層/電洞傳輸層/電子阻擋層/發光層(第3發光層)/電洞阻擋層/電子傳輸層/電子注入層/第2電極 (6) First electrode/hole injection layer/hole transmission layer/electron barrier layer/light-emitting layer (first light-emitting layer)/hole barrier layer/electron transport layer/electron injection layer/carrier generation layer/hole Transport layer / electron blocking layer / light emitting layer (second light emitting layer) / hole resistance Retaining layer/electron transport layer/electron injection layer/carrier generation layer/hole transport layer/electron barrier layer/light emitting layer (third light emitting layer)/hole blocking layer/electron transport layer/electron injection layer/second electrode

(7)第1電極/電洞注入層/電洞傳輸層/發光層(第1發光層)/電子傳輸層/載子產生層/電洞傳輸層/發光層(第2發光層)/發光層(第3發光層)/電子傳輸層/電子注入層/第2電極 (7) First electrode/hole injection layer/hole transmission layer/light-emitting layer (first light-emitting layer)/electron transport layer/carrier generation layer/hole transport layer/light-emitting layer (second light-emitting layer)/luminescence Layer (third light-emitting layer) / electron transport layer / electron injection layer / second electrode

(8)第1電極/電洞注入層/電洞傳輸層/電子阻擋層/發光層(第1發光層)/電洞阻擋層/電子傳輸層/電子注入層/載子產生層/電洞傳輸層/電子阻擋層/發光層(第2發光層)/發光層(第3發光層)/電洞阻擋層/電子傳輸層/電子注入層/第2電極 (8) First electrode/hole injection layer/hole transmission layer/electron barrier layer/light-emitting layer (first light-emitting layer)/hole barrier layer/electron transport layer/electron injection layer/carrier generation layer/hole Transport layer/electron barrier layer/light emitting layer (second light emitting layer)/light emitting layer (third light emitting layer)/hole blocking layer/electron transport layer/electron injection layer/second electrode

又,於本實施形態中,列舉如下之情形為例進行了說明:經由載子產生層而設置載子傳輸層(電洞傳輸層、電子傳輸層)及W發光之發光層(第1發光層24、第2發光層28),設置有第1發光層24及第2發光層28之至少2個發光層作為W發光之發光層。 In the present embodiment, a case has been described in which a carrier transport layer (hole transport layer, electron transport layer) and a W-emitting light-emitting layer (first light-emitting layer) are provided via a carrier generation layer. 24. The second light-emitting layer 28) is provided with at least two light-emitting layers of the first light-emitting layer 24 and the second light-emitting layer 28 as light-emitting layers of W light.

然而,發光層以外之有機層並非為有機EL層43所必需之層,又,發光層設置至少1個即可。有機EL層43之構成根據所要求之有機EL元件20之特性適當形成即可。 However, the organic layer other than the light-emitting layer is not a layer necessary for the organic EL layer 43, and at least one light-emitting layer may be provided. The configuration of the organic EL layer 43 may be appropriately formed in accordance with the characteristics of the desired organic EL element 20.

因此,作為一例,上述有機EL元件20亦可具有例如(9)所示之層構成。 Therefore, the organic EL element 20 may have a layer configuration as shown in (9), for example.

(9)第1電極/電洞注入層/電洞傳輸層/發光層(第1發光層)/電子傳輸層/電子注入層/第2電極 (9) First electrode/hole injection layer/hole transport layer/light-emitting layer (first light-emitting layer)/electron transport layer/electron injection layer/second electrode

又,一個層亦可具有複數之功能,例如,電洞注入層與電洞傳輸層既可如上述般作為相互獨立之層而形成,亦可 相互一體化地設置。即,亦可設置電洞注入層與電洞傳輸層一體化之電洞注入層兼電洞傳輸層,作為電洞注入層及電洞傳輸層。 Moreover, a layer may also have a plurality of functions. For example, the hole injection layer and the hole transport layer may be formed as separate layers as described above, or may be formed. They are integrated with each other. That is, a hole injection layer and a hole transport layer integrated with the hole injection layer and the hole transport layer may be provided as the hole injection layer and the hole transport layer.

同樣地,電子傳輸層與電子注入層既可如上述般作為相互獨立之層而形成,亦可作為電子傳輸層兼電子注入層而相互一體化地設置。 Similarly, the electron transport layer and the electron injection layer may be formed as separate layers as described above, or may be integrally provided as an electron transport layer and an electron injection layer.

再者,上述積層順序係將第1電極21設為陽極,將第2電極31設為陰極。於將第1電極21設為陰極,將第2電極31設為陽極之情形時,有機EL層43之積層順序反轉。 In the above-described lamination sequence, the first electrode 21 is an anode, and the second electrode 31 is a cathode. When the first electrode 21 is a cathode and the second electrode 31 is an anode, the order of lamination of the organic EL layer 43 is reversed.

再者,藉由將第1電極21設為半透明電極,將第2電極31設為反射電極,而形成底部發光型之有機EL元件20。 In addition, the second electrode 31 is a reflective electrode, and the bottom emission type organic EL element 20 is formed by using the first electrode 21 as a translucent electrode.

另一方面,藉由將第1電極21設為反射電極,將第2電極31設為半透明電極,而形成頂部發光型之有機EL元件20。 On the other hand, the first electrode 21 is a reflective electrode, and the second electrode 31 is a semi-transparent electrode to form a top emission type organic EL element 20.

再者,有機EL元件20之構成並不限定於上述例示之層構成,亦可根據所要求之有機EL元件20之特性而探用所期望之層構成。 In addition, the configuration of the organic EL element 20 is not limited to the above-described layer configuration, and a desired layer configuration can be explored in accordance with the characteristics of the desired organic EL element 20.

<圖像顯示方法> <Image display method>

圖6係對本實施形態之有機EL顯示裝置100之圖像顯示方法進行說明之模式圖。再者,於圖6中,簡化表示有機EL元件20之光徑之主要部分之構成。 FIG. 6 is a schematic view for explaining an image display method of the organic EL display device 100 of the present embodiment. In addition, in FIG. 6, the structure which shows the principal part of the optical path of the organic electroluminescent element 20 is simplified.

本實施形態之有機EL元件20具有微空腔構造。 The organic EL element 20 of the present embodiment has a microcavity structure.

所謂微空腔,係指藉由發出之光於陽極與陰極之間進行多次反射並發生共振,而發射光譜變陡,且波峰波長之發光強度被放大之現象。 The term "microcavity" refers to a phenomenon in which the emitted light is reflected by the light emitted from the anode and the cathode and resonated, and the emission spectrum becomes steep, and the luminous intensity of the peak wavelength is amplified.

微空腔效應可藉由例如將陽極或陰極之反射率及膜厚、有機層之膜厚等設計為最佳而獲得。 The microcavity effect can be obtained, for example, by designing the reflectance and film thickness of the anode or cathode, the film thickness of the organic layer, and the like to be optimal.

本實施形態之有機EL元件20係頂部發光型之有機EL元件,如圖6所示,為陰極且提取發光之側之第2電極31係作為半透明電極(半穿透反射電極)而發揮功能,為陽極且未提取發光之側之第1電極21係藉由包含反射電極層111而作為反射電極來發揮功能。 The organic EL element 20 of the present embodiment is a top emission type organic EL element, and as shown in FIG. 6, the second electrode 31 which is a cathode and extracts light emission functions as a translucent electrode (semi-transflective electrode). The first electrode 21 on the side where the anode is not extracted and emits light functions as a reflective electrode by including the reflective electrode layer 111.

因此,自設置於第1電極21與第2電極31之間之有機EL層43中之發光層(圖5所示之例中為第1發光層24及第2發光層28)發出之光係於第1電極21中之反射電極層111與第2電極31之間重複進行反射。 Therefore, the light-emitting layer emitted from the light-emitting layer (the first light-emitting layer 24 and the second light-emitting layer 28 in the example shown in FIG. 5) provided in the organic EL layer 43 between the first electrode 21 and the second electrode 31 The reflection between the reflective electrode layer 111 and the second electrode 31 in the first electrode 21 is repeated.

此時,如圖6所示,針對每一發光色,改變各子像素71R.71G.71B中之有機EL元件20之光徑長73R.73G.73B,藉此,自上述發光層發出之光於第1電極21之反射層與第2電極31之間往返,而特定波長之光之強度被放大。 At this time, as shown in FIG. 6, for each illuminating color, each sub-pixel 71R is changed. 71G. The optical path length of the organic EL element 20 in 71B is 73R. 73G. 73B, whereby light emitted from the light-emitting layer reciprocates between the reflective layer of the first electrode 21 and the second electrode 31, and the intensity of light of a specific wavelength is amplified.

於本實施形態中,於反射電極層111上設置透明電極層121,針對每一子像素71R.71G.71B變更該透明電極層121之膜厚,藉此,變更各子像素71R.71G.71B中之有機EL元件20之光徑長73R.73G.73B。 In this embodiment, a transparent electrode layer 121 is disposed on the reflective electrode layer 111 for each sub-pixel 71R. 71G. 71B changes the film thickness of the transparent electrode layer 121, thereby changing each sub-pixel 71R. 71G. The optical path length of the organic EL element 20 in 71B is 73R. 73G. 73B.

具體而言,於本實施形態中,如圖5及圖6所示,於子像素71B中僅利用反射電極層111形成第1電極21,將子像素71R.71G設為反射電極層111與透明電極層121之積層構造,利用1層或2層構成子像素71R.71G中之反射電極層111上之透明電極層121,藉此,變更各子像素71R.71G.71B中 之透明電極層121之膜厚。 Specifically, in the present embodiment, as shown in FIGS. 5 and 6 , the first electrode 21 is formed only by the reflective electrode layer 111 in the sub-pixel 71B, and the sub-pixel 71R. 71G is a laminated structure of the reflective electrode layer 111 and the transparent electrode layer 121, and the sub-pixel 71R is formed by one or two layers. The transparent electrode layer 121 on the reflective electrode layer 111 in the 71G, thereby changing each sub-pixel 71R. 71G. 71B The film thickness of the transparent electrode layer 121.

藉由如此般變更各子像素71R.71G.71B中之透明電極層121之膜厚,可使微空腔效應發生變化而調整發光色。 By changing the sub-pixels 71R as such. 71G. The film thickness of the transparent electrode layer 121 in 71B can change the luminescence color by changing the microcavity effect.

各子像素71R.71G.71B中之有機EL元件20之光徑長73R.73G.73B、即各子像素71R.71G.71B中之微空腔構造內之光徑之光學距離係以與應發生共振之光之波長具有固定關係之方式設定。 Each sub-pixel 71R. 71G. The optical path length of the organic EL element 20 in 71B is 73R. 73G. 73B, that is, each sub-pixel 71R. 71G. The optical distance of the optical path within the microcavity structure in 71B is set in a fixed relationship to the wavelength of the light that should resonate.

即,藉由如上述般對各子像素71R.71G.71B中之第1電極21之反射電極層111與第2電極31之間的距離進行調整而使光徑長一致之波長之光之強度藉由共振得到加強,而僅波長一致之光自第2電極31側射出。另一方面,除此以外之光徑長發生偏移之波長之光之強度較弱。 That is, by sub-pixels 71R as described above. 71G. In 71B, the distance between the reflective electrode layer 111 of the first electrode 21 and the second electrode 31 is adjusted so that the intensity of the light having the same optical path length is enhanced by resonance, and only the light having the same wavelength is from the second The side of the electrode 31 is emitted. On the other hand, the intensity of light having a wavelength at which the optical path length is shifted is weak.

因此,該等光徑長73R.73G.73B設定為與來自第2電極31之發射光之色相對應之光學長。 Therefore, the optical path length is 73R. 73G. 73B is set to an optical length corresponding to the color of the emitted light from the second electrode 31.

如本實施形態所示,例如,於子像素71中之顯示色為R、G、B之情形時,各光徑長73R.73G.73B係為了與該等R、G、B之各色之發射光譜峰波長一致,而以各光徑長73R.73G.73B按照光徑長73R>光徑長73G>光徑長73B之順序變短之方式設定各子像素71R.71G.71B中之透明電極層121之膜厚。 As shown in the present embodiment, for example, when the display color in the sub-pixel 71 is R, G, or B, each optical path length is 73R. 73G. 73B is in accordance with the emission spectrum peak wavelengths of the respective colors of R, G, and B, and each optical path length is 73R. 73G. 73B sets each sub-pixel 71R so that the optical path length 73R>the optical path length 73G>the optical path length 73B becomes shorter. 71G. The film thickness of the transparent electrode layer 121 in 71B.

然而,由於各光之適於共振之光徑長存在複數個,故亦可不一定按照光徑長73R>光徑長73G>光徑長73B之順序變短,亦可具有除此以外之關係。 However, since there are a plurality of optical path lengths suitable for resonance of each light, the optical path length 73R>the optical path length 73G>the optical path length 73B may not necessarily be shortened, or may have other relationships.

即,與R光之有機EL層43重疊之透明電極層121設定為 適於R光之共振之厚度,與G光之有機EL層43重疊之透明電極層121設定為適於G光之共振之厚度,與B光之有機EL層43重疊之透明電極層121設定為適於B光之共振之厚度。藉此,可發射色純度較高之光,而可提高有機EL顯示裝置100之色再現性。 That is, the transparent electrode layer 121 overlapping the organic EL layer 43 of the R light is set to The transparent electrode layer 121 which is suitable for the resonance of the R light and which overlaps with the organic EL layer 43 of the G light is set to have a thickness suitable for the resonance of the G light, and the transparent electrode layer 121 which is overlapped with the organic EL layer 43 of the B light is set to Suitable for the thickness of the resonance of B light. Thereby, light having a higher color purity can be emitted, and the color reproducibility of the organic EL display device 100 can be improved.

<有機EL顯示裝置100之製造方法> <Method of Manufacturing Organic EL Display Device 100>

繼而,對本實施形態之有機EL顯示裝置100之製造方法進行說明。 Next, a method of manufacturing the organic EL display device 100 of the present embodiment will be described.

首先,對有機EL元件20中之各層之材料及積層方法之概略進行說明。 First, the outline of the material and the lamination method of each layer in the organic EL element 20 will be described.

<有機EL元件20中之各層之材料及積層方法之概略> <Summary of Materials and Lamination Methods of Each Layer in Organic EL Element 20>

第1電極21係利用濺鍍法等形成電極材料之後,藉由光微影術技術及蝕刻等,對應於各個子像素71R.71G.71B而圖案形成。 The first electrode 21 is formed by an electrode material by a sputtering method or the like, and then corresponds to each sub-pixel 71R by photolithography, etching, or the like. 71G. 71B and the pattern is formed.

作為第1電極21,可使用多種導電性材料,但於如上述般向絕緣基板11側放射光之底部發光型之有機EL元件20之情形時,必需為半透明。 Although a plurality of types of conductive materials can be used as the first electrode 21, in the case of the bottom emission type organic EL element 20 which emits light to the insulating substrate 11 side as described above, it is necessary to be translucent.

另一方面,於自絕緣基板11之相反側放射光之頂部發光型之有機EL元件20之情形時,第2電極31必需為半透明。 On the other hand, in the case of the top emission type organic EL element 20 which emits light from the opposite side of the insulating substrate 11, the second electrode 31 must be translucent.

於有機EL元件20為頂部發光型之情形時,理想的是對第1電極21中之反射電極層111使用不透明之電極。作為反射電極層111中使用之反射電極材料,可使用例如Ag(銀)、Ag合金、Al(鋁)、Al合金及包含含有該等電極材料之層之積層體(積層膜)。 In the case where the organic EL element 20 is of the top emission type, it is preferable to use an opaque electrode for the reflective electrode layer 111 in the first electrode 21. As the reflective electrode material used in the reflective electrode layer 111, for example, Ag (silver), an Ag alloy, Al (aluminum), an Al alloy, and a laminate (layered film) including a layer containing the electrode materials can be used.

又,作為透明電極層121中使用之透明電極材料,可使用ITO(Indium Tin Oxide:氧化銦錫)、IZO(Indium Zinc Oxide:氧化銦鋅)、氧化鋅鎵(GZO,Gallium Zinc Oxide)等。 Further, as the transparent electrode material used in the transparent electrode layer 121, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), zinc gallium oxide (GZO, Gallium Zinc Oxide), or the like can be used.

另一方面,理想的是對第2電極31使用半透明電極。作為半透明電極,可使用例如金屬之半透明電極單質、金屬之半透明電極層與透明電極層之積層體,但就反射率.穿透率之觀點而言,較佳為銀。 On the other hand, it is preferable to use a translucent electrode for the second electrode 31. As the translucent electrode, for example, a metal translucent electrode element, a metal semi-transparent electrode layer and a transparent electrode layer can be used, but the reflectance. From the viewpoint of the transmittance, silver is preferred.

又,作為第1電極21及第2電極31之積層方法,可使用濺鍍法、真空蒸鍍法、CVD(chemical vapor deposition、化學蒸鍍)法、電漿CVD法、印刷法等。 Further, as a method of laminating the first electrode 21 and the second electrode 31, a sputtering method, a vacuum deposition method, a CVD (chemical vapor deposition) method, a plasma CVD method, a printing method, or the like can be used.

於本實施形態中,為了利用光徑長之差而控制所射出之發光色,藉由對子像素71R.71G.71B變更第1電極21或第2電極31(圖5及圖6所示之例中為第1電極21)中之透明電極層121之厚度,而對子像素71R.71G.71B導入微空腔構造。 In the present embodiment, in order to control the emitted luminescent color by the difference in optical path length, by sub-pixel 71R. 71G. 71B changes the thickness of the transparent electrode layer 121 in the first electrode 21 or the second electrode 31 (the first electrode 21 in the example shown in FIGS. 5 and 6), and the sub-pixel 71R. 71G. 71B is introduced into the microcavity structure.

再者,以下對如此般藉由變更透明電極層121之厚度而對子像素71R.71G.71B導入微空腔構造之方法進行詳細敍述。 Furthermore, the following applies to the sub-pixel 71R by changing the thickness of the transparent electrode layer 121. 71G. The method of introducing the 71B into the microcavity structure will be described in detail.

作為有機EL層43之材料,可使用既知之材料。 As the material of the organic EL layer 43, a known material can be used.

作為電洞注入層、電洞傳輸層或電洞注入層兼電洞傳輸層之材料,可列舉例如蒽、氮雜聯伸三苯、茀酮、腙、茋、聯伸三苯、苯炔、苯乙烯基胺、三苯基胺、卟啉、三唑、咪唑、二唑、噁唑、多芳基烷烴、苯二胺、芳基胺及該等之衍生物、噻吩系化合物、聚矽烷系化合物、乙烯 咔唑系化合物、苯胺系化合物等鏈狀式或雜環式共軛系之單體、低聚物或聚合物等。 Examples of the material of the hole injection layer, the hole transport layer, or the hole injection layer and the hole transport layer include hydrazine, aza-linked triphenyl, anthracene, anthracene, anthracene, a terphenyl, a benzene, and a styrene. Amine, triphenylamine, porphyrin, triazole, imidazole, A chain or heterocyclic ring such as an oxadiazole, an oxazole, a polyarylalkane, a phenylenediamine, an arylamine, or a derivative thereof, a thiophene compound, a polydecane compound, a vinyl oxazole compound or an aniline compound A monomer, oligomer or polymer of the conjugated system.

作為電子傳輸層、電子注入層或電子傳輸層兼電子注入層之材料,可列舉例如三(8-羥基喹啉)鋁錯合物、二唑衍生物、三唑衍生物、苯基喹噁啉衍生物、噻咯衍生物等。 Examples of the material of the electron transporting layer, the electron injecting layer, or the electron transporting layer and the electron injecting layer include tris(8-hydroxyquinoline)aluminum complex, An oxadiazole derivative, a triazole derivative, a phenylquinoxaline derivative, a silole derivative, and the like.

作為發光層之材料,可使用低分子螢光色素、金屬錯合物等發光效率較高之材料。可列舉例如蒽、萘、茚、菲、芘、稠四苯、聯伸三苯、苝、苉、丙二烯合茀、乙烯合菲、戊芬、稠五苯、蔻、丁二烯、香豆素、吖啶、茋及該等之衍生物、三(8-羥基喹啉)鋁錯合物、雙(苯并羥基喹啉)鈹錯合物、三(二苯甲醯基甲基)啡啉銪錯合物、二甲苯甲醯基乙烯基聯苯、羥基苯基噁唑、羥基苯基噻唑等。 As the material of the light-emitting layer, a material having high light-emitting efficiency such as a low molecular weight fluorescent dye or a metal complex can be used. For example, hydrazine, naphthalene, anthracene, phenanthrene, anthracene, fused tetraphenyl, terphenyl, hydrazine, hydrazine, propadiene, phenanthrene, pentyl, pentacene, hydrazine, butadiene, and coumarin , acridine, anthracene and derivatives thereof, tris(8-hydroxyquinoline)aluminum complex, bis(benzoquinoline)oxime complex, tris(diphenylmercaptomethyl)morphine A porphyrin complex, xylylene methylbiphenyl, hydroxyphenyl oxazole, hydroxyphenyl thiazole, and the like.

再者,對於發光層,既可分別使用單一之材料,亦可使用以某材料為主體材料,將其他材料作為客體材料或摻雜劑而混入之混合材料。 Further, as the light-emitting layer, a single material may be used, or a mixed material in which another material is used as a host material and other materials are used as a guest material or a dopant may be used.

作為載子產生層之材料,可列舉氧化鉬或五氧化釩等金屬氧化物、或將其等與芳香族烴或咔唑衍生物等共蒸鍍所得者、Au或Ag之金屬薄膜、IZO或ITO等透明導電層(透明電極層)等。 Examples of the material of the carrier-generating layer include metal oxides such as molybdenum oxide and vanadium pentoxide, or those obtained by co-evaporating them with an aromatic hydrocarbon or a carbazole derivative, or a metal thin film of Au or Ag, IZO or A transparent conductive layer (transparent electrode layer) such as ITO.

<有機EL顯示裝置100之製造方法> <Method of Manufacturing Organic EL Display Device 100>

繼而,對有機EL顯示裝置100之製造方法進行說明。 Next, a method of manufacturing the organic EL display device 100 will be described.

然而,本實施形態中記載之各構成要素之尺寸、材質、形狀等始終只是一實施形態,不應由此而限定解釋本發明 之範圍。 However, the dimensions, materials, shapes, and the like of the respective constituent elements described in the present embodiment are always only one embodiment, and the present invention should not be construed as limiting thereby. The scope.

首先,參照圖7,對有機EL顯示裝置100之製造步驟之流程之概要進行說明。 First, an outline of the flow of the manufacturing steps of the organic EL display device 100 will be described with reference to FIG.

圖7係按步驟表示有機EL顯示裝置100之製造步驟之一例之流程圖。 Fig. 7 is a flow chart showing an example of the manufacturing steps of the organic EL display device 100 in steps.

又,如上所述,本實施形態中記載之積層順序係將第1電極21設為陽極,將第2電極31設為陰極,於將第1電極21設為陰極,將第2電極31設為陽極之情形時,於第1電極21與第2電極31中,其材料以及厚度反轉。 Further, as described above, in the layering procedure described in the present embodiment, the first electrode 21 is an anode, the second electrode 31 is a cathode, and the first electrode 21 is a cathode, and the second electrode 31 is a cathode. In the case of the anode, the material and thickness of the first electrode 21 and the second electrode 31 are reversed.

首先,於步驟S1中,利用既知之方法,如圖5所示,於絕緣基板11之顯示區域R1上形成TFT12、信號線14、層間絕緣膜13及接觸孔13a。 First, in step S1, as shown in FIG. 5, the TFT 12, the signal line 14, the interlayer insulating film 13, and the contact hole 13a are formed on the display region R1 of the insulating substrate 11 by a known method.

於如本實施形態般製造頂部發光型之有機EL顯示裝置100之情形時,作為絕緣基板11,使用例如板厚0.7~1.1 mm之無鹼玻璃基板等玻璃基板或塑膠基板。 In the case of manufacturing the top emission type organic EL display device 100 as in the present embodiment, a glass substrate or a plastic substrate such as an alkali-free glass substrate having a thickness of 0.7 to 1.1 mm is used as the insulating substrate 11.

再者,絕緣基板11之X軸方向及Y軸方向之大小根據用途等適當設定即可,並無特別限定。再者,於本實施形態中,使用板厚0.7 mm之無鹼玻璃基板。 In addition, the size of the insulating substrate 11 in the X-axis direction and the Y-axis direction may be appropriately set depending on the application or the like, and is not particularly limited. Further, in the present embodiment, an alkali-free glass substrate having a thickness of 0.7 mm is used.

層間絕緣膜13及接觸孔13a係藉由利用公知之技術於形成有TFT12以及信號線14等之絕緣基板11上塗佈感光性樹脂,並利用光微影術技術進行圖案化而形成。 The interlayer insulating film 13 and the contact hole 13a are formed by applying a photosensitive resin to the insulating substrate 11 on which the TFT 12 and the signal line 14 are formed by a known technique, and patterning by photolithography.

再者,作為層間絕緣膜13,可使用既知之感光性樹脂。作為上述感光性樹脂,可列舉例如丙烯酸樹脂或聚醯亞胺樹脂等。作為層間絕緣膜13之膜厚,只要能夠補償由 TFT12所引起之階差即可,並無特別限定。於本實施形態中,例如,將丙烯酸樹脂成膜為約2 μm之膜厚。 Further, as the interlayer insulating film 13, a known photosensitive resin can be used. The photosensitive resin may, for example, be an acrylic resin or a polyimide resin. As the film thickness of the interlayer insulating film 13, as long as it can be compensated by The step caused by the TFT 12 is not particularly limited. In the present embodiment, for example, the film thickness of the acrylic resin is about 2 μm.

再者,於該步驟中,以將用以驅動TFT12之閘極線及源極線等信號線14抽出至端子部區域R3為止之方式圖案形成。又,於該步驟中,例如如圖3所示,於第2電極連接區域R2圖案形成連接部60。 In this step, the signal lines 14 for driving the TFTs 12, such as the gate lines and the source lines, are patterned to be drawn out to the terminal portion region R3. Moreover, in this step, for example, as shown in FIG. 3, the connection portion 60 is patterned in the second electrode connection region R2.

繼而,於步驟S2中,針對每一子像素71R.71G.71B製作厚度不同之第1電極21。再者,以下對如上所述有機EL顯示裝置100為頂部發光型之情形時之第1電極21之製作方法進行詳細敍述。 Then, in step S2, for each sub-pixel 71R. 71G. 71B produces the first electrode 21 having a different thickness. In the following, a method of manufacturing the first electrode 21 when the organic EL display device 100 is in the top emission type will be described in detail below.

然後,於步驟S3中,於層間絕緣膜13上被覆第1電極21之端部(圖案端部),並且如圖4所示,針對每一子像素71R.71G.71B以形成開口部15R.15G.15B之方式製作邊罩15。 Then, in step S3, the end portion (pattern end portion) of the first electrode 21 is coated on the interlayer insulating film 13, and as shown in FIG. 4, for each sub-pixel 71R. 71G. 71B to form an opening 15R. 15G. The side cover 15 is produced in the manner of 15B.

與層間絕緣膜13同樣地,對於邊罩15,可使用既知之感光性樹脂。作為上述感光性樹脂,可列舉例如丙烯酸樹脂或聚醯亞胺樹脂等。 Similarly to the interlayer insulating film 13, a known photosensitive resin can be used for the side cover 15. The photosensitive resin may, for example, be an acrylic resin or a polyimide resin.

邊罩15係為了補償由相鄰之子像素71中之第1電極21之層厚之差異而引起之階差,並且防止於上述第1電極21之端部,第1電極21與第2電極31發生短路,而將自第1電極21之膜厚最厚之子像素71R中之第1電極21之表面起之高度設定為例如約1 μm。 The side cover 15 is for preventing the step difference caused by the difference in the layer thickness of the first electrode 21 in the adjacent sub-pixels 71, and is prevented from being formed at the end of the first electrode 21, and the first electrode 21 and the second electrode 31 are provided. A short circuit occurs, and the height from the surface of the first electrode 21 in the sub-pixel 71R having the thickest film thickness of the first electrode 21 is set to, for example, about 1 μm.

於本實施形態中,以自子像素71R中之第1電極21之表面起之高度成為約1 μm之方式,圖案化形成自層間絕緣膜13 之表面起之高度約為1.2 μm之含有丙烯酸樹脂之邊罩15。 In the present embodiment, the self-interlayer insulating film 13 is patterned so as to have a height of about 1 μm from the surface of the first electrode 21 in the sub-pixel 71R. The side cover 15 is made of acrylic resin having a height of about 1.2 μm.

藉由以上步驟,製作形成有第1電極21及邊罩15之支撐基板10。 Through the above steps, the support substrate 10 on which the first electrode 21 and the side cover 15 are formed is produced.

繼而,於步驟S4中,對經由如上所述之步驟而獲得之支撐基板10實施用於脫水之減壓烘烤及作為第1電極21之表面清洗之氧電漿處理之後,如圖5所示,以被覆第1電極21及邊罩15之方式,於支撐基板10之顯示區域R1之整個表面製作有機EL層43。再者,以下對有機EL層43之製作方法進行具體說明。 Then, in step S4, the support substrate 10 obtained through the above-described steps is subjected to decompression baking for dehydration and oxygen plasma treatment as surface cleaning of the first electrode 21, as shown in FIG. The organic EL layer 43 is formed on the entire surface of the display region R1 of the support substrate 10 so as to cover the first electrode 21 and the side cover 15. In addition, the method of producing the organic EL layer 43 will be specifically described below.

然後,於步驟S5中,利用既知之方法形成第2電極31。具體而言,為了於顯示區域R1之整個表面形成第2電極31,並且與第2電極連接區域R2之連接部60電性連接,而以使其等區域露出之方式,利用例如使用蒸鍍用之遮罩之蒸鍍法而圖案形成。再者,對於第2電極31之製作,可使用與有機EL層43相同之方法。 Then, in step S5, the second electrode 31 is formed by a known method. Specifically, in order to form the second electrode 31 on the entire surface of the display region R1 and to electrically connect the connection portion 60 of the second electrode connection region R2, for example, the vapor deposition is used. The mask is formed by vapor deposition. Further, as for the fabrication of the second electrode 31, the same method as the organic EL layer 43 can be used.

第2電極31之膜厚較佳為10~30 nm。於第2電極31之膜厚未達10 nm之情形時,有無法充分進行光之反射,而無法充分獲得微空腔效應之虞。另一方面,於第2電極31之膜厚超過30 nm之情形時,有光之穿透率下降而亮度降低之虞。於本實施形態中,形成膜厚為20 nm之Ag而作為第2電極31。 The film thickness of the second electrode 31 is preferably 10 to 30 nm. When the film thickness of the second electrode 31 is less than 10 nm, the light reflection cannot be sufficiently performed, and the microcavity effect cannot be sufficiently obtained. On the other hand, when the film thickness of the second electrode 31 exceeds 30 nm, the transmittance of light decreases and the brightness decreases. In the present embodiment, Ag having a film thickness of 20 nm is formed as the second electrode 31.

藉此,於支撐基板10上形成包含第1電極21、有機EL層43及第2電極31之有機EL元件20。 Thereby, the organic EL element 20 including the first electrode 21, the organic EL layer 43, and the second electrode 31 is formed on the support substrate 10.

繼而,於步驟S6中,如圖2所示,利用密封樹脂層41將 形成有有機EL元件20之支撐基板10與密封基板50貼合,而進行有機EL元件20之封入。 Then, in step S6, as shown in FIG. 2, the sealing resin layer 41 is used. The support substrate 10 on which the organic EL element 20 is formed is bonded to the sealing substrate 50, and the organic EL element 20 is sealed.

又,有機EL元件20之封入可以例如如下之方式進行。 Moreover, the sealing of the organic EL element 20 can be performed, for example, as follows.

首先,如圖2所示,於包圍圖3所示之支撐基板10中之顯示區域R1及第2電極連接區域R2之框狀之密封區域L形成密封樹脂層41。 First, as shown in FIG. 2, a sealing resin layer 41 is formed in a frame-shaped sealing region L surrounding the display region R1 and the second electrode connection region R2 in the support substrate 10 shown in FIG.

繼而,於由支撐基板10與密封樹脂層41所包圍之空間內,以覆蓋第2電極31之方式,填充含有乾燥劑之具有接著性之填充樹脂層42作為防止氧或水分自外部滲入有機EL元件20內之保護膜。 Then, in the space surrounded by the support substrate 10 and the sealing resin layer 41, the filling resin layer 42 containing the desiccant is filled to prevent oxygen or moisture from infiltrating into the organic EL from the outside so as to cover the second electrode 31. A protective film in the component 20.

對於填充樹脂層42,使用例如環氧樹脂等。填充樹脂層42之膜厚為例如1~20 μm。 For the filling resin layer 42, for example, an epoxy resin or the like is used. The film thickness of the filled resin layer 42 is, for example, 1 to 20 μm.

然後,經由該密封樹脂層41,將支撐基板10與密封基板50貼合。 Then, the support substrate 10 and the sealing substrate 50 are bonded together via the sealing resin layer 41.

藉此,利用支撐基板10、密封基板50、密封樹脂層41及填充樹脂層42而將有機EL元件20密封。 Thereby, the organic EL element 20 is sealed by the support substrate 10, the sealing substrate 50, the sealing resin layer 41, and the filling resin layer 42.

作為密封基板50,使用例如具有0.4~1.1 mm之板厚之玻璃基板或塑膠基板等絕緣基板。再者,於本實施形態中,使用板厚0.7 mm之無鹼玻璃基板。 As the sealing substrate 50, for example, an insulating substrate such as a glass substrate or a plastic substrate having a thickness of 0.4 to 1.1 mm is used. Further, in the present embodiment, an alkali-free glass substrate having a thickness of 0.7 mm is used.

然後,於步驟S7中,如圖2所示,經由例如未圖示之ACF(Anisotropic Conductive Film:各向異性導電膜),將電路部102之連接端子103連接於支撐基板10之端子部區域R3之電氣配線端子2。如此,製造有機EL顯示裝置100。 Then, in step S7, as shown in FIG. 2, the connection terminal 103 of the circuit portion 102 is connected to the terminal portion region R3 of the support substrate 10 via, for example, an ACF (Anisotropic Conductive Film) (not shown). Electrical wiring terminal 2. In this manner, the organic EL display device 100 is manufactured.

再者,密封基板50之X軸方向及Y軸方向之大小亦可根 據作為目的之有機EL顯示裝置100之尺寸而適當調整,亦可使用與支撐基板10中之絕緣基板11大致相同之尺寸之絕緣基板,密封有機EL元件20之後,依據作為目的之有機EL顯示裝置100之尺寸而分斷。 Furthermore, the size of the sealing substrate 50 in the X-axis direction and the Y-axis direction may also be The organic EL display device 100 can be appropriately adjusted in size, and an insulating substrate having substantially the same size as the insulating substrate 11 in the support substrate 10 can be used, and after sealing the organic EL element 20, the organic EL display device can be used according to the purpose. Divided by the size of 100.

<有機EL層43之製作步驟之流程> <Flow of Production Step of Organic EL Layer 43>

繼而,列舉具有圖5所示之構成之有機EL顯示裝置100為例,對步驟S4中之有機EL層43之製作步驟之流程之概要進行說明。 Next, an outline of the flow of the manufacturing process of the organic EL layer 43 in the step S4 will be described by taking the organic EL display device 100 having the configuration shown in FIG. 5 as an example.

圖8係按步驟表示有機EL層43之製作步驟之一例之流程圖。 Fig. 8 is a flow chart showing an example of the steps of producing the organic EL layer 43 in steps.

其中,圖8所示之積層順序係將第1電極21設為陽極,將第2電極31設為陰極,於將第1電極21設為陰極,將第2電極31設為陽極之情形時,有機EL層43之積層順序反轉。 In the case where the second electrode 31 is a cathode and the second electrode 31 is an anode, the first electrode 21 is a cathode and the second electrode 31 is an anode. The layering order of the organic EL layer 43 is reversed.

於圖7所示之步驟S4中,對實施了用於脫水之減壓烘烤及作為第1電極21之表面清洗之氧電漿處理之支撐基板10,如圖8所示,首先,以被覆第1電極21及邊罩15之方式,於支撐基板10之顯示區域R1之整個表面藉由蒸鍍而圖案形成電洞注入層22(步驟S11)。 In the step S4 shown in FIG. 7, the support substrate 10 subjected to the reduced-pressure baking for dehydration and the oxygen plasma treatment as the surface cleaning of the first electrode 21 is as shown in FIG. In the first electrode 21 and the side cover 15, the hole injection layer 22 is patterned by vapor deposition on the entire surface of the display region R1 of the support substrate 10 (step S11).

對於上述圖案形成,使用例如真空蒸鍍法。於真空蒸鍍法中,使密接固定有顯示區域R1之整個表面開口之遮罩(開放遮罩)之支撐基板10之被蒸鍍面與蒸鍍源對向,使來自蒸鍍源之蒸鍍粒子(成膜材料)通過遮罩之開口而蒸鍍於被蒸鍍面。藉此,使自蒸鍍源飛散之蒸鍍粒子通過開放遮罩之開口部而均勻地蒸鍍於顯示區域R1之整個表面。 For the above pattern formation, for example, a vacuum evaporation method is used. In the vacuum vapor deposition method, the vapor deposition surface of the support substrate 10 in which the mask (open mask) having the entire surface opening of the display region R1 is fixed is opposed to the vapor deposition source, and the vapor deposition from the vapor deposition source is performed. The particles (film forming material) are vapor-deposited on the vapor-deposited surface through the opening of the mask. Thereby, the vapor deposition particles scattered from the vapor deposition source are uniformly vapor-deposited on the entire surface of the display region R1 by opening the opening of the mask.

再者,關於上述蒸鍍,例如,既可於使顯示區域R1之整個表面開口之開放遮罩相對於支撐基板10進行對準調整後將其密接貼合,一面使支撐基板10與開放遮罩一併旋轉,一面使自蒸鍍源飛散之蒸鍍粒子通過開放遮罩之開口部而蒸鍍於顯示區域R1,亦可使用上述開放遮罩,進行於支撐基板10與開放遮罩密接固定之狀態下掃描蒸鍍源而蒸鍍般之掃描蒸鍍。 Further, in the vapor deposition, for example, the open mask of the entire surface of the display region R1 may be aligned and adjusted with respect to the support substrate 10, and then the support substrate 10 and the open mask may be adhered to each other. The vapor deposition particles scattered from the vapor deposition source are vapor-deposited in the display region R1 through the opening of the open mask, and the open mask can be adhered and fixed to the support substrate 10 and the open mask. In the state of scanning, the vapor deposition source is scanned and vapor deposition is performed as in vapor deposition.

再者,此處,所謂對顯示區域R1之整個表面進行蒸鍍,係指遍及鄰接之色不同之子像素間不間斷地進行蒸鍍。 Here, the vapor deposition of the entire surface of the display region R1 means that vapor deposition is continuously performed between sub-pixels having different adjacent colors.

對於上述蒸鍍,可使用與先前相同之真空蒸鍍裝置。因此,此處,對真空蒸鍍裝置以及蒸鍍方法之詳細情況省略說明以及圖示。 For the above vapor deposition, the same vacuum evaporation apparatus as before can be used. Therefore, the details of the vacuum vapor deposition apparatus and the vapor deposition method will not be described or illustrated here.

再者,於如上述般使用真空蒸鍍裝置而成膜蒸鍍膜之情形時,理想的是該真空蒸鍍裝置藉由真空泵而設定為1.0×10-4 Pa以上之真空極限率。換言之,理想的是真空室內之壓力設定為1.0×10-4 Pa以下。 In the case where the vapor deposition film is formed by a vacuum vapor deposition apparatus as described above, it is preferable that the vacuum vapor deposition apparatus is set to a vacuum limit rate of 1.0 × 10 -4 Pa or more by a vacuum pump. In other words, it is desirable that the pressure in the vacuum chamber is set to 1.0 × 10 -4 Pa or less.

為了成為高於1.0×10-3 Pa之真空度,蒸鍍粒子之平均自由徑必需獲得充分之值。另一方面,若真空度低於1.0×10-3 Pa,則該平均自由徑變短,從而蒸鍍粒子散射,對於被成膜基板即支撐基板10之到達效率降低,或蒸鍍粒子附著於不需要之區域。因此,理想的是真空室設定為上述真空極限率。 In order to achieve a degree of vacuum higher than 1.0 × 10 -3 Pa, the average free path of the vapor-deposited particles must obtain a sufficient value. On the other hand, when the degree of vacuum is less than 1.0 × 10 -3 Pa, the average free diameter is shortened, and the vapor deposition particles are scattered, and the arrival efficiency of the support substrate 10 as a film formation substrate is lowered, or the vapor deposition particles are attached thereto. Unwanted area. Therefore, it is desirable that the vacuum chamber be set to the above vacuum limit rate.

繼而,於步驟S12中,使用開放遮罩,以被覆電洞注入層22之方式,以與電洞注入層22相同之圖案,以與電洞注 入層22相同之方式,於顯示區域R1之整個表面圖案形成(蒸鍍)電洞傳輸層23。 Then, in step S12, an open mask is used to cover the hole injection layer 22 in the same pattern as the hole injection layer 22, and the hole is injected. In the same manner as the entry layer 22, the hole transport layer 23 is formed (evaporated) over the entire surface pattern of the display region R1.

然後,使用開放遮罩,以被覆上述電洞傳輸層23之方式,以與電洞注入層22及電洞傳輸層23相同之圖案,以與電洞注入層22及電洞傳輸層23相同之方式,於顯示區域R1之整個表面,於各步驟中,依序同樣地圖案形成(蒸鍍)第1發光層24(步驟S13)、電子傳輸層25(步驟S14)、載子產生層26(步驟S15)、電洞傳輸層27(步驟S16)、第2發光層28(步驟S17)、電子傳輸層29(步驟S18)、電子注入層30(步驟S19)。 Then, an open mask is used to cover the hole transport layer 23 in the same pattern as the hole injection layer 22 and the hole transport layer 23, and is the same as the hole injection layer 22 and the hole transport layer 23. In the entire surface of the display region R1, the first light-emitting layer 24 (step S13), the electron transport layer 25 (step S14), and the carrier-generating layer 26 are sequentially formed (vapor-deposited) in each step. Step S15), hole transport layer 27 (step S16), second light-emitting layer 28 (step S17), electron transport layer 29 (step S18), and electron injection layer 30 (step S19).

該等有機EL層43之膜厚設定為例如與先前相同。 The film thickness of the organic EL layers 43 is set to be, for example, the same as before.

再者,電洞注入層22與電洞傳輸層23既可如上述般作為獨立之層而形成,亦可如上述般一體化。作為各自之膜厚,例如為1~100 nm。又,電洞注入層22與電洞傳輸層23之合計膜厚為例如2~200 nm。 Further, the hole injection layer 22 and the hole transport layer 23 may be formed as separate layers as described above, or may be integrated as described above. The film thickness of each is, for example, 1 to 100 nm. Further, the total film thickness of the hole injection layer 22 and the hole transport layer 23 is, for example, 2 to 200 nm.

又,電子傳輸層29與電子注入層30既可如上述般作為獨立之層而形成,亦可如上述般一體化。 Further, the electron transport layer 29 and the electron injection layer 30 may be formed as separate layers as described above, or may be integrated as described above.

作為電子傳輸層25、電子傳輸層29、電子注入層30各自之膜厚,例如為1~100 nm。又,電子傳輸層29與電子注入層30之合計膜厚為例如20~200 nm。 The film thickness of each of the electron transport layer 25, the electron transport layer 29, and the electron injection layer 30 is, for example, 1 to 100 nm. Further, the total film thickness of the electron transport layer 29 and the electron injection layer 30 is, for example, 20 to 200 nm.

第1發光層24及第2發光層28各自之膜厚為例如10~100 nm。 The film thickness of each of the first light-emitting layer 24 and the second light-emitting layer 28 is, for example, 10 to 100 nm.

又,載子產生層26之膜厚為例如1~30 nm。 Further, the film thickness of the carrier generating layer 26 is, for example, 1 to 30 nm.

於本實施形態中,成膜膜厚為2 nm之酞菁銅作為電洞注 入層22。又,成膜膜厚為30 nm之NPB(4,4'-雙[N-(1-萘基)-N-苯基胺基]聯苯)作為電洞傳輸層23。 In the present embodiment, copper phthalocyanine having a film thickness of 2 nm is used as a hole injection. Into layer 22. Further, NPB (4,4'-bis[N-(1-naphthyl)-N-phenylamino]biphenyl) having a film thickness of 30 nm was used as the hole transport layer 23.

又,分別成膜膜厚為40 nm之二唑衍生物作為電子傳輸層25及電子傳輸層29。又,成膜膜厚為1 nm之氟化鋰作為電子注入層30。 Also, the film thickness of each film is 40 nm. The oxadiazole derivative serves as the electron transport layer 25 and the electron transport layer 29. Further, lithium fluoride having a film thickness of 1 nm was used as the electron injection layer 30.

又,分別將以銥錯合物為客體材料,共蒸鍍作為主體材料之CBP(4,4'-N,N'-二咔唑-聯苯)而得者成膜為膜厚30 nm,而作為第1發光層24及第2發光層28。又,將共蒸鍍氧化鉬與NPB所得者成膜為膜厚10 nm,而作為載子產生層26。 Further, a film having a thickness of 30 nm was formed by co-depositing CBP (4,4'-N,N'-dicarbazole-biphenyl) as a host material by using a ruthenium complex as a guest material. The first light-emitting layer 24 and the second light-emitting layer 28 are used. Further, a film obtained by co-evaporation of molybdenum oxide and NPB was formed to have a film thickness of 10 nm, and was used as a carrier generating layer 26.

再者,於積層包含第3發光層之單元之情形時,例如,於步驟S18與步驟S19之間,如兩點劃線所示,依序同樣地圖案形成(蒸鍍)載子產生層(步驟S21)、電洞傳輸層(步驟S22)、第3發光層(步驟S23)、電子傳輸層(步驟S24)。 In the case where the unit including the third light-emitting layer is laminated, for example, between step S18 and step S19, the carrier generation layer is formed (vapor-deposited) in the same manner as indicated by a two-dot chain line. Step S21), a hole transport layer (step S22), a third light-emitting layer (step S23), and an electron transport layer (step S24).

作為此情形時之載子產生層、電洞傳輸層、第3發光層、電子傳輸層之材料及膜厚,例如,與包含第2發光層28之單元同樣地設定即可。 The material and film thickness of the carrier generation layer, the hole transport layer, the third light-emitting layer, and the electron transport layer in this case may be set in the same manner as the unit including the second light-emitting layer 28, for example.

於如上所述之有機EL顯示裝置100中,當藉由來自信號線14之信號輸入而使TFT12導通(ON)時,自第1電極21向有機EL層43注入電洞(hole)。另一方面,當自第2電極31對有機EL層43注入電子,電洞與電子於各發光層內再結合,再結合所得之電洞及電子使能量失活時,作為光而射出。 In the organic EL display device 100 as described above, when the TFT 12 is turned on (ON) by the signal input from the signal line 14, a hole is injected from the first electrode 21 to the organic EL layer 43. On the other hand, when electrons are injected from the second electrode 31 to the organic EL layer 43, the holes and electrons are recombined in the respective light-emitting layers, and when the obtained holes and electrons are combined to deactivate the energy, they are emitted as light.

於本實施形態中,第1發光層24及第2發光層28係不同之發光色之發光層,藉由有機EL元件20而獲得自第1發光層 24及第2發光層28射出之光之混合受到微空腔效應所得之光。 In the present embodiment, the first light-emitting layer 24 and the second light-emitting layer 28 are different in light-emitting color, and the light-emitting layer is obtained from the first light-emitting layer by the organic EL element 20. The mixture of the light emitted by the 24 and the second luminescent layer 28 is subjected to the microcavity effect.

<第1電極21之製作方法> <Method of Manufacturing First Electrode 21>

繼而,對頂部發光型之有機EL顯示裝置100中之第1電極21之製作方法(即,針對每一子像素71而光徑長均不同之電極之製作方法)進行說明。 Next, a method of fabricating the first electrode 21 in the top emission type organic EL display device 100 (that is, a method of fabricating an electrode having a different optical path length for each sub-pixel 71) will be described.

圖1(a)~(i)係按步驟表示步驟S2所示之頂部發光型之有機EL顯示裝置100中之第1電極21之製作方法之一例的剖面圖。 1(a) to 1(i) are cross-sectional views showing an example of a method of fabricating the first electrode 21 in the top emission type organic EL display device 100 shown in the step S2.

首先,於形成有圖5所示之層間絕緣膜13及接觸孔13a之支撐基板10上,如圖1(a)所示,利用濺鍍法等依序成膜作為透明電極層之非晶質(amorphous)之ITO(以下,記作「a-ITO」)層110、含有金屬材料等反射電極材料之反射電極層111、作為透明電極層之a-ITO層112(第1透明電極層)。 First, on the support substrate 10 on which the interlayer insulating film 13 and the contact hole 13a shown in FIG. 5 are formed, as shown in FIG. 1(a), an amorphous film as a transparent electrode layer is sequentially formed by sputtering or the like. An ITO (hereinafter referred to as "a-ITO") layer 110, a reflective electrode layer 111 containing a reflective electrode material such as a metal material, and an a-ITO layer 112 (first transparent electrode layer) as a transparent electrode layer.

繼而,於上述a-ITO層112上,針對每一子像素71R.71G.71B,藉由光微影術而形成抗蝕圖案201R.201G.201B。然後,將各抗蝕圖案201R.201G.201B作為遮罩,如圖1(b)所示,對a-ITO層110、反射電極層111及a-ITO層112進行蝕刻之後,藉由抗蝕劑剝離液而剝離清洗該等抗蝕圖案201R.201G.201B。 Then, on the above a-ITO layer 112, for each sub-pixel 71R. 71G. 71B, a resist pattern 201R is formed by photolithography. 201G. 201B. Then, each resist pattern 201R. 201G. As a mask, as shown in FIG. 1(b), the a-ITO layer 110, the reflective electrode layer 111, and the a-ITO layer 112 are etched, and then the resist patterns are peeled off and cleaned by a resist stripping solution. 201R. 201G. 201B.

藉此,如圖1(b)所示,以針對各色之每一子像素71R.71G.71B而將a-ITO層110、反射電極層111及a-ITO層112分離之方式進行圖案化。即,針對各色之每一子像素71R.71G.71B而形成經圖案化之a-ITO層110、反射電極層 111及a-ITO層112。 Thereby, as shown in FIG. 1(b), for each sub-pixel 71R of each color. 71G. 71B, the a-ITO layer 110, the reflective electrode layer 111, and the a-ITO layer 112 are patterned to be separated. That is, for each sub-pixel 71R of each color. 71G. 71B forms a patterned a-ITO layer 110, a reflective electrode layer 111 and a-ITO layer 112.

作為上述反射電極層111中使用之反射電極材料,較佳為與a-ITO不發生電蝕反應之反射電極材料,可使用例如選自由Ag、Ag合金及Al合金所組成之群之任一種。 As the reflective electrode material used in the above-mentioned reflective electrode layer 111, a reflective electrode material which does not undergo an electrolytic corrosion reaction with a-ITO is preferably used, and for example, any one selected from the group consisting of Ag, an Ag alloy, and an Al alloy can be used.

又,反射電極層111之厚度設定為例如50~200 nm。於本實施形態中,成膜電極厚度為100 nm之銀合金作為反射電極層111。 Further, the thickness of the reflective electrode layer 111 is set to, for example, 50 to 200 nm. In the present embodiment, a silver alloy having a film forming electrode thickness of 100 nm is used as the reflective electrode layer 111.

又,a-ITO層110之膜厚設定為例如200 nm以下(0~200 nm)。a-ITO層112之膜厚設定為例如5~50 nm。於本實施形態中,成膜電極厚度為100 nm之a-ITO層110及電極厚度為20 nm之a-ITO層112。 Further, the film thickness of the a-ITO layer 110 is set to, for example, 200 nm or less (0 to 200 nm). The film thickness of the a-ITO layer 112 is set to, for example, 5 to 50 nm. In the present embodiment, the a-ITO layer 110 having a film-forming electrode thickness of 100 nm and the a-ITO layer 112 having an electrode thickness of 20 nm are used.

再者,對於上述蝕刻,使用利用例如磷酸.硝酸.醋酸之混合液或氯化鐵等蝕刻液作為蝕刻液之濕式蝕刻。又,對於抗蝕劑剝離液,使用例如單異丙醇胺等。 Furthermore, for the above etching, use of, for example, phosphoric acid is used. Nitric acid. An etching solution such as a mixture of acetic acid or ferric chloride is used as a wet etching of an etching solution. Further, as the resist stripper, for example, monoisopropanolamine or the like is used.

然後,藉由對上述支撐基板10進行熱處理(退火),而如圖1(c)所示,使a-ITO層110.112結晶化。 Then, by heat-treating (annealing) the support substrate 10, as shown in FIG. 1(c), the a-ITO layer 110.112 is crystallized.

再者,上述熱處理中之處理溫度以及處理時間係以能夠使a-ITO層110.112結晶化之方式適當設定即可,並無特別限定。 In addition, the treatment temperature and the treatment time in the heat treatment are appropriately set so that the a-ITO layer 110.112 can be crystallized, and are not particularly limited.

於本實施形態中,於200℃下進行熱處理1小時。藉此,a-ITO轉化為結晶性之ITO(以下,記作「p-ITO」)。其結果,如圖1(c)所示,各子像素71R.71G.71B中之a-ITO層110.112轉化為p-ITO層113.114。 In the present embodiment, heat treatment was performed at 200 ° C for 1 hour. Thereby, a-ITO is converted into crystalline ITO (hereinafter referred to as "p-ITO"). As a result, as shown in FIG. 1(c), each sub-pixel 71R. 71G. The a-ITO layer 110.112 in 71B is converted to the p-ITO layer 113.114.

再者,於自a-ITO向p-ITO之轉化中,不存在膜厚之減少 等,而維持a-ITO之成膜時之膜厚。 Furthermore, in the conversion of a-ITO to p-ITO, there is no reduction in film thickness. And the film thickness at the time of film formation of a-ITO is maintained.

繼而,如圖1(d)所示,於上述支撐基板10上,以覆蓋上述p-ITO層113、反射電極層111及p-ITO層114(第1透明電極層)之方式,藉由例如濺鍍而成膜作為透明電極層之a-ITO層115(第2透明電極層)。 Then, as shown in FIG. 1(d), the p-ITO layer 113, the reflective electrode layer 111, and the p-ITO layer 114 (first transparent electrode layer) are covered on the support substrate 10 by, for example, The film was sputter-deposited as the a-ITO layer 115 (second transparent electrode layer) of the transparent electrode layer.

a-ITO層115之膜厚設定為例如40~120 nm。於本實施形態中,成膜電極厚度為80 nm之a-ITO層115。 The film thickness of the a-ITO layer 115 is set to, for example, 40 to 120 nm. In the present embodiment, the a-ITO layer 115 having a film-forming electrode thickness of 80 nm is formed.

繼而,如圖1(d)所示,於子像素71R中之a-ITO層115上,藉由光微影術,以俯視時覆蓋經圖案化之上述p-ITO層113、反射電極層111及p-ITO層114之方式形成抗蝕圖案202R。 Then, as shown in FIG. 1(d), on the a-ITO layer 115 in the sub-pixel 71R, the patterned p-ITO layer 113 and the reflective electrode layer 111 are covered in plan view by photolithography. A resist pattern 202R is formed in the same manner as the p-ITO layer 114.

此時,抗蝕圖案202R係以俯視時覆蓋反射電極層111之下層之p-ITO層113之圖案端部之方式,形成為較子像素71R中之p-ITO層113之圖案寬。 At this time, the resist pattern 202R is formed to be wider than the pattern of the p-ITO layer 113 in the sub-pixel 71R so as to cover the pattern end portion of the p-ITO layer 113 under the reflective electrode layer 111 in plan view.

換言之,抗蝕圖案202R係俯視時與上述反射電極層111及p-ITO層113重疊,且形成為俯視時較上述反射電極層111及p-ITO層113大。 In other words, the resist pattern 202R is overlapped with the reflective electrode layer 111 and the p-ITO layer 113 in plan view, and is formed larger than the reflective electrode layer 111 and the p-ITO layer 113 in plan view.

再者,俯視時抗蝕圖案202R自p-ITO層113之圖案端部起之突出量分別設定為2 μm。 Further, the amount of protrusion of the resist pattern 202R from the pattern end portion of the p-ITO layer 113 in plan view was set to 2 μm, respectively.

然後,將抗蝕圖案202R作為遮罩,使用蝕刻液,如圖1(e)所示,對未由抗蝕圖案202R遮罩之a-ITO層115進行濕式蝕刻之後,藉由抗蝕劑剝離液而剝離清洗抗蝕圖案202R。 Then, using the etching resist 202R as a mask, an etching liquid is used, as shown in FIG. 1(e), after the wet etching is performed on the a-ITO layer 115 not covered by the resist pattern 202R, the resist is used. The cleaning resist pattern 202R is peeled off by the stripping liquid.

作為上述蝕刻液,使用例如草酸。藉此,可選擇性地對 a-ITO層115進行蝕刻。又,對於抗蝕劑剝離液,可使用與圖1(b)所示之蝕刻中使用之抗蝕劑剝離液相同之抗蝕劑剝離液。 As the etching liquid, for example, oxalic acid is used. Thereby selectively The a-ITO layer 115 is etched. Further, as the resist stripping liquid, the same resist stripping liquid as that used in the etching shown in Fig. 1(b) can be used.

此時,p-ITO層113.114及反射電極層111未被上述蝕刻液(草酸)蝕刻或蝕刻速度明顯較慢。因此,p-ITO層113.114及反射電極層111係藉由上述蝕刻未被去除而殘留。 At this time, the p-ITO layer 113.114 and the reflective electrode layer 111 are not etched by the above etching liquid (oxalic acid) or the etching rate is remarkably slow. Therefore, the p-ITO layer 113.114 and the reflective electrode layer 111 remain without being removed by the above etching.

藉此,如圖1(e)所示,僅將由抗蝕圖案202R遮罩之子像素71R之a-ITO層115以外之a-ITO層115去除。 Thereby, as shown in FIG. 1(e), only the a-ITO layer 115 other than the a-ITO layer 115 of the sub-pixel 71R masked by the resist pattern 202R is removed.

然後,藉由對上述支撐基板10進行熱處理,而如圖1(f)所示,使a-ITO層115結晶化。 Then, by heat-treating the support substrate 10, the a-ITO layer 115 is crystallized as shown in Fig. 1(f).

再者,上述熱處理中之處理溫度以及處理時間係以能夠使a-ITO層115結晶化之方式適當設定即可,並無特別限定。 In addition, the treatment temperature and the treatment time in the heat treatment are appropriately set so that the a-ITO layer 115 can be crystallized, and are not particularly limited.

於本實施形態中,與圖1(c)所示之步驟同樣地,於200℃進行熱處理1小時。藉此,a-ITO轉化為p-ITO。其結果,如圖1(f)所示,子像素71R中之a-ITO層115轉化為p-ITO層116。 In the present embodiment, heat treatment was performed at 200 ° C for 1 hour in the same manner as the step shown in Fig. 1 (c). Thereby, a-ITO is converted into p-ITO. As a result, as shown in FIG. 1(f), the a-ITO layer 115 in the sub-pixel 71R is converted into the p-ITO layer 116.

繼而,如圖1(g)所示,於上述支撐基板10上,以覆蓋各子像素71R.71G.71B中之各透明電極層及反射電極層111之方式,藉由例如濺鍍而成膜作為透明電極層之a-ITO層117。 Then, as shown in FIG. 1(g), on the support substrate 10, to cover each sub-pixel 71R. 71G. In the manner of each of the transparent electrode layer and the reflective electrode layer 111 in the 71B, the a-ITO layer 117 which is a transparent electrode layer is formed by, for example, sputtering.

a-ITO層117之膜厚設定為例如20~60 nm。於本實施形態中,如下所述,由於在圖1(h)所示之步驟中藉由蝕刻而將子像素71R中之a-ITO層117去除,故以a-ITO層117之膜厚 小於p-ITO層116之膜厚(子像素71R中之光徑長73R)之方式成膜a-ITO層117。因此,將a-ITO層117之膜厚設定為小於p-ITO層116之膜厚之40 nm。 The film thickness of the a-ITO layer 117 is set to, for example, 20 to 60 nm. In the present embodiment, as described below, since the a-ITO layer 117 in the sub-pixel 71R is removed by etching in the step shown in FIG. 1(h), the film thickness of the a-ITO layer 117 is used. The a-ITO layer 117 is formed in a manner smaller than the film thickness of the p-ITO layer 116 (the optical path length 73R in the sub-pixel 71R). Therefore, the film thickness of the a-ITO layer 117 is set to be smaller than 40 nm of the film thickness of the p-ITO layer 116.

繼而,如圖1(g)所示,於子像素71G中之a-ITO層117上,藉由光微影術,以俯視時覆蓋經圖案化之上述p-ITO層113、反射電極層111及a-ITO層117之方式形成抗蝕圖案202G。 Then, as shown in FIG. 1(g), on the a-ITO layer 117 in the sub-pixel 71G, the patterned p-ITO layer 113 and the reflective electrode layer 111 are covered in plan view by photolithography. A resist pattern 202G is formed in the same manner as the a-ITO layer 117.

此時,抗蝕圖案202G係以俯視時覆蓋反射電極層111之下層之p-ITO層113之圖案端部之方式,形成為較子像素71G中之p-ITO層113之圖案寬。 At this time, the resist pattern 202G is formed to be wider than the pattern of the p-ITO layer 113 in the sub-pixel 71G so as to cover the pattern end portion of the p-ITO layer 113 under the reflective electrode layer 111 in plan view.

即,抗蝕圖案202G俯視時亦與上述反射電極層111及p-ITO層113重疊,且形成為俯視時較上述反射電極層111及p-ITO層113大。 In other words, the resist pattern 202G is also overlapped with the reflective electrode layer 111 and the p-ITO layer 113 in plan view, and is formed to be larger than the reflective electrode layer 111 and the p-ITO layer 113 in plan view.

再者,俯視時抗蝕圖案202G自p-ITO層113之圖案端部起之突出量與抗蝕圖案202R同樣地,分別設定為2 μm。 In addition, the amount of protrusion of the resist pattern 202G from the pattern end portion of the p-ITO layer 113 in plan view is set to 2 μm in the same manner as the resist pattern 202R.

然後,將抗蝕圖案202G作為遮罩,使用蝕刻液,如圖1(h)所示,對未由抗蝕圖案202G遮罩之a-ITO層117進行濕式蝕刻之後,藉由抗蝕劑剝離液而剝離清洗抗蝕圖案202G。 Then, using the etching resist 202G as a mask, an etching liquid is used, as shown in FIG. 1(h), after the wet etching of the a-ITO layer 117 not masked by the resist pattern 202G, the resist is used. The cleaning resist pattern 202G is peeled off by the stripping liquid.

再者,對於上述蝕刻液及剝離液,可使用與圖1(e)所示之蝕刻中使用之蝕刻液及剝離液相同之蝕刻液及剝離液。藉此,可選擇性地對a-ITO層117進行蝕刻。 Further, as the etching liquid and the peeling liquid, an etching liquid and a peeling liquid which are the same as the etching liquid and the peeling liquid used for the etching shown in Fig. 1(e) can be used. Thereby, the a-ITO layer 117 can be selectively etched.

此時,p-ITO層113.114.116及反射電極層111未被上述蝕刻液(草酸)蝕刻或蝕刻速度明顯較慢。因此,p-ITO層 113.114.116及反射電極層111係藉由上述蝕刻未被去除而殘留。 At this time, the p-ITO layer 113.114.116 and the reflective electrode layer 111 are not etched by the above etching liquid (oxalic acid) or the etching rate is remarkably slow. Therefore, the p-ITO layer 113.114.116 and the reflective electrode layer 111 remain without being removed by the above etching.

藉此,如圖1(h)所示,僅將由抗蝕圖案202G遮罩之子像素71G之a-ITO層117以外之a-ITO層117去除。 Thereby, as shown in FIG. 1(h), only the a-ITO layer 117 other than the a-ITO layer 117 of the sub-pixel 71G masked by the resist pattern 202G is removed.

然後,藉由對上述支撐基板10進行熱處理,而如圖1(i)所示,使a-ITO層117結晶化。 Then, by heat-treating the support substrate 10, the a-ITO layer 117 is crystallized as shown in Fig. 1(i).

再者,上述熱處理中之處理溫度以及處理時間係以能夠使a-ITO層117結晶化之方式適當設定即可,並無特別限定。 In addition, the treatment temperature and the treatment time in the heat treatment are appropriately set so that the a-ITO layer 117 can be crystallized, and are not particularly limited.

此處,亦與圖1(c)所示之步驟同樣地,於200℃下進行熱處理1小時。藉此,如圖1(i)所示,子像素71G中之a-ITO層117轉化為p-ITO層118。 Here, heat treatment was also performed at 200 ° C for 1 hour in the same manner as the step shown in Fig. 1 (c). Thereby, as shown in FIG. 1(i), the a-ITO layer 117 in the sub-pixel 71G is converted into the p-ITO layer 118.

藉此,於子像素71R形成反射電極層111由作為反射電極層111之下層之透明電極層之p-ITO層113與作為反射電極層111之上層之透明電極層之p-ITO層114.116包圍之第1電極21。 Thereby, the p-ITO layer 113 in which the reflective electrode layer 111 is formed of the transparent electrode layer as the lower layer of the reflective electrode layer 111 and the transparent electrode layer as the upper layer of the reflective electrode layer 111 is formed in the sub-pixel 71R. The first electrode 21 is surrounded.

再者,作為反射電極層111之上層之透明電極層之p-ITO層114.116係作為形成微空腔之透明電極層121而發揮功能。 Further, the p-ITO layer 114.116 which is a transparent electrode layer above the reflective electrode layer 111 functions as a transparent electrode layer 121 which forms a microcavity.

因此,於子像素71R中,以p-ITO層113.116之合計膜厚成為子像素71R之光徑長73R之方式設定各p-ITO層113.116之膜厚。 Therefore, in the sub-pixel 71R, the film thickness of each p-ITO layer 113.116 is set so that the total film thickness of the p-ITO layer 113.116 becomes the optical path length 73R of the sub-pixel 71R.

又,於子像素71G形成反射電極層111由作為反射電極層111之下層之透明電極層之p-ITO層113與作為反射電極層 111之上層之透明電極層之p-ITO層114及膜厚小於p-ITO層116之p-ITO層118包圍之第1電極21。 Further, the reflective electrode layer 111 is formed on the sub-pixel 71G by the p-ITO layer 113 as a transparent electrode layer under the reflective electrode layer 111 and as a reflective electrode layer. The p-ITO layer 114 and the film thickness of the transparent electrode layer of the upper layer of 111 are smaller than the first electrode 21 surrounded by the p-ITO layer 118 of the p-ITO layer 116.

於子像素71G中,作為反射電極層111之上層之透明電極層之p-ITO層114.118係作為形成微空腔之透明電極層121而發揮功能。 In the sub-pixel 71G, the p-ITO layer 114.118 which is a transparent electrode layer above the reflective electrode layer 111 functions as a transparent electrode layer 121 which forms a microcavity.

因此,於子像素71G中,以p-ITO層114.118之合計膜厚成為子像素71G之光徑長73G之方式設定各p-ITO層114.118之膜厚。 Therefore, in the sub-pixel 71G, the film thickness of each p-ITO layer 114.118 is set so that the total film thickness of the p-ITO layer 114.118 becomes the optical path length 73G of the sub-pixel 71G.

又,於子像素71B形成反射電極層111由作為反射電極層111之下層之透明電極層之p-ITO層113與作為反射電極層111之上層之透明電極層之p-ITO層114夾持之第1電極21。 Further, the reflective electrode layer 111 is formed on the sub-pixel 71B by the p-ITO layer 113 which is a transparent electrode layer under the reflective electrode layer 111 and the p-ITO layer 114 which is a transparent electrode layer above the reflective electrode layer 111. The first electrode 21.

於子像素71B中,作為反射電極層111之上層之透明電極層之p-ITO層114係作為形成微空腔之透明電極層121而發揮功能。 In the sub-pixel 71B, the p-ITO layer 114 which is a transparent electrode layer above the reflective electrode layer 111 functions as a transparent electrode layer 121 which forms a microcavity.

因此,於子像素71B中,以p-ITO層114之膜厚成為子像素71G之光徑長73G之方式設定p-ITO層114之膜厚。 Therefore, in the sub-pixel 71B, the film thickness of the p-ITO layer 114 is set such that the film thickness of the p-ITO layer 114 becomes the optical path length 73G of the sub-pixel 71G.

然而,本實施形態並不限定於此,亦可具有於各子像素71R.71G.71B進而積層有未圖示之p-ITO層或如IZO層般組成與ITO層不同之透明電極層之構成。 However, the embodiment is not limited thereto, and may be provided in each sub-pixel 71R. 71G. Further, 71B is formed by laminating a p-ITO layer (not shown) or a transparent electrode layer different from the ITO layer as in the case of an IZO layer.

如上所述,根據本實施形態,藉由如上述般重複進行a-ITO層之成膜步驟、藉由光微影術對上述a-ITO層進行蝕刻而將其圖案化之圖案化步驟、及將進行圖案化所得之a-ITO層轉化為p-ITO層之結晶化步驟,可對任意之子像素積層任意數量之p-ITO層。 As described above, according to the present embodiment, the patterning step of patterning the a-ITO layer by etching the a-ITO layer by photolithography is repeated by repeating the film forming step of the a-ITO layer as described above, and The crystallization step of converting the a-ITO layer obtained by patterning into a p-ITO layer allows any number of p-ITO layers to be laminated on any sub-pixel.

藉由經由以上之處理,如圖1(i)所示,可針對不同色之每一子像素71R.71G.71B,改變透明電極層121之膜厚。 By the above processing, as shown in FIG. 1(i), each sub-pixel 71R of different colors can be used. 71G. 71B, the film thickness of the transparent electrode layer 121 is changed.

於本實施形態中,如此般形成第1電極21之後,如步驟S3所示,製作邊罩15。 In the present embodiment, after the first electrode 21 is formed in this manner, the side cover 15 is produced as shown in step S3.

圖9(a)係模式性地表示於步驟S3中於第1電極21上製作有邊罩15時之第1電極21之概略構成的剖面圖,圖9(b)係模式性地表示於步驟S3中於第1電極21上製作有邊罩15時之第1電極21之概略構成的俯視圖。 Fig. 9(a) is a cross-sectional view schematically showing a schematic configuration of the first electrode 21 when the side cover 15 is formed on the first electrode 21 in step S3, and Fig. 9(b) is schematically shown in the step. A plan view showing a schematic configuration of the first electrode 21 when the side cover 15 is formed on the first electrode 21 in S3.

於本實施形態中,如圖1(d)所示,使抗蝕圖案202R以俯視時覆蓋反射電極層111之下層之p-ITO層113之圖案端部之方式形成為較子像素71R中之p-ITO層113之圖案寬。 In the present embodiment, as shown in FIG. 1(d), the resist pattern 202R is formed to be in the sub-pixel 71R so as to cover the end portion of the pattern of the p-ITO layer 113 under the reflective electrode layer 111 in plan view. The pattern of the p-ITO layer 113 is wide.

因此,於本實施形態中,藉由圖1(e)所示之步驟中之蝕刻,由抗蝕圖案202R覆蓋之p-ITO層113之周圍之a-ITO層115未被蝕刻去除,而如圖9(a).(b)所示,以覆蓋經圖案化之反射電極層111及p-ITO層113之方式殘留。 Therefore, in the present embodiment, the a-ITO layer 115 around the p-ITO layer 113 covered by the resist pattern 202R is not etched away by etching in the step shown in FIG. 1(e), and Figure 9 (a). (b) remains as shown covering the patterned reflective electrode layer 111 and the p-ITO layer 113.

又,於本實施形態中,如圖1(g)所示,抗蝕圖案202G係以俯視時覆蓋反射電極層111之下層之p-ITO層113之圖案端部之方式形成為較子像素71G中之各p-ITO層113之圖案寬。 Further, in the present embodiment, as shown in FIG. 1(g), the resist pattern 202G is formed to be smaller than the sub-pixel 71G so as to cover the end portion of the pattern of the p-ITO layer 113 under the reflective electrode layer 111 in plan view. The pattern of each of the p-ITO layers 113 is wide.

因此,於本實施形態中,藉由圖1(h)所示之步驟中之蝕刻,由抗蝕圖案202G覆蓋之p-ITO層113之周圍之a-ITO層117未被蝕刻去除,而如圖9(a).(b)所示,以覆蓋經圖案化之反射電極層111及p-ITO層113之方式殘留。 Therefore, in the present embodiment, the a-ITO layer 117 around the p-ITO layer 113 covered by the resist pattern 202G is not etched away by etching in the step shown in FIG. 1(h). Figure 9 (a). (b) remains as shown covering the patterned reflective electrode layer 111 and the p-ITO layer 113.

因此,於本實施形態中,於圖1(e)或圖1(h)所示之步驟 後,於各子像素71R.71G中,不僅反射電極層111之上層不露出,其側面亦不露出。 Therefore, in the present embodiment, the steps shown in Fig. 1 (e) or Fig. 1 (h) After, in each sub-pixel 71R. In the 71G, not only the upper layer of the reflective electrode layer 111 is not exposed, but also the side surface thereof is not exposed.

再者,於圖1(a)~(i)所示之步驟中,於子像素71R.71G中之反射電極層111上積層有複數層p-ITO層,勿庸置疑,藉由變更形成抗蝕圖案之子像素,可於任意之子像素中之反射電極層111上積層複數層p-ITO層。 Furthermore, in the steps shown in FIGS. 1(a) to (i), the sub-pixel 71R. A plurality of p-ITO layers are laminated on the reflective electrode layer 111 in the 71G, and it is needless to say that a plurality of p-ITO layers can be laminated on the reflective electrode layer 111 in any sub-pixel by changing the sub-pixels forming the resist pattern. .

又,於使在反射電極層111上積層之p-ITO層之積層數增加之情形時,以與圖1(d)或圖1(g)所示之步驟相同之方式,於子像素71B上形成p-ITO層,藉此,不僅於子像素71R.71G中,於子像素71B中,亦可獲得反射電極層111由作為反射電極層111之下層之透明電極層之p-ITO層113與作為反射電極層111之上層之透明電極層之p-ITO層114.116包圍之第1電極21。 Further, when the number of layers of the p-ITO layer laminated on the reflective electrode layer 111 is increased, the sub-pixel 71B is applied in the same manner as the step shown in Fig. 1 (d) or Fig. 1 (g). Forming a p-ITO layer, thereby not only sub-pixel 71R. In the 71G, in the sub-pixel 71B, the p-ITO layer 113 having the reflective electrode layer 111 from the transparent electrode layer as the lower layer of the reflective electrode layer 111 and the transparent electrode layer as the upper layer of the reflective electrode layer 111 can also be obtained. The first electrode 21 is surrounded by a layer 114.116.

<效果> <effect>

如上所述,於本實施形態中,於反射電極層111之上層(例如反射電極層111上)成膜a-ITO層112(第1透明電極層)作為含有非晶質之透明電極材料之透明電極層並統括地進行蝕刻之後,將該a-ITO層112轉化為含有多晶之透明電極材料之透明電極層(即p-ITO層114),利用其與成膜於其之上方之透明電極層即a-ITO層115.117(第2透明電極層)之耐蝕刻性之差異而積層透明電極層,藉此於各子像素71R.71G.71B間變更上述透明電極層之合計膜厚。 As described above, in the present embodiment, the a-ITO layer 112 (first transparent electrode layer) is formed on the upper layer of the reflective electrode layer 111 (for example, on the reflective electrode layer 111) as a transparent transparent electrode material. After the electrode layer is collectively etched, the a-ITO layer 112 is converted into a transparent electrode layer (ie, p-ITO layer 114) containing a polycrystalline transparent electrode material, and a transparent electrode formed thereon is formed thereon. The layer, that is, the a-ITO layer 115.117 (the second transparent electrode layer) has a difference in etching resistance, and a transparent electrode layer is laminated, whereby each sub-pixel 71R. 71G. The total film thickness of the above transparent electrode layers was changed between 71B.

如上所述,根據本實施形態,藉由如上述般於反射電極層111之上層成膜a-ITO層112,並統括地對反射電極層111 及a-ITO層112進行蝕刻,而不會增加光微影術之次數,且可於反射電極層111上積層p-ITO層114。 As described above, according to the present embodiment, the a-ITO layer 112 is formed on the upper surface of the reflective electrode layer 111 as described above, and the reflective electrode layer 111 is collectively applied. The a-ITO layer 112 is etched without increasing the number of photolithography, and the p-ITO layer 114 may be laminated on the reflective electrode layer 111.

又,根據本實施形態,於成膜耐蝕刻性低於p-ITO層114(第1透明電極層)之透明電極層(第2透明電極層)即a-ITO層115.117之前,於各子像素71R.71G.71B預先積層有a-ITO層112,藉此,可對任意之子像素71積層上述第2透明電極層。 Further, according to the present embodiment, before the a-ITO layer 115.117 which is a transparent electrode layer (second transparent electrode layer) having a lower film forming etching resistance than the p-ITO layer 114 (first transparent electrode layer), Subpixel 71R. 71G. In the 71B, the a-ITO layer 112 is laminated in advance, whereby the second transparent electrode layer can be laminated on any of the sub-pixels 71.

因此,即便不如專利文獻3般,為了堆積透明電極層而另外成膜具有結晶性之ITO層並將其圖案化,並且每當光微影術時於2個子像素形成相同膜厚之透明電極層之圖案,亦可利用2次光微影術,針對顯示色不同之每一子像素71R.71G.71B,形成反射電極層111上之透明電極層之合計膜厚(即透明電極層121之膜厚)不同之第1電極21。 Therefore, even if it is not as in the case of Patent Document 3, a crystalline ITO layer is additionally formed and patterned in order to deposit a transparent electrode layer, and a transparent electrode layer having the same film thickness is formed in two sub-pixels every time the photolithography is performed. The pattern can also be used for 2 times of photolithography, for each sub-pixel 71R with different display colors. 71G. 71B, the first electrode 21 having a total thickness of the transparent electrode layers on the reflective electrode layer 111 (that is, the film thickness of the transparent electrode layer 121) is different.

即,根據本實施形態,如圖1(d).(g)所示,作為為了針對每一子像素71R.71G.71B而變更透明電極層之膜厚(積層數)所需之光微影術之次數,可利用2次光微影術而針對每一子像素71R.71G.71B任意地變更反射電極層111上之透明電極層121之膜厚。又,根據本實施形態,即便包含反射電極層111之蝕刻,亦可將光微影術之次數抑制為3次。 That is, according to this embodiment, as shown in Fig. 1(d). (g) is shown as being for each sub-pixel 71R. 71G. 71B, the number of photolithography required to change the film thickness (the number of layers) of the transparent electrode layer can be used for each sub-pixel 71R by secondary photolithography. 71G. 71B arbitrarily changes the film thickness of the transparent electrode layer 121 on the reflective electrode layer 111. Further, according to the present embodiment, even if the etching of the reflective electrode layer 111 is included, the number of photolithography can be suppressed to three times.

因此,根據本實施形態,即便如上述般減少了光微影術之次數,亦可使任意之子像素71中之第2透明電極層之膜厚獨立於其他子像素71中之第2透明電極層之膜厚而設定。 Therefore, according to the present embodiment, even if the number of photolithography is reduced as described above, the film thickness of the second transparent electrode layer in any of the sub-pixels 71 can be made independent of the second transparent electrode layer in the other sub-pixels 71. The film thickness is set.

據此,於本實施形態中,如上所述,利用含有非結晶之 透明電極材料之透明電極層與含有多晶之透明電極材料之透明電極層之蝕刻選擇性之差異(例如如上所述,a-ITO層與p-ITO層之蝕刻選擇性之差異),進行各色單層中之透明電極層之堆積。 Accordingly, in the present embodiment, as described above, the use of non-crystalline The difference in etching selectivity between the transparent electrode layer of the transparent electrode material and the transparent electrode layer containing the polycrystalline transparent electrode material (for example, the difference in etching selectivity between the a-ITO layer and the p-ITO layer as described above) Stacking of transparent electrode layers in a single layer.

根據本實施形態,藉由將非結晶之透明電極材料轉化為多晶之透明電極材料,可提高對於蝕刻液之耐蝕刻性。 According to this embodiment, the etching resistance to the etching liquid can be improved by converting the amorphous transparent electrode material into a polycrystalline transparent electrode material.

因此,根據本實施形態,可任意且容易地調整各子像素71R.71G.71B中之光徑長73R.73G.73B,而不會如專利文獻3般受光徑長之制約。 Therefore, according to this embodiment, each sub-pixel 71R can be arbitrarily and easily adjusted. 71G. The light path length in 71B is 73R. 73G. 73B, and is not restricted by the optical path length as in Patent Document 3.

因此,根據本實施形態,可利用次數少於先前之光微影術,針對顯示色不同之每一子像素71任意地變更第1電極21之膜厚、換言之、有機EL元件20之光徑長。 Therefore, according to the present embodiment, the film thickness of the first electrode 21, in other words, the optical path length of the organic EL element 20, can be arbitrarily changed for each sub-pixel 71 having a different display color than the previous photolithography. .

因此,可實現較先前成本降低及佔據面積減少。 As a result, a lower cost reduction and a smaller footprint can be achieved.

又,如上所述,於先前之方法中,由於抗蝕劑之剝離及烘烤步驟變多,故有反射電極層之表面粗糙或發生氧化而反射效率降低,或因反射電極之表面粗糙而發生電極間漏電而導致像素缺陷之虞。 Further, as described above, in the prior method, since the peeling and baking steps of the resist are increased, the surface of the reflective electrode layer is rough or oxidized to lower the reflection efficiency, or the surface of the reflective electrode is rough. Leakage between electrodes leads to defects in pixel defects.

然而,根據本實施形態,由於可減少曝光、顯影、抗蝕劑剝離處理等之次數,故不存在如上所述之擔憂,而可提高作為有機EL用基板之支撐基板10之品質。又,可縮短處理節拍。 However, according to the present embodiment, since the number of times of exposure, development, and resist stripping treatment can be reduced, there is no fear as described above, and the quality of the support substrate 10 as the substrate for organic EL can be improved. Also, the processing beat can be shortened.

又,於反射電極層111或信號線14之端子部由Ag所形成之情形時,若Ag處於暴露狀態(即露出狀態),則當例如為了提高抗蝕劑之濕潤性而對支撐基板10進行紫外線照射 時,暴露之Ag發生氧化而成為氧化銀。 Further, when the terminal portions of the reflective electrode layer 111 or the signal line 14 are formed of Ag, if Ag is exposed (ie, exposed), the support substrate 10 is performed, for example, to improve the wettability of the resist. Ultraviolet radiation At this time, the exposed Ag is oxidized to become silver oxide.

因此,於反射電極層111或信號線14之端子部由Ag所形成之情形時,不理想的是於進行紫外線照射之情形時,當紫外線照射時Ag處於暴露狀態。 Therefore, when the terminal portions of the reflective electrode layer 111 or the signal line 14 are formed of Ag, it is not preferable that when ultraviolet irradiation is performed, Ag is exposed when ultraviolet rays are irradiated.

又,於反射電極層111或信號線14之端子部由Al所形成之情形時,亦有Al之耐溶劑性較低,而溶劑通過IZO層滲入之可能性。 Further, when the terminal portions of the reflective electrode layer 111 or the signal line 14 are formed of Al, there is a possibility that the solvent resistance of Al is low and the solvent penetrates through the IZO layer.

因此,於任一情形時,理想的是反射電極層111及信號線14之端子部如上述般由p-ITO層覆蓋。 Therefore, in either case, it is desirable that the terminal portions of the reflective electrode layer 111 and the signal line 14 are covered by the p-ITO layer as described above.

根據本實施形態,形成於反射電極層111之下層或上層之p-ITO層係藉由於a-ITO層之成膜步驟中,亦於源極線等信號線14之端子部上成膜a-ITO層,而可用作覆蓋源極線等信號線14之端子部之保護膜。 According to the present embodiment, the p-ITO layer formed on the lower layer or the upper layer of the reflective electrode layer 111 is formed by forming a film on the terminal portion of the signal line 14 such as the source line by the film formation step of the a-ITO layer. The ITO layer can be used as a protective film covering the terminal portion of the signal line 14 such as the source line.

再者,對於積層於反射電極層111上之其他透明電極層,藉由將該等透明電極層積層於源極線等信號線14之端子部上,亦可用作覆蓋信號線14之端子部之保護膜。 Further, the other transparent electrode layers laminated on the reflective electrode layer 111 may be used as a terminal portion covering the signal line 14 by laminating the transparent electrode layers on the terminal portions of the signal lines 14 such as the source lines. Protective film.

又,根據本實施形態,藉由反射電極層111及信號線14之端子部於製造步驟中之早期階段由p-ITO層113.114覆蓋,例如可減少該等反射電極層111及信號線14之端子部被浸於顯影液中之次數或區域等,可保護上述反射電極層111免受有損壞該反射電極層111之品質之虞之上述要因的影響。 Further, according to the present embodiment, the terminal portions of the reflective electrode layer 111 and the signal line 14 are covered by the p-ITO layer 113.114 at an early stage in the manufacturing process, for example, the reflective electrode layers 111 and the signal lines 14 can be reduced. The number of times or the area in which the terminal portion is immersed in the developer can protect the reflective electrode layer 111 from the above-mentioned factors that may deteriorate the quality of the reflective electrode layer 111.

又,如上述般將抗蝕圖案202R.202G形成為俯視時較各子像素71R.71G中之p-ITO層113之圖案寬,如上述般利用 p-ITO層夾持或者利用p-ITO層密封反射電極層111,藉此可獲得相同之效果。 Moreover, the resist pattern 202R is as described above. 202G is formed in a plan view compared to each sub-pixel 71R. The pattern of the p-ITO layer 113 in the 71G is wide and is utilized as described above. The p-ITO layer is sandwiched or the reflective electrode layer 111 is sealed with a p-ITO layer, whereby the same effect can be obtained.

再者,p-ITO不僅可藉由對a-ITO進行熱處理而獲得,亦可直接藉由成膜裝置而形成p-ITO。然而,當直接成膜p-ITO時,容易因成膜中之結晶粒之成長而膜之平坦性降低,或容易產生結晶間之針孔。若膜之平坦性變低,則有機EL元件20容易因第1電極21與第2電極31之短路而受損。又,若產生針孔,則有蝕刻液或顯影液等自上述針孔滲入,而使下層之膜受損之虞。因此,p-ITO層理想的是於成膜a-ITO層之後,進行圖案化而轉化為p-ITO層。 Further, p-ITO can be obtained not only by heat-treating a-ITO, but also by directly forming a p-ITO by a film forming apparatus. However, when p-ITO is directly formed, the flatness of the film is liable to be lowered due to the growth of crystal grains in the film formation, or pinholes between crystals are likely to occur. When the flatness of the film is lowered, the organic EL element 20 is easily damaged by the short circuit between the first electrode 21 and the second electrode 31. Further, when a pinhole is formed, an etching solution, a developing solution, or the like penetrates from the pinhole, and the film of the lower layer is damaged. Therefore, the p-ITO layer is desirably patterned into a p-ITO layer after film formation of the a-ITO layer.

又,如圖1(b)~(j)所示,第1電極21係藉由使用適於電極層材料之蝕刻液而形成為錐狀。藉由將第1電極21形成為錐狀,不易發生第1電極21中之各層之膜剝落或膜破裂。 Further, as shown in FIGS. 1(b) to 1(j), the first electrode 21 is formed in a tapered shape by using an etching liquid suitable for the electrode layer material. By forming the first electrode 21 into a tapered shape, film peeling or film breakage of each layer in the first electrode 21 is less likely to occur.

於專利文獻3中,將反射電極層圖案化之後,對第1及第3子像素成膜具有結晶性之ITO並將其圖案化。然而,具有結晶性之ITO相對於反射電極層之蝕刻中使用之蝕刻液之溶解性較高。 In Patent Document 3, after patterning the reflective electrode layer, crystalline ITO is formed on the first and third sub-pixels and patterned. However, the solubility of the crystalline ITO with respect to the etching liquid used for etching the reflective electrode layer is high.

因此,若於反射電極層上直接成膜具有結晶性之ITO層並藉由光微影術而將其圖案化,則有反射電極層不為錐狀之虞。 Therefore, if a crystalline ITO layer is directly formed on the reflective electrode layer and patterned by photolithography, the reflective electrode layer is not tapered.

另一方面,若為了避免上述問題點而分別將反射電極層與具有結晶性之ITO層圖案化,則光微影術之次數增加。 On the other hand, if the reflective electrode layer and the crystalline ITO layer are respectively patterned in order to avoid the above problem, the number of photolithography increases.

然而,根據本實施形態,由於如上述般成膜a-ITO層110.112並將其與反射電極層111一併圖案化,然後,將a- ITO層110.112轉化為p-ITO層113.114,故亦不會產生如上所述之問題。 However, according to the present embodiment, since the a-ITO layer 110.112 is formed as described above and patterned together with the reflective electrode layer 111, then, a- The ITO layer 110.112 is converted to the p-ITO layer 113.114, so that the problem as described above is not caused.

<光微影術之變化例> <Changes in photomicrography>

再者,於本實施形態中,列舉如下之情形為例進行了說明:如圖1(g)所示,使a-ITO層117之膜厚小於p-ITO層116之膜厚(即子像素71R中之光徑長73R),於圖1(h)所示之步驟中藉由蝕刻而將子像素71R中之a-ITO層117去除。 Further, in the present embodiment, a case has been described as an example in which the film thickness of the a-ITO layer 117 is made smaller than the film thickness of the p-ITO layer 116 (i.e., sub-pixels) as shown in Fig. 1(g). The optical path length of the 71R is 73R), and the a-ITO layer 117 in the sub-pixel 71R is removed by etching in the step shown in FIG. 1(h).

然而,本實施形態並不限定於此。於在圖1(g)所示之步驟中對子像素71R.71G之兩者形成抗蝕圖案,在圖1(h)所示之步驟中不將子像素71R中之a-ITO層117蝕刻去除而直接殘留之情形時,並不一定需要將a-ITO層117之膜厚設定為小於p-ITO層116之膜厚。 However, the embodiment is not limited to this. In the step shown in Figure 1 (g) for the sub-pixel 71R. When both of 71G form a resist pattern, the a-ITO layer is not necessarily required when the a-ITO layer 117 in the sub-pixel 71R is not removed by etching in the step shown in FIG. 1(h). The film thickness of 117 is set to be smaller than the film thickness of the p-ITO layer 116.

於此情形時,於子像素71R.71G分別形成使a-ITO層117結晶化而成之相同膜厚之p-ITO層118。 In this case, in the sub-pixel 71R. Each of 71G forms a p-ITO layer 118 having the same film thickness which is obtained by crystallizing the a-ITO layer 117.

然而,於本實施形態中,於圖1(d)所示之步驟中僅對子像素71R形成抗蝕圖案202R,藉此,如圖1(e)所示,將子像素71R以外之a-ITO層115去除,而僅於子像素71R堆積有a-ITO層115。 However, in the present embodiment, only the resist pattern 202R is formed on the sub-pixel 71R in the step shown in FIG. 1(d), whereby a- other than the sub-pixel 71R is shown in FIG. 1(e). The ITO layer 115 is removed, and only the a-ITO layer 115 is deposited on the sub-pixel 71R.

因此,根據本實施形態,以獲得所期望之光徑長73B之方式設定a-ITO層112之膜厚,將a-ITO層117之膜厚設定為自所期望之光徑長73G中減去a-ITO層112之膜厚(換言之,p-ITO層114之膜厚)所得之膜厚,將a-ITO層115之膜厚設定為自所期望之光徑長73R中減去a-ITO層112之膜厚與a-ITO層117之膜厚所得之膜厚,藉此,可任意且容易地設定.變 更各子像素71R.71G.71B之光徑長73R.73G.73B。 Therefore, according to the present embodiment, the film thickness of the a-ITO layer 112 is set so as to obtain the desired optical path length 73B, and the film thickness of the a-ITO layer 117 is set to be subtracted from the desired optical path length 73G. The film thickness of the film thickness of the a-ITO layer 112 (in other words, the film thickness of the p-ITO layer 114) is set such that the film thickness of the a-ITO layer 115 is subtracted from the desired optical path length 73R by a-ITO. The film thickness of the layer 112 and the film thickness of the a-ITO layer 117 can be arbitrarily and easily set. change More sub-pixels 71R. 71G. 71B's light path length is 73R. 73G. 73B.

再者,於本實施形態中,作為具體例,列舉將a-ITO層112(p-ITO層114)之電極厚度設為20 nm,將a-ITO層115(p-ITO層116)之電極厚度設為80 nm,將a-ITO層117(p-ITO層118)之電極厚度設為40 nm之情形為例進行了說明,但上述具體例始終只是一例,本實施形態並不限定於此。 Further, in the present embodiment, as an example, the electrode of the a-ITO layer 112 (p-ITO layer 114) is set to have an electrode thickness of 20 nm, and the electrode of the a-ITO layer 115 (p-ITO layer 116) is used. The thickness is 80 nm, and the case where the electrode thickness of the a-ITO layer 117 (p-ITO layer 118) is 40 nm has been described as an example. However, the above specific example is always an example, and the embodiment is not limited thereto. .

例如,亦可根據有機EL層43之膜厚設計等設計,而進一步增大a-ITO層112(p-ITO層114)之電極厚度。 For example, the electrode thickness of the a-ITO layer 112 (p-ITO layer 114) can be further increased according to the design of the film thickness of the organic EL layer 43 or the like.

<有機EL元件20之密封方法之變化例> <Modification of Sealing Method of Organic EL Element 20>

又,於本實施形態中,如上所述,列舉如下之情形為例進行了說明:藉由於有機EL元件20上形成含有乾燥劑之接著性之填充樹脂層42,而進行支撐基板10與密封基板50之貼合以及有機EL元件20之封入。 In the present embodiment, as described above, the case where the support substrate 10 and the sealing substrate are formed by forming the filling resin layer 42 containing the desiccant on the organic EL element 20 has been described as an example. The bonding of 50 and the sealing of the organic EL element 20.

然而,本實施形態並不限定於此。亦可代替於由支撐基板10、密封基板50及密封樹脂層41所包圍之空間內填充密封樹脂,而設為於上述空間內封入有惰性氣體之中空構造。又,除此以外,亦可具有於中空構造內塗佈或貼附有乾燥劑之構造。然而,於自密封基板50側射出光之情形時,必需使光不被乾燥劑遮蔽。 However, the embodiment is not limited to this. Instead of the sealing resin filled in the space surrounded by the support substrate 10, the sealing substrate 50, and the sealing resin layer 41, a hollow structure in which an inert gas is sealed in the space may be used. Further, in addition to this, a structure in which a desiccant is applied or attached to a hollow structure may be provided. However, when light is emitted from the side of the self-sealing substrate 50, it is necessary to shield the light from the desiccant.

又,於本實施形態中,列舉具有於支撐基板10上依序設置有有機EL元件20及密封樹脂層41、填充樹脂層42、密封基板50之構成之情形為例進行了說明。然而,本實施形態並不限定於此。 In the present embodiment, a configuration in which the organic EL element 20, the sealing resin layer 41, the filling resin layer 42, and the sealing substrate 50 are sequentially provided on the support substrate 10 has been described as an example. However, the embodiment is not limited to this.

例如,為了進一步提高有機EL元件20之密封性能,亦可 於有機EL元件20上積層未圖示之無機膜或有機.無機之混合積層膜等。 For example, in order to further improve the sealing performance of the organic EL element 20, An inorganic film (not shown) or an organic layer is laminated on the organic EL element 20. Inorganic mixed laminated film, etc.

進而,若僅藉由無機膜或有機.無機之混合積層膜等而有機EL元件20之密封性能充分,則亦可省略密封樹脂層41或密封基板50、填充樹脂層42。 Furthermore, if only by inorganic film or organic. In the inorganic mixed laminated film or the like and the sealing performance of the organic EL element 20 is sufficient, the sealing resin layer 41, the sealing substrate 50, and the filling resin layer 42 may be omitted.

又,於本實施形態中,列舉經由形成為框狀之密封樹脂層41而將支撐基板10與密封基板50貼合,藉此進行有機EL元件20之密封之情形為例進行了說明。 In the present embodiment, the case where the support substrate 10 and the sealing substrate 50 are bonded together via the sealing resin layer 41 formed in a frame shape, and the organic EL element 20 is sealed is described as an example.

然而,有機EL元件20之密封方法並不限定於此,例如亦可代替密封樹脂而將粉狀玻璃(粉末玻璃)形成為框狀,進行有機EL元件20之密封。 However, the sealing method of the organic EL element 20 is not limited thereto. For example, powder glass (powder glass) may be formed in a frame shape instead of the sealing resin, and the organic EL element 20 may be sealed.

<像素構成之變化例> <Example of change in pixel configuration>

又,於本實施形態中,列舉1個像素70包含R、G、B之3色之子像素71R.71G.71B之情形為例進行了說明。然而,本實施形態並不限定於此。1個像素70亦可包含青色(C)、紫紅色(M)、黃色(Y)等R、G、B以外之3色之子像素71。 Moreover, in the present embodiment, one pixel 70 includes three sub-pixels 71R of R, G, and B. 71G. The case of 71B is explained as an example. However, the embodiment is not limited to this. The one pixel 70 may include sub-pixels 71 of three colors other than R, G, and B such as cyan (C), magenta (M), and yellow (Y).

又,例如,亦可包含對R、G、B添加Y等之4色之子像素71等4色以上之子像素71。 Further, for example, sub-pixels 71 of four or more colors such as sub-pixels 71 of four colors such as Y may be added to R, G, and B.

根據本實施形態,如上所述,利用成為下層之p-ITO(第1透明電極層)與其上層之a-ITO層(第2透明電極層)之蝕刻選擇性之差異,進行例如各色單層中之透明電極層之堆積,藉此可對任意之子像素71形成任意膜厚之透明電極層。 According to the present embodiment, as described above, the difference in etching selectivity between the lower p-ITO (first transparent electrode layer) and the upper a-ITO layer (second transparent electrode layer) is performed, for example, in each color single layer. The deposition of the transparent electrode layers allows a transparent electrode layer of any thickness to be formed on any of the sub-pixels 71.

再者,於本實施形態中,反射電極層111上之透明電極 層之積層數並無特別限定,可任意設定。 Furthermore, in the present embodiment, the transparent electrode on the reflective electrode layer 111 The number of layers in the layer is not particularly limited and can be arbitrarily set.

於任一情形時,根據本實施形態,若與積層相同數量之透明電極層之情形相比,則可利用次數少於先前之光微影術,於顯示色不同之子像素間,變更反射電極層上之透明電極層之積層數或合計膜厚。 In either case, according to the present embodiment, if the number of transparent electrode layers is the same as that of the laminated layer, the number of available times is less than that of the previous photolithography, and the reflective electrode layer is changed between sub-pixels having different display colors. The number of layers of the transparent electrode layer or the total film thickness.

又,於本實施形態中,如上所述,列舉於各子像素71形成有TFT12之主動矩陣型之有機EL顯示裝置100為例。然而,本實施形態並不限定於此,只要不受有機EL元件20之驅動方式影響,則亦可將本發明應用於未形成有TFT之被動矩陣型之有機EL顯示裝置之製造。 Further, in the present embodiment, as described above, the active matrix type organic EL display device 100 in which the TFTs 12 are formed in each of the sub-pixels 71 is exemplified. However, the present embodiment is not limited thereto, and the present invention can be applied to the manufacture of a passive matrix type organic EL display device in which a TFT is not formed, as long as it is not affected by the driving method of the organic EL element 20.

<有機EL層43之製作方法之變化例> <Variation of Manufacturing Method of Organic EL Layer 43>

又,於本實施形態中,列舉利用真空蒸鍍法製作有機EL層43之情形為例進行了說明。然而,勿庸置疑,有機EL層43之製作方法並不限定於此,亦可適當選擇.採用噴墨法、雷射轉印法等先前公知之有機膜之成膜方法。 Further, in the present embodiment, a case where the organic EL layer 43 is formed by a vacuum deposition method has been described as an example. However, it goes without saying that the manufacturing method of the organic EL layer 43 is not limited thereto, and may be appropriately selected. A film forming method of a conventionally known organic film such as an inkjet method or a laser transfer method is employed.

<顯示裝置之變化例> <Variation of display device>

又,於本實施形態中,作為本實施形態中製造之顯示裝置,列舉對發光元件使用有機EL元件之顯示裝置為例進行了說明。然而,本實施形態並不限定於此,亦可廣泛應用於使用可作為例如如無機EL元件般之微小共振器而構成之發光元件之顯示裝置。 In the display device manufactured in the present embodiment, a display device using an organic EL element for a light-emitting element has been described as an example. However, the present embodiment is not limited to this, and can be widely applied to a display device using a light-emitting element which can be configured as a minute resonator such as an inorganic EL element.

[實施形態2] [Embodiment 2]

若主要根據圖10(a)~(h)對本實施形態進行說明,則如下所述。 The present embodiment will be described mainly based on Figs. 10(a) to (h) as follows.

再者,於本實施形態中,主要對與實施形態1之不同點進行說明,對具有與實施形態1中使用之構成要素相同之功能之構成要素標註相同之編號,並省略其說明。 In the present embodiment, the differences from the first embodiment will be mainly described, and the same components as those having the same functions as those in the first embodiment will be denoted by the same reference numerals and will not be described.

本實施形態之有機EL顯示裝置100係第1電極21之積層構造及步驟S2所示之第1電極21之製作方法與實施形態1不同,除此以外,與實施形態1相同。因此,於本實施形態中,對步驟S2所示之第1電極21之其他製作方法及積層構造進行說明。 In the organic EL display device 100 of the present embodiment, the laminated structure of the first electrode 21 and the method of fabricating the first electrode 21 shown in the step S2 are different from those of the first embodiment, and the same as the first embodiment. Therefore, in the present embodiment, another manufacturing method and laminated structure of the first electrode 21 shown in step S2 will be described.

<第1電極21之製作方法> <Method of Manufacturing First Electrode 21>

圖10(a)~(h)係按步驟表示自步驟S2所示之頂部發光型之有機EL顯示裝置100中之第1電極21之製作直至步驟S3所示之邊罩之製作為止之步驟之一例的剖面圖。 Figs. 10(a) to 10(h) are steps showing steps from the production of the first electrode 21 in the top emission type organic EL display device 100 shown in the step S2 to the production of the side mask shown in the step S3. A cross-sectional view of an example.

於本實施形態中,圖10(a)~(c)所示之步驟係與圖1(a)~(c)所示之步驟相同。因此,對圖10(a)~(c)所示之步驟省略說明。 In the present embodiment, the steps shown in Figs. 10(a) to (c) are the same as those shown in Figs. 1(a) to 1(c). Therefore, the description of the steps shown in Figs. 10(a) to (c) will be omitted.

於本實施形態中,於圖10(c)所示之步驟後,如圖10(d)所示,於上述支撐基板10上,以覆蓋上述p-ITO層113、反射電極層111及p-ITO層114(第1透明電極層)之方式,藉由例如濺鍍而成膜作為透明電極層之IZO層131(第2透明電極層)。 In the present embodiment, after the step shown in FIG. 10(c), as shown in FIG. 10(d), the p-ITO layer 113, the reflective electrode layer 111, and the p- are covered on the support substrate 10. In the ITO layer 114 (first transparent electrode layer), for example, an IZO layer 131 (second transparent electrode layer) as a transparent electrode layer is formed by sputtering.

IZO層131之膜厚設定為例如20~60 nm。於本實施形態中,成膜膜厚40 nm之IZO層131。 The film thickness of the IZO layer 131 is set to, for example, 20 to 60 nm. In the present embodiment, an IZO layer 131 having a film thickness of 40 nm is formed.

繼而,如圖10(d)所示,於子像素71R中之IZO層131上,藉由光微影術,以俯視時覆蓋上述p-ITO層113、反射電極 層111及p-ITO層114之方式形成抗蝕圖案202R。 Then, as shown in FIG. 10(d), on the IZO layer 131 in the sub-pixel 71R, the p-ITO layer 113 and the reflective electrode are covered in plan view by photolithography. The resist pattern 202R is formed in the form of the layer 111 and the p-ITO layer 114.

然後,將抗蝕圖案202R作為遮罩,使用蝕刻液,對未由抗蝕圖案202R遮罩之IZO層131進行濕式蝕刻之後,藉由抗蝕劑剝離液而剝離清洗抗蝕圖案202R。 Then, the resist pattern 202R is used as a mask, and the IZO layer 131 not covered by the resist pattern 202R is wet-etched using an etching solution, and then the cleaning resist pattern 202R is peeled off by the resist stripping solution.

再者,對於上述蝕刻液及剝離液,可使用與圖1(e)所示之蝕刻步驟中使用之蝕刻液及剝離液相同之蝕刻液及剝離液。對於上述蝕刻液,使用例如草酸。藉此,可選擇性地對IZO層131進行蝕刻。 Further, as the etching liquid and the peeling liquid, the etching liquid and the peeling liquid which are the same as the etching liquid and the peeling liquid used in the etching step shown in Fig. 1(e) can be used. For the above etching liquid, for example, oxalic acid is used. Thereby, the IZO layer 131 can be selectively etched.

此時,p-ITO層113.114及反射電極層111未被上述蝕刻液(草酸)蝕刻或蝕刻速度明顯較慢。因此,p-ITO層113.114及反射電極層111係藉由上述蝕刻未被去除而殘留。 At this time, the p-ITO layer 113.114 and the reflective electrode layer 111 are not etched by the above etching liquid (oxalic acid) or the etching rate is remarkably slow. Therefore, the p-ITO layer 113.114 and the reflective electrode layer 111 remain without being removed by the above etching.

藉此,如圖10(e)所示,僅將由抗蝕圖案202R遮罩之子像素71R之IZO層131以外之IZO層131去除。 Thereby, as shown in FIG. 10(e), only the IZO layer 131 other than the IZO layer 131 of the sub-pixel 71R masked by the resist pattern 202R is removed.

繼而,如圖10(f)所示,於上述支撐基板10上,以覆蓋各子像素71R.71G.71B中之各透明電極層及反射電極層111之方式,藉由例如濺鍍而成膜作為透明電極層之IZO層132。 Then, as shown in FIG. 10(f), on the support substrate 10, to cover each sub-pixel 71R. 71G. In the manner of each of the transparent electrode layer and the reflective electrode layer 111 in the 71B, the IZO layer 132 as a transparent electrode layer is formed by, for example, sputtering.

IZO層132之膜厚設定為例如20~60 nm。於本實施形態中,將IZO層132之膜厚設為40 nm。 The film thickness of the IZO layer 132 is set to, for example, 20 to 60 nm. In the present embodiment, the film thickness of the IZO layer 132 is set to 40 nm.

繼而,如圖10(f)所示,於子像素71R.71G中之IZO層132上,藉由光微影術,以俯視時覆蓋經圖案化之上述各透明電極層及反射電極層111之方式形成抗蝕圖案203R.203G。 Then, as shown in FIG. 10(f), in the sub-pixel 71R. The resist pattern 203R is formed on the IZO layer 132 of the 71G by means of photolithography to cover the patterned transparent electrode layer and the reflective electrode layer 111 in plan view. 203G.

此時,抗蝕圖案203G係以俯視時覆蓋反射電極層111之下層之p-ITO層113之圖案端部之方式形成為較子像素71R.71G中之p-ITO層113之圖案寬。 At this time, the resist pattern 203G is formed to be closer to the sub-pixel 71R so as to cover the end portion of the pattern of the p-ITO layer 113 under the reflective electrode layer 111 in plan view. The pattern of the p-ITO layer 113 in the 71G is wide.

再者,俯視時抗蝕圖案203G自p-ITO層113之圖案端部起之突出量係與抗蝕圖案202R相同,分別設定為2 μm。 In addition, the amount of protrusion of the resist pattern 203G from the pattern end portion of the p-ITO layer 113 in the plan view is the same as that of the resist pattern 202R, and is set to 2 μm.

又,抗蝕圖案203R係以俯視時覆蓋IZO層131之圖案端部之方式,形成為較子像素71R.71G中之IZO層131之圖案寬。 Moreover, the resist pattern 203R is formed so as to cover the end portion of the pattern of the IZO layer 131 in a plan view, and is formed to be smaller than the sub-pixel 71R. The pattern of the IZO layer 131 in the 71G is wide.

再者,俯視時抗蝕圖案203G自IZO層131之圖案端部起之突出量分別設定為2 μm。 Further, the amount of protrusion of the resist pattern 203G from the pattern end portion of the IZO layer 131 in plan view was set to 2 μm, respectively.

然後,將抗蝕圖案203R.203G作為遮罩,使用蝕刻液,如圖10(g)所示,對未由抗蝕圖案203R.203G遮罩之IZO層132進行濕式蝕刻之後,藉由抗蝕劑剝離液而剝離清洗抗蝕圖案203R.203G。 Then, the resist pattern 203R. 203G as a mask, using an etchant, as shown in Figure 10 (g), the pair is not by the resist pattern 203R. After the 203G mask IZO layer 132 is wet etched, the cleaning resist pattern 203R is peeled off by the resist stripping solution. 203G.

再者,對於上述蝕刻液及剝離液,可使用與圖10(e)所示之蝕刻中使用之蝕刻液及剝離液相同之蝕刻液及剝離液。藉此,可選擇性地對IZO層132進行蝕刻。 Further, as the etching liquid and the peeling liquid, the etching liquid and the peeling liquid which are the same as the etching liquid and the peeling liquid used for the etching shown in FIG. 10(e) can be used. Thereby, the IZO layer 132 can be selectively etched.

此時,如上所述,p-ITO層113.114及反射電極層111未被上述蝕刻液(草酸)蝕刻或蝕刻速度明顯較慢。因此,p-ITO層113.114及反射電極層111係藉由上述蝕刻未被去除而殘留。 At this time, as described above, the p-ITO layer 113.114 and the reflective electrode layer 111 are not etched by the above etching liquid (oxalic acid) or the etching rate is remarkably slow. Therefore, the p-ITO layer 113.114 and the reflective electrode layer 111 remain without being removed by the above etching.

藉此,如圖10(g)所示,僅將由抗蝕圖案203R.203G遮罩之子像素71R.71G之IZO層132以外之IZO層132去除。 Thereby, as shown in FIG. 10(g), only the resist pattern 203R will be used. 203G mask sub-pixel 71R. The IZO layer 132 other than the 71G IZO layer 132 is removed.

藉此,如圖10(g)所示,於子像素71R形成反射電極層111由作為反射電極層111之下層之透明電極層之p-ITO層113與作為反射電極層111之上層之透明電極層之p-ITO層114及IZO層131.132包圍之第1電極21。 Thereby, as shown in FIG. 10(g), the reflective electrode layer 111 is formed on the sub-pixel 71R by the p-ITO layer 113 which is a transparent electrode layer below the reflective electrode layer 111 and the transparent electrode which is the upper layer of the reflective electrode layer 111. The p-ITO layer 114 of the layer and the first electrode 21 surrounded by the IZO layer 131.132.

又,於子像素71G形成反射電極層111由作為反射電極層111之下層之透明電極層之p-ITO層113與作為反射電極層111之上層之透明電極層之p-ITO層114及IZO層132包圍之第1電極21。 Further, the p-ITO layer 113 having the reflective electrode layer 111 as the transparent electrode layer under the reflective electrode layer 111 and the p-ITO layer 114 and the IZO layer as the transparent electrode layer above the reflective electrode layer 111 are formed in the sub-pixel 71G. The first electrode 21 surrounded by 132.

又,於子像素71B形成反射電極層111由作為反射電極層111之下層之透明電極層之p-ITO層113與作為反射電極層111之上層之透明電極層之p-ITO層114夾持之第1電極21。 Further, the reflective electrode layer 111 is formed on the sub-pixel 71B by the p-ITO layer 113 which is a transparent electrode layer under the reflective electrode layer 111 and the p-ITO layer 114 which is a transparent electrode layer above the reflective electrode layer 111. The first electrode 21.

然後,如圖10(h)所示,於步驟S3中,於上述各子像素71R.71G.71B中之第1電極21上製作邊罩15。 Then, as shown in FIG. 10(h), in step S3, in each of the sub-pixels 71R. 71G. A side cover 15 is formed on the first electrode 21 of 71B.

於本實施形態中,作為反射電極層111之上層之透明電極層之p-ITO層114及IZO層131.132係作為形成微空腔之透明電極層121而發揮功能。 In the present embodiment, the p-ITO layer 114 and the IZO layer 131.132 which are transparent electrode layers on the upper surface of the reflective electrode layer 111 function as the transparent electrode layer 121 which forms the microcavity.

因此,於子像素71R中,以p-ITO層114及IZO層131.132之合計膜厚成為子像素71R之光徑長73R之方式設定p-ITO層114及IZO層131.132之膜厚。 Therefore, in the sub-pixel 71R, the film thickness of the p-ITO layer 114 and the IZO layer 131.132 is set such that the total thickness of the p-ITO layer 114 and the IZO layer 131.132 becomes the optical path length 73R of the sub-pixel 71R. .

又,於子像素71G中,作為反射電極層111之上層之透明電極層之p-ITO層114及IZO層132係作為形成微空腔之透明電極層121而發揮功能。 Further, in the sub-pixel 71G, the p-ITO layer 114 and the IZO layer 132 which are transparent electrode layers on the upper surface of the reflective electrode layer 111 function as the transparent electrode layer 121 which forms the microcavity.

因此,於子像素71G中,以p-ITO層114及IZO層132之合計膜厚成為子像素71G之光徑長73G之方式設定p-ITO層114及IZO層132之膜厚。 Therefore, in the sub-pixel 71G, the film thickness of the p-ITO layer 114 and the IZO layer 132 is set so that the total thickness of the p-ITO layer 114 and the IZO layer 132 becomes the optical path length 73G of the sub-pixel 71G.

又,於子像素71B中,作為反射電極層111之上層之透明電極層之p-ITO層114係作為形成微空腔之透明電極層121而發揮功能。 Further, in the sub-pixel 71B, the p-ITO layer 114 which is a transparent electrode layer above the reflective electrode layer 111 functions as a transparent electrode layer 121 which forms a microcavity.

因此,於子像素71B中,以p-ITO層114之膜厚成為子像素71G之光徑長73G之方式設定p-ITO層114之膜厚。 Therefore, in the sub-pixel 71B, the film thickness of the p-ITO layer 114 is set such that the film thickness of the p-ITO layer 114 becomes the optical path length 73G of the sub-pixel 71G.

如上所述,根據本實施形態,如上述般使a-ITO層112結晶化而將其轉化為p-ITO層114之後,於p-ITO層114上成膜IZO層作為耐蝕刻性低於p-ITO層114之透明電極層,藉由光微影術選擇性地對該IZO層進行蝕刻而將其圖案化,藉此,可對任意之子像素堆積IZO層。 As described above, according to the present embodiment, after the a-ITO layer 112 is crystallized and converted into the p-ITO layer 114 as described above, the IZO layer is formed on the p-ITO layer 114 as an etching resistance lower than p. The transparent electrode layer of the -ITO layer 114 is selectively etched by photolithography to pattern the IZO layer, whereby the IZO layer can be deposited on any of the sub-pixels.

藉此,可於至少2個子像素間變更透明電極層之積層數。 Thereby, the number of layers of the transparent electrode layer can be changed between at least two sub-pixels.

又,根據本實施形態,藉由重複進行成膜耐蝕刻性低於p-ITO層114之IZO層,並利用光微影術選擇性地對該IZO層進行蝕刻而將其圖案化之步驟,可對所期望之子像素堆積IZO層。 Further, according to the present embodiment, the IZO layer having a lower film forming etching resistance than the p-ITO layer 114 is repeatedly formed, and the IZO layer is selectively etched by photolithography to pattern the IZO layer. The IZO layer can be stacked on the desired sub-pixels.

<變化例> <variation>

然而,本實施形態並不限定於此,亦可具有於各子像素71R.71G.71B進一步積層有未圖示之p-ITO層或如IZO層般之透明電極層之構成。 However, the embodiment is not limited thereto, and may be provided in each sub-pixel 71R. 71G. 71B is further laminated with a p-ITO layer (not shown) or a transparent electrode layer such as an IZO layer.

例如,於本實施形態中,於圖10(d)所示之步驟中以單層積層IZO層131,但此時,亦可進行耐蝕刻性低於p-ITO層114之包含IZO層131之複數之透明電極層之成膜。 For example, in the present embodiment, the IZO layer 131 is laminated in a single layer in the step shown in FIG. 10(d). However, in this case, the IZO layer 131 may be formed to have lower etching resistance than the p-ITO layer 114. Film formation of a plurality of transparent electrode layers.

例如,於圖10(d)所示之步驟中,既可於IZO層131上進一步成膜a-ITO層之後,於子像素71R形成抗蝕圖案202R,亦可於IZO層131上進一步依序成膜a-ITO層及IZO層之後,於子像素71R形成抗蝕圖案202R。 For example, in the step shown in FIG. 10(d), after the a-ITO layer is further formed on the IZO layer 131, the resist pattern 202R is formed on the sub-pixel 71R, and the IZO layer 131 may be further sequentially processed. After the a-ITO layer and the IZO layer are formed, a resist pattern 202R is formed on the sub-pixel 71R.

再者,於如上述般形成a-ITO層作為耐蝕刻性低於p-ITO層114之透明電極層之情形時,如實施形態1般,於將抗蝕圖案202R作為遮罩之濕式蝕刻後,進行熱處理,將上述a-ITO層轉化為p-ITO層即可。 Further, when the a-ITO layer is formed as described above as a transparent electrode layer having lower etching resistance than the p-ITO layer 114, as in the first embodiment, the resist pattern 202R is used as a mask for wet etching. Thereafter, heat treatment is performed to convert the a-ITO layer into a p-ITO layer.

再者,勿庸置疑,相同之方法亦可應用於圖10(e)及圖10(f)所示之步驟,除此以外,勿庸置疑,藉由進一步於圖10(g)所示之步驟與圖10(h)所示之步驟之間,積層單層或複數層耐蝕刻性低於p-ITO層之層,以與上述相同之方式進行濕式蝕刻,可進一步堆積透明電極層。 Furthermore, it goes without saying that the same method can be applied to the steps shown in FIG. 10(e) and FIG. 10(f), and other than that, it is undoubtedly further shown by FIG. 10(g). Between the steps and the step shown in FIG. 10(h), the laminated single layer or the plurality of layers are less etch-resistant than the layer of the p-ITO layer, and wet etching is performed in the same manner as described above, whereby the transparent electrode layer can be further deposited.

於任一情形時,根據本實施形態,若與積層相同數量之透明電極層之情形相比,則可利用次數少於先前之光微影術,於顯示色不同之子像素間,變更反射電極層上之透明電極層之積層數或合計膜厚。 In either case, according to the present embodiment, if the number of transparent electrode layers is the same as that of the laminated layer, the number of available times is less than that of the previous photolithography, and the reflective electrode layer is changed between sub-pixels having different display colors. The number of layers of the transparent electrode layer or the total film thickness.

<效果> <effect>

於本實施形態中,利用含有多晶之透明電極材料之透明電極層與形成於該含有多晶之透明電極材料之透明電極層上之透明電極層之蝕刻選擇性之差異、例如如上所述p-ITO層與IZO層(及a-ITO層)之蝕刻選擇性之差異,進行透明電極層之堆積。 In the present embodiment, the difference in etching selectivity between the transparent electrode layer containing the polycrystalline transparent electrode material and the transparent electrode layer formed on the transparent electrode layer containing the polycrystalline transparent electrode material is, for example, as described above. The difference in etching selectivity between the ITO layer and the IZO layer (and the a-ITO layer) is performed to deposit the transparent electrode layer.

再者,於圖10(g)所示之例中,於子像素71R.71G分別形成有相同膜厚之IZO層132。 Furthermore, in the example shown in FIG. 10(g), the sub-pixel 71R. 71G is formed with an IZO layer 132 having the same film thickness.

然而,於本實施形態中,於圖10(d)所示之步驟中僅於子像素71R形成抗蝕圖案202R,藉此,如圖10(e)所示,將子像素71R以外之IZO層131去除,而僅於子像素71R堆積 有IZO層131。 However, in the present embodiment, the resist pattern 202R is formed only in the sub-pixel 71R in the step shown in FIG. 10(d), whereby the IZO layer other than the sub-pixel 71R is formed as shown in FIG. 10(e). 131 is removed, and only the sub-pixel 71R is stacked There is an IZO layer 131.

因此,根據本實施形態,以獲得所期望之光徑長73B之方式設定a-ITO層112之膜厚,將IZO層131之膜厚設定為自所期望之光徑長73G中減去a-ITO層112之膜厚(換言之,p-ITO層114之膜厚)所得之膜厚,將IZO層132之膜厚設定為自所期望之光徑長73R中減去a-ITO層112之膜厚與IZO層131之膜厚所得之膜厚,藉此,可任意且容易地設定.變更各子像素71R.71G.71B之光徑長73R.73G.73B。 Therefore, according to the present embodiment, the film thickness of the a-ITO layer 112 is set so as to obtain the desired optical path length 73B, and the film thickness of the IZO layer 131 is set to be subtracted from the desired optical path length 73G by a- The film thickness of the film thickness of the ITO layer 112 (in other words, the film thickness of the p-ITO layer 114) is set to a film thickness of the IZO layer 132 minus the film of the a-ITO layer 112 from the desired path length 73R. The film thickness of the film thickness of the thick and IZO layer 131 can be set arbitrarily and easily. Change each sub-pixel 71R. 71G. 71B's light path length is 73R. 73G. 73B.

因此,於本實施形態中,亦可利用2次光微影術,任意且容易地調整各子像素71R.71G.71B中之光徑長73R.73G.73B,而不會如專利文獻3般受光徑長之制約。 Therefore, in the present embodiment, each sub-pixel 71R can be arbitrarily and easily adjusted by secondary photolithography. 71G. The light path length in 71B is 73R. 73G. 73B, and is not restricted by the optical path length as in Patent Document 3.

因此,於本實施形態中,如圖10(d).(g)所示,作為為了針對每一子像素71R.71G.71B變更透明電極層之膜厚(積層數)而所需之光微影術之次數,可利用2次光微影術,針對每一子像素71任意且容易地變更第1電極21之厚度。 Therefore, in this embodiment, as shown in FIG. 10(d). (g) is shown as being for each sub-pixel 71R. 71G. 71B The number of photolithography required to change the film thickness (the number of layers) of the transparent electrode layer can be arbitrarily and easily changed the thickness of the first electrode 21 for each sub-pixel 71 by secondary photolithography.

又,於本實施形態中,如上所示,即便包含反射電極層111之蝕刻,亦可將光微影術之次數抑制為3次。而且,不會增加光微影術之次數,且亦可於光徑長最短之子像素71B之反射電極層111上形成p-ITO層114作為透明電極層。 Further, in the present embodiment, as described above, even if the etching of the reflective electrode layer 111 is included, the number of photolithography can be suppressed to three times. Further, the number of times of photolithography is not increased, and the p-ITO layer 114 can be formed as a transparent electrode layer on the reflective electrode layer 111 of the sub-pixel 71B having the shortest optical path length.

因此,可利用次數少於先前之光微影術,針對每一子像素71任意地變更第1電極21之膜厚、換言之、有機EL元件20之光徑長。 Therefore, the number of available times is smaller than that of the previous photolithography, and the film thickness of the first electrode 21, in other words, the optical path length of the organic EL element 20, is arbitrarily changed for each sub-pixel 71.

而且,根據本實施形態,可不將含有非結晶之透明電極材料之透明電極層轉化為含有多晶之透明電極材料之透明 電極層,而如上所述,利用含有多晶之透明電極材料之透明電極層與形成於該含有多晶之透明電極材料之透明電極層上之透明電極層之蝕刻選擇性之差異、例如如上所述p-ITO層與IZO層之蝕刻選擇性之差異,進行透明電極層之堆積。因此,可進一步縮短處理節拍。 Further, according to the present embodiment, the transparent electrode layer containing the amorphous transparent electrode material can be converted into a transparent material containing the polycrystalline transparent electrode material. An electrode layer, as described above, a difference in etching selectivity between a transparent electrode layer containing a polycrystalline transparent electrode material and a transparent electrode layer formed on the transparent electrode layer containing the polycrystalline transparent electrode material, for example, as described above The difference in etching selectivity between the p-ITO layer and the IZO layer is performed, and the deposition of the transparent electrode layer is performed. Therefore, the processing beat can be further shortened.

又,於本實施形態中,形成於反射電極層111之下層或上層之p-ITO層係藉由於a-ITO層之成膜步驟中,亦於源極線等信號線14之端子部上成膜a-ITO層,而可用作覆蓋源極線等信號線14之端子部之保護膜。 Further, in the present embodiment, the p-ITO layer formed on the lower layer or the upper layer of the reflective electrode layer 111 is formed on the terminal portion of the signal line 14 such as the source line by the film formation step of the a-ITO layer. The film a-ITO layer can be used as a protective film covering the terminal portion of the signal line 14 such as the source line.

又,對於積層於反射電極層111上之其他透明電極層,藉由將該等透明電極層積層於源極線等信號線14之端子部上,亦可用作覆蓋信號線14之端子部之保護膜。 Further, the other transparent electrode layer laminated on the reflective electrode layer 111 can be used as a terminal portion covering the signal line 14 by laminating the transparent electrode layers on the terminal portions of the signal lines 14 such as the source lines. Protective film.

[實施形態3] [Embodiment 3]

若主要根據圖11及圖12對本實施形態進行說明,則如下所述。 The present embodiment will be mainly described with reference to Figs. 11 and 12 as follows.

再者,於本實施形態中,主要對與實施形態1、2之不同點進行說明,對具有與實施形態1、2中使用之構成要素相同之功能之構成要素標註相同之編號,並省略其說明。 In the present embodiment, the differences from the first and second embodiments will be mainly described, and the same components as those of the components used in the first and second embodiments will be denoted by the same reference numerals, and the description will be omitted. Description.

圖11係表示本實施形態之有機EL顯示面板1之概略構成的剖面圖。再者,表示本實施形態之有機EL顯示裝置100之主要部分之概略構成的分解剖面圖與圖2相同,表示有機EL顯示裝置100中之支撐基板10之概略構成的俯視圖與圖3相同。又,表示支撐基板10中之顯示區域R1之主要部分之構成的俯視圖與圖4相同。圖11相當於表示沿圖4所示 之A-A線切斷有機EL顯示面板1時之有機EL顯示面板1之概略構成的剖面圖。 Fig. 11 is a cross-sectional view showing a schematic configuration of an organic EL display panel 1 of the present embodiment. In addition, the exploded cross-sectional view of the main part of the organic EL display device 100 of the present embodiment is the same as that of FIG. 2, and the plan view of the schematic configuration of the support substrate 10 in the organic EL display device 100 is the same as that of FIG. Further, a plan view showing a configuration of a main portion of the display region R1 in the support substrate 10 is the same as that of FIG. 4. Figure 11 is equivalent to showing the same as shown in Figure 4. A cross-sectional view showing a schematic configuration of the organic EL display panel 1 when the organic EL display panel 1 is cut by the A-A line.

於實施形態1、2中,如上所述,列舉藉由積層複數層發光層並使發光色重合而獲得W發光之情形為例進行了說明。 In the first and second embodiments, as described above, a case where a plurality of light-emitting layers are laminated and the luminescent colors are superimposed to obtain W luminescence has been described as an example.

然而,實施形態1、2所示之第1電極21之形成方法亦可同樣地應用於如下之情形:藉由使用針對發光層之每一種顏色進行蒸鍍之分塗方式,而於同一平面內形成發光色不同之複數層發光層。 However, the method of forming the first electrode 21 shown in the first and second embodiments can be similarly applied to the case where the coating method for vapor deposition for each color of the light-emitting layer is used in the same plane. A plurality of light-emitting layers having different luminescent colors are formed.

於使用分塗方式之全彩之有機EL顯示裝置100中,如圖11所示,設有例如RGB之各色之發光層82R.82G.82B之有機EL元件20係以子像素71R.71G.71B之形式排列形成於支撐基板10上。於如上所述之有機EL顯示裝置100中,使用TFT12,選擇性地使該等有機EL元件20以所期望之亮度發光,藉此進行彩色圖像顯示。 In the full-color organic EL display device 100 using the split coating method, as shown in FIG. 11, a light-emitting layer 82R of each color such as RGB is provided. 82G. The organic EL element 20 of 82B is sub-pixel 71R. 71G. The form of 71B is formed on the support substrate 10. In the organic EL display device 100 as described above, the TFTs 12 are selectively used to selectively emit the organic EL elements 20 at a desired luminance, thereby performing color image display.

於本實施形態中,藉由如此般於同一平面內形成發光色不同之複數層發光層82R.82G.82B,並且對發光色不同之各子像素71R.71G.71B導入微空腔構造,而如上所述,進行全彩之圖像顯示。 In this embodiment, a plurality of light-emitting layers 82R having different luminescent colors are formed in the same plane. 82G. 82B, and for each sub-pixel 71R with different illuminating colors. 71G. The 71B is introduced into the microcavity structure, and as described above, the full color image is displayed.

又,於本實施形態中,如圖11所示,藉由併用CF層52,亦可利用CF層52而調整自有機EL元件20射出之光之光譜。 Further, in the present embodiment, as shown in FIG. 11, by using the CF layer 52 in combination, the spectrum of light emitted from the organic EL element 20 can be adjusted by the CF layer 52.

如圖11所示,本實施形態之有機EL顯示裝置100係有機EL元件20中之有機EL層43之積層構造不同,除此以外, 具有與圖5所示之有機EL顯示裝置100相同之構成。 As shown in FIG. 11, the organic EL display device 100 of the present embodiment has a different laminated structure of the organic EL layer 43 in the organic EL element 20, and It has the same structure as the organic EL display device 100 shown in FIG.

以下,對本實施形態之有機EL元件20之構成進行說明。 Hereinafter, the configuration of the organic EL element 20 of the present embodiment will be described.

<有機EL元件20之構成> <Configuration of Organic EL Element 20>

於圖11所示之有機EL顯示裝置100中,具有如下之構成:於第1電極21與第2電極31之間,作為有機EL層43,而自第1電極21側起,依序形成有例如電洞注入層兼電洞傳輸層81、發光層82R.82G.82B、電子傳輸層兼電子注入層83。 In the organic EL display device 100 shown in FIG. 11, the organic EL layer 43 is formed between the first electrode 21 and the second electrode 31, and is formed in order from the first electrode 21 side. For example, the hole injection layer and the hole transport layer 81, the light-emitting layer 82R. 82G. 82B, an electron transport layer and an electron injection layer 83.

再者,關於電洞注入層兼電洞傳輸層及電子傳輸層兼電子注入層,係如實施形態1中說明所述,此處,省略電洞注入層兼電洞傳輸層81及電子傳輸層兼電子注入層83之說明。 Further, the hole injection layer and the hole transport layer and the electron transport layer and the electron injection layer are as described in the first embodiment, and the hole injection layer and the hole transport layer 81 and the electron transport layer are omitted here. The description of the electron injection layer 83 is also provided.

如圖11所示,電洞注入層兼電洞傳輸層81係以覆蓋第1電極21及邊罩15之方式,遍及支撐基板10中之顯示區域R1之整個表面而同樣地形成。 As shown in FIG. 11, the hole injection layer and the hole transport layer 81 are formed in the same manner over the entire surface of the display region R1 in the support substrate 10 so as to cover the first electrode 21 and the side cover 15.

於電洞注入層兼電洞傳輸層81上,分別對應於子像素71R.71G.71B而形成有發光層82R.82G.82B。 On the hole injection layer and the hole transmission layer 81, respectively corresponding to the sub-pixel 71R. 71G. 71B is formed with a light-emitting layer 82R. 82G. 82B.

發光層82R.82G.82B係使自第1電極21側注入之電洞與自第2電極31側注入之電子再結合而射出光。於本實施形態中,發光層82R.82G.82B亦分別由低分子螢光色素、金屬錯合物等發光效率較高之材料所形成。 Light emitting layer 82R. 82G. In the 82B system, the hole injected from the side of the first electrode 21 and the electron injected from the side of the second electrode 31 are recombined to emit light. In this embodiment, the light-emitting layer 82R. 82G. 82B is also formed by materials with high luminous efficiency such as low molecular weight fluorescent pigments and metal complexes.

電子傳輸層兼電子注入層83係以覆蓋發光層82R.82G.82B及電洞注入層兼電洞傳輸層81之方式,於該等發光層82R.82G.82B及電洞注入層兼電洞傳輸層81上遍 及支撐基板10中之顯示區域R1之整個表面而同樣地形成。 The electron transport layer and the electron injection layer 83 are arranged to cover the light emitting layer 82R. 82G. 82B and the hole injection layer and the hole transport layer 81 are in the manner of the light-emitting layer 82R. 82G. 82B and hole injection layer and hole transmission layer 81 And the entire surface of the display region R1 in the support substrate 10 is formed in the same manner.

再者,於本實施形態中,如上所述,列舉設置有電洞注入層兼電洞傳輸層81作為電洞注入層及電洞傳輸層之情形為例而進行圖示,並且列舉設置有電子傳輸層兼電子注入層83作為電子傳輸層及電子注入層之情形為例而進行圖示。然而,本實施形態並不限定於此,電洞注入層與電洞傳輸層亦可作為相互獨立之層而形成。同樣地,電子傳輸層與電子注入層亦可作為相互獨立之層而形成。 In the present embodiment, as described above, the case where the hole injection layer and the hole transport layer 81 are provided as the hole injection layer and the hole transport layer is exemplified, and the electrons are provided. The case where the transport layer and the electron injection layer 83 are used as the electron transport layer and the electron injection layer is illustrated as an example. However, the present embodiment is not limited thereto, and the hole injection layer and the hole transport layer may be formed as separate layers. Similarly, the electron transport layer and the electron injection layer may be formed as separate layers.

再者,發光層82R.82G.82B以外之有機層並非為有機EL層43所必需之層,根據所要求之有機EL元件20之特性適當形成即可。 Furthermore, the light-emitting layer 82R. 82G. The organic layer other than 82B is not a layer necessary for the organic EL layer 43, and may be appropriately formed according to the characteristics of the desired organic EL element 20.

又,如電洞注入層兼電洞傳輸層81及電子傳輸層兼電子注入層83般,一個層亦可具有複數之功能。 Further, as with the hole injection layer and the hole transport layer 81 and the electron transport layer and the electron injection layer 83, one layer may have a plurality of functions.

又,亦可視需要,對有機EL層43追加載子阻擋層。例如,藉由於發光層82R.82G.82B與電子傳輸層兼電子注入層83之間追加電洞阻擋層作為載子阻擋層,可阻止電洞穿過電子傳輸層兼電子注入層83,而提高發光效率。 Further, the organic EL layer 43 may be chased by the sub-blocking layer as needed. For example, by the light-emitting layer 82R. 82G. A hole blocking layer is added between the 82B and the electron transport layer and the electron injecting layer 83 as a carrier blocking layer, which prevents the holes from passing through the electron transporting layer and the electron injecting layer 83, thereby improving luminous efficiency.

於本實施形態中,適當插入第1電極21(陽極)、第2電極31(陰極)及發光層82R.82G.82B以外之層即可。 In the present embodiment, the first electrode 21 (anode), the second electrode 31 (cathode), and the light-emitting layer 82R are appropriately inserted. 82G. The layer other than 82B can be.

作為上述有機EL元件20之構成,可採用例如如下述(1)~(8)所示之層構成。 As the configuration of the organic EL element 20, for example, a layer configuration as shown in the following (1) to (8) can be employed.

(1)第1電極/發光層/第2電極 (1) First electrode/light emitting layer/second electrode

(2)第1電極/電洞傳輸層/發光層/電子傳輸層/第2電極 (2) First electrode/hole transport layer/light-emitting layer/electron transport layer/second electrode

(3)第1電極/電洞傳輸層/發光層/電洞阻擋層/電子傳輸層/ 第2電極 (3) 1st electrode/hole transport layer/light emitting layer/hole blocking layer/electron transport layer/ Second electrode

(4)第1電極/電洞傳輸層/發光層/電洞阻擋層/電子傳輸層/電子注入層/第2電極 (4) First electrode/hole transport layer/light-emitting layer/hole barrier layer/electron transport layer/electron injection layer/second electrode

(5)第1電極/電洞注入層/電洞傳輸層/發光層/電子傳輸層/電子注入層/第2電極 (5) First electrode/hole injection layer/hole transmission layer/light-emitting layer/electron transport layer/electron injection layer/second electrode

(6)第1電極/電洞注入層/電洞傳輸層/發光層/電洞阻擋層/電子傳輸層/第2電極 (6) First electrode/hole injection layer/hole transmission layer/light-emitting layer/hole barrier layer/electron transport layer/second electrode

(7)第1電極/電洞注入層/電洞傳輸層/發光層/電洞阻擋層/電子傳輸層/電子注入層/第2電極 (7) First electrode/hole injection layer/hole transmission layer/light-emitting layer/hole blocking layer/electron transport layer/electron injection layer/second electrode

(8)第1電極/電洞注入層/電洞傳輸層/電子阻擋層/發光層/電洞阻擋層/電子傳輸層/電子注入層/第2電極 (8) First electrode/hole injection layer/hole transmission layer/electron barrier layer/light-emitting layer/hole barrier layer/electron transport layer/electron injection layer/second electrode

再者,於本實施形態中,上述積層順序亦將第1電極21設為陽極,將第2電極31設為陰極。於本實施形態中,於將第1電極21設為陰極,將第2電極31設為陽極之情形時,有機EL層43之積層順序亦反轉。 Further, in the present embodiment, the first electrode 21 is also an anode and the second electrode 31 is a cathode. In the present embodiment, when the first electrode 21 is a cathode and the second electrode 31 is an anode, the order of lamination of the organic EL layer 43 is reversed.

<有機EL顯示裝置100之製造方法> <Method of Manufacturing Organic EL Display Device 100>

繼而,對本實施形態之有機EL顯示裝置100之製造方法進行說明。 Next, a method of manufacturing the organic EL display device 100 of the present embodiment will be described.

於本實施形態中,有機EL顯示裝置100之製造步驟之流程之概要亦如使用圖7進行說明所述。再者,於本實施形態中,於將第1電極21設為陰極,將第2電極31設為陽極之情形時,於第1電極21與第2電極31中,其材料以及厚度亦反轉。 In the present embodiment, the outline of the flow of the manufacturing steps of the organic EL display device 100 is also described using FIG. In the present embodiment, when the first electrode 21 is a cathode and the second electrode 31 is an anode, the material and thickness of the first electrode 21 and the second electrode 31 are reversed. .

以下,列舉具有圖11所示之構成之有機EL顯示裝置100 為例,對步驟S4中之圖7所示之有機EL層43之製作步驟之流程之概要進行說明。 Hereinafter, an organic EL display device 100 having the configuration shown in FIG. 11 will be listed. As an example, an outline of the flow of the manufacturing steps of the organic EL layer 43 shown in FIG. 7 in the step S4 will be described.

<有機EL層43之製作步驟之流程> <Flow of Production Step of Organic EL Layer 43>

圖12係按步驟表示圖11所示之有機EL層43之製作步驟之一例的流程圖。 Fig. 12 is a flow chart showing an example of the steps of producing the organic EL layer 43 shown in Fig. 11 in steps.

於本實施形態中,首先,於圖7所示之步驟S4中,對實施了用於脫水之減壓烘烤及作為第1電極21之表面清洗之氧電漿處理之支撐基板10,如圖12所示,首先,以覆蓋第1電極21及邊罩15之方式,於支撐基板10之顯示區域R1之整個表面,利用真空蒸鍍法而圖案形成電洞注入層兼電洞傳輸層81(電洞注入層.電洞傳輸層)(步驟S31)。 In the present embodiment, first, in the step S4 shown in FIG. 7, the support substrate 10 subjected to decompression baking for dehydration and oxygen plasma treatment as the surface cleaning of the first electrode 21 is as shown in the drawing. As shown in FIG. 12, first, the hole injection layer and the hole transport layer 81 are patterned by vacuum deposition on the entire surface of the display region R1 of the support substrate 10 so as to cover the first electrode 21 and the side cover 15 ( Hole injection layer. Hole transport layer) (step S31).

再者,如上所述,電洞注入層兼電洞傳輸層81係遍及支撐基板10中之顯示區域R1之整個表面而同樣地形成。因此,與實施形態1中之電洞注入層22及電洞傳輸層23同樣地,將顯示區域R1之整個表面開口之開放遮罩用作蒸鍍用之遮罩而進行成膜。 Further, as described above, the hole injection layer and the hole transport layer 81 are formed in the same manner over the entire surface of the display region R1 in the support substrate 10. Therefore, similarly to the hole injection layer 22 and the hole transport layer 23 in the first embodiment, the open mask having the entire surface opening of the display region R1 is used as a mask for vapor deposition to form a film.

另一方面,於如本實施形態般使用分塗方式之全彩之有機EL顯示裝置100中,如上所述,使用TFT12而選擇性地使有機EL元件20以所期望之亮度發光,藉此進行彩色圖像顯示。 On the other hand, in the organic EL display device 100 of the full-color coating system using the coating method, as described above, the organic EL element 20 is selectively used to emit light with a desired luminance by using the TFT 12 as described above. Color image display.

因此,為了製造上述有機EL顯示裝置100,必需針對每一有機EL元件20以特定之圖案而成膜含有發出各色之光之有機發光材料之發光層82R.82G.82B。 Therefore, in order to manufacture the above-described organic EL display device 100, it is necessary to form a light-emitting layer 82R containing an organic light-emitting material emitting light of each color in a specific pattern for each organic EL element 20. 82G. 82B.

因此,對於發光層82R.82G.82B之成膜,將僅使所期望 之顯示色之發光材料蒸鍍之區域開口之精準遮罩用作蒸鍍用之遮罩,利用真空蒸鍍法而進行分塗蒸鍍(步驟S32)。藉此,形成與各子像素71R.71G.71B相對應之圖案膜。 Therefore, for the light-emitting layer 82R. 82G. Film formation of 82B will only make the desired The precise mask of the opening of the region in which the light-emitting material of the display color is vapor-deposited is used as a mask for vapor deposition, and is subjected to partial vapor deposition by a vacuum deposition method (step S32). Thereby, formed with each sub-pixel 71R. 71G. 71B corresponds to the pattern film.

然後,於形成有發光層82R.82G.82B之支撐基板10上,將顯示區域R1之整個表面開口之開放遮罩用作蒸鍍用之遮罩,利用真空蒸鍍法,依序於像素區域整個表面形成電子傳輸層兼電子注入層83(電子傳輸層.電子注入層)(步驟S33)、第2電極31(步驟S5)。 Then, a light-emitting layer 82R is formed. 82G. On the support substrate 10 of the 82B, an open mask having the entire surface opening of the display region R1 is used as a mask for vapor deposition, and an electron transport layer and an electron injection layer 83 are sequentially formed on the entire surface of the pixel region by vacuum evaporation. (Electron Transport Layer. Electron Injection Layer) (Step S33) and Second Electrode 31 (Step S5).

再者,於本實施形態中,對於上述蒸鍍,可使用與先前相同之真空蒸鍍裝置。再者,對於較佳之真空極限率等條件,係如實施形態1中說明所述。因此,對真空蒸鍍裝置以及蒸鍍方法之詳細情況省略說明以及圖示。 Further, in the present embodiment, the vacuum vapor deposition apparatus similar to the prior art can be used for the vapor deposition. Further, conditions such as a preferable vacuum limit rate are as described in the first embodiment. Therefore, the detailed description of the vacuum vapor deposition apparatus and the vapor deposition method will be omitted.

又,於本實施形態中,作為用作電洞注入層兼電洞傳輸層81及電子傳輸層兼電子注入層83之電洞注入層兼電洞傳輸層及電子傳輸層兼電子注入層之材料以及膜厚,係如實施形態1中說明所述。 Further, in the present embodiment, the material of the hole injection layer and the hole transport layer and the electron transport layer and the electron injection layer which are used as the hole injection layer and the hole transport layer 81 and the electron transport layer and electron injection layer 83 are used. The film thickness is as described in the first embodiment.

又,對於用作發光層82R.82G.82B之發光層之材料,係如實施形態1中說明所述。再者,對於發光層82R.82G.82B,既可分別使用發光色不同之單一之材料,亦可使用以某材料為主體材料,將其他材料作為客體材料或摻雜劑而混入之混合材料。 Also, for use as the light-emitting layer 82R. 82G. The material of the light-emitting layer of 82B is as described in the first embodiment. Furthermore, for the light-emitting layer 82R. 82G. 82B, a single material having a different luminescent color may be used separately, or a mixed material in which another material is used as a host material and other materials are used as a guest material or a dopant may be used.

再者,作為此情形時之發光層82R.82G.82B之膜厚,為例如10~100 nm。 Furthermore, as the light-emitting layer 82R in this case. 82G. The film thickness of 82B is, for example, 10 to 100 nm.

於本實施形態中,如圖11所示,與實施形態1同樣地, 藉由將第1電極21設為反射電極層111與透明電極層121之積層構造,而對有機EL元件20導入微空腔構造。 In the present embodiment, as shown in FIG. 11, as in the first embodiment, By forming the first electrode 21 as a laminated structure of the reflective electrode layer 111 and the transparent electrode layer 121, the organic EL element 20 is introduced into a microcavity structure.

因此,於本實施形態中,將各發光層82R.82G.82B之膜厚設定為相同之膜厚。因此,以與實施形態1、2相同之方式設定光徑長73R.73G.73B。 Therefore, in the present embodiment, each of the light-emitting layers 82R. 82G. The film thickness of 82B was set to the same film thickness. Therefore, the optical path length 73R is set in the same manner as in the first and second embodiments. 73G. 73B.

因此,電洞注入層兼電洞傳輸層81、電子傳輸層兼電子注入層83、發光層82R.82G.82B之材料及膜厚可設定為與先前相同。因此,於本實施形態中,省略關於該等電洞注入層兼電洞傳輸層81、電子傳輸層兼電子注入層83、發光層82R.82G.82B之具體之材料以及膜厚之說明。 Therefore, the hole injection layer and the hole transport layer 81, the electron transport layer and electron injection layer 83, the light emitting layer 82R. 82G. The material and film thickness of 82B can be set to be the same as before. Therefore, in the present embodiment, the hole injection layer and hole transport layer 81, the electron transport layer and electron injection layer 83, and the light emitting layer 82R are omitted. 82G. Description of the specific material and film thickness of 82B.

<效果> <effect>

如上所述,於本實施形態中,與實施形態1同樣地,藉由將第1電極21設為反射電極層111與透明電極層121之積層構造,而對有機EL元件20導入微空腔構造。 As described above, in the first embodiment, the first electrode 21 is a laminated structure of the reflective electrode layer 111 and the transparent electrode layer 121, and the microcavity structure is introduced into the organic EL element 20 in the same manner as in the first embodiment. .

因此,於本實施形態中,為了對有機EL元件20導入微空腔構造,無需針對每一發光色而變更各發光層82R.82G.82B之膜厚。 Therefore, in the present embodiment, in order to introduce the microcavity structure to the organic EL element 20, it is not necessary to change each of the light-emitting layers 82R for each luminescent color. 82G. The film thickness of 82B.

因此,於本實施形態中,與如實施形態1~7般使用W發光之發光層之情形同樣地,亦可將各發光層82R.82G.82B之膜厚成膜為一樣薄,故可縮短處理節拍。 Therefore, in the present embodiment, as in the case of using the light-emitting layer of the light-emitting layer as in the first to seventh embodiments, each of the light-emitting layers 82R may be used. 82G. The film thickness of 82B is as thin as it is, so the processing beat can be shortened.

又,於本實施形態中,藉由有機EL元件20而獲得對自各發光層82R.82G.82B射出之光之混合添加微空腔效應所得之光。又,藉由利用設置於密封基板50之CF層52調整上述光,可將具有所期望之光譜之光提取至外部。因此,於本 實施形態中,藉由如此般組合使用分塗方式之發光層82R.82G.82B、微空腔效應及CF層52,可提高色純度。 Moreover, in the present embodiment, the self-luminous layer 82R is obtained by the organic EL element 20. 82G. The light from the 82B is added to the light obtained by the microcavity effect. Further, by adjusting the light by the CF layer 52 provided on the sealing substrate 50, light having a desired spectrum can be extracted to the outside. Therefore, in this In an embodiment, the light-emitting layer 82R of the split coating method is used in combination as described above. 82G. 82B, microcavity effect and CF layer 52 can improve color purity.

又,勿庸置疑,於本實施形態中,藉由以與實施形態1、2相同之方式針對每一子像素71R.71G.71B變更第1電極21中之透明電極層121之膜厚,亦獲得與實施形態1、2相同之效果。 Moreover, it is needless to say that in the present embodiment, each sub-pixel 71R is used in the same manner as in the first and second embodiments. 71G. 71B changes the film thickness of the transparent electrode layer 121 in the first electrode 21, and the same effects as those in the first and second embodiments are obtained.

<要點概要> <point summary>

如上所述,本發明之一態樣之顯示裝置之製造方法係如下之方法:於反射電極層之上層成膜含有非晶質之透明電極材料之第1透明電極層並統括地進行蝕刻之後,將含有非晶質之透明電極材料之第1透明電極層轉化為含有多晶之透明電極材料之第1透明電極層,利用其與成膜於其之上方之第2透明電極層之耐蝕刻性之差異而積層透明電極層,藉此,於子像素間變更上述透明電極層之合計膜厚。 As described above, a method of manufacturing a display device according to an aspect of the present invention is a method in which a first transparent electrode layer containing an amorphous transparent electrode material is formed on a layer of a reflective electrode layer and is collectively etched. The first transparent electrode layer containing an amorphous transparent electrode material is converted into a first transparent electrode layer containing a polycrystalline transparent electrode material, and the etching resistance of the second transparent electrode layer formed thereon is formed. The transparent electrode layer is laminated in a difference, whereby the total film thickness of the transparent electrode layer is changed between the sub-pixels.

因此,本發明之一態樣之顯示裝置之製造方法係如下之顯示裝置之製造方法:各子像素中之形成電場之成對電極中,一個電極包含反射電極層及形成於該反射電極層上之至少一層透明電極層,並且於至少1個子像素中之反射電極層上形成有複數層上述透明電極層,於顯示色不同之子像素間上述透明電極層之整體之膜厚不同,該顯示裝置之製造方法包含如下步驟:成膜反射電極層;第1透明電極層成膜步驟,其係於上述反射電極層之上層,成膜含有非晶質之透明電極材料之第1透明電極層;圖案化步驟,其係藉由光微影術對上述含有非晶質之透明電極材料之第1 透明電極層及上述反射電極層統括地進行蝕刻而將其等圖案化;第1透明電極層結晶化步驟,其係使上述圖案化步驟中經圖案化之上述含有非晶質之透明電極材料之第1透明電極層結晶化,而轉化為含有多晶之透明電極材料之第1透明電極層;及第2透明電極層積層步驟,其係於上述含有多晶之透明電極材料之第1透明電極層上,成膜含有耐蝕刻性低於上述含有多晶之透明電極材料之第1透明電極層之透明電極材料的第2透明電極層,並藉由光微影術選擇性地對上述第2透明電極層進行蝕刻而將其圖案化。 Therefore, a method of manufacturing a display device according to an aspect of the present invention is a method of manufacturing a display device in which a pair of electrodes forming an electric field in each sub-pixel includes a reflective electrode layer and is formed on the reflective electrode layer. At least one transparent electrode layer, and a plurality of the transparent electrode layers are formed on the reflective electrode layer of at least one of the sub-pixels, and the overall thickness of the transparent electrode layer is different between sub-pixels having different display colors, and the display device is different The manufacturing method includes the steps of: forming a reflective electrode layer; forming a first transparent electrode layer, the film is formed on the upper layer of the reflective electrode layer, and forming a first transparent electrode layer containing an amorphous transparent electrode material; a step of the first amorphous electrode material containing amorphous material by photolithography The transparent electrode layer and the reflective electrode layer are collectively etched and patterned, and the first transparent electrode layer crystallization step is performed by patterning the amorphous amorphous electrode material in the patterning step. The first transparent electrode layer is crystallized to be converted into a first transparent electrode layer containing a polycrystalline transparent electrode material; and the second transparent electrode layer stacking step is performed on the first transparent electrode of the polycrystalline transparent electrode material a second transparent electrode layer containing a transparent electrode material having a lower etching resistance than the first transparent electrode layer containing the polycrystalline transparent electrode material is formed on the layer, and the second transparent layer is selectively selected by photolithography The transparent electrode layer is etched to pattern it.

根據上述方法,可提供一種於各子像素中之反射電極層上積層有透明電極層,並且可於顯示色不同之子像素間任意地變更反射電極層上之透明電極層之膜厚之實用之顯示裝置之製造方法,並且可削減光微影術之次數。 According to the above method, it is possible to provide a practical display in which a transparent electrode layer is laminated on a reflective electrode layer in each sub-pixel, and the film thickness of the transparent electrode layer on the reflective electrode layer can be arbitrarily changed between sub-pixels having different display colors. The manufacturing method of the device, and the number of times of photolithography can be reduced.

又,於上述顯示裝置之製造方法中,較佳為上述第2透明電極層積層步驟係變更形成抗蝕圖案之子像素而進行複數次,並且包含下述步驟:於藉由光微影術選擇性地對上述第2透明電極層進行蝕刻而將其圖案化時,僅於1個子像素形成抗蝕圖案,將該抗蝕圖案作為遮罩而對上述第2透明電極層進行蝕刻,藉此,僅於上述1個子像素形成上述第2透明電極層之圖案。 Further, in the method of manufacturing the display device, it is preferable that the second transparent electrode layer stacking step is performed by changing a sub-pixel in which a resist pattern is formed, and includes the following steps: selective by photolithography When the second transparent electrode layer is etched and patterned, a resist pattern is formed only for one sub-pixel, and the second transparent electrode layer is etched by using the resist pattern as a mask. A pattern of the second transparent electrode layer is formed on the one sub-pixel.

根據上述方法,如上所述,作為為了變更透明電極層之合計膜厚而所需之光微影術之次數,可利用2次光微影術針對每一子像素任意地變更上述透明電極層之合計膜厚,且可使任意之子像素中之第2透明電極層之膜厚獨立於其 他子像素中之第2透明電極層之膜厚而設定。 According to the above method, as described above, as the number of photolithography required to change the total film thickness of the transparent electrode layer, the transparent electrode layer can be arbitrarily changed for each sub-pixel by secondary photolithography. The film thickness is increased, and the film thickness of the second transparent electrode layer in any of the sub-pixels can be independent of The film thickness of the second transparent electrode layer in the sub-pixel is set.

根據上述方法,如上所述,藉由包含僅於上述1個子像素形成上述第2透明電極層之圖案之步驟,可任意且容易地調整各子像素中之光徑長,而不會如專利文獻3般受光徑長之制約。 According to the above method, as described above, by including the step of forming the pattern of the second transparent electrode layer only by the one sub-pixel, the optical path length in each sub-pixel can be arbitrarily and easily adjusted without being as in the patent document. 3 is generally restricted by the long path of light.

又,上述顯示裝置之製造方法較佳為上述第2透明電極層為含有非晶質之透明電極材料之透明電極層,上述第2透明電極層積層步驟包含如下步驟:第2透明電極層成膜步驟,其係成膜上述含有非晶質之透明電極材料之第2透明電極層;第2透明電極層圖案化步驟,其係藉由光微影術對上述含有非晶質之透明電極材料之第2透明電極層進行蝕刻而將其圖案化;及第2透明電極層結晶化步驟,其係使進行圖案化所得之上述含有非晶質之透明電極材料之第2透明電極層結晶化而轉化為含有多晶之透明電極材料之第2透明電極層;於上述第2透明電極層積層步驟中,藉由重複進行上述第2透明電極層成膜步驟、第2透明電極層圖案化步驟及第2透明電極層結晶化步驟,對任意之子像素積層任意數量之含有多晶之透明電極材料之透明電極層。 Further, in the method of manufacturing the display device, the second transparent electrode layer is a transparent electrode layer containing an amorphous transparent electrode material, and the second transparent electrode layer stacking step includes the step of forming a second transparent electrode layer. a step of forming a second transparent electrode layer containing the amorphous transparent electrode material; and a second transparent electrode layer patterning step of the amorphous transparent electrode material by photolithography The second transparent electrode layer is etched and patterned, and the second transparent electrode layer is crystallized by crystallizing and transforming the second transparent electrode layer containing the amorphous transparent electrode material obtained by patterning. a second transparent electrode layer comprising a polycrystalline transparent electrode material; wherein the second transparent electrode layer forming step, the second transparent electrode layer patterning step, and the second transparent electrode layer forming step are repeated in the second transparent electrode layer stacking step 2 Transparent electrode layer crystallization step, stacking any number of transparent electrode layers containing polycrystalline transparent electrode material for any sub-pixel.

根據上述方法,如上所述,利用含有非晶質之透明電極材料之透明電極層與含有多晶之透明電極材料之透明電極層之蝕刻選擇性之差異而進行透明電極層之堆積。 According to the above method, as described above, the deposition of the transparent electrode layer is performed by the difference in etching selectivity between the transparent electrode layer containing the amorphous transparent electrode material and the transparent electrode layer containing the polycrystalline transparent electrode material.

根據上述方法,可使各透明電極層之膜厚獨立於其他子像素中之透明電極層之膜厚而設定,可任意且容易地調整 各子像素中之光徑長。 According to the above method, the film thickness of each transparent electrode layer can be set independently of the film thickness of the transparent electrode layer in the other sub-pixels, and can be adjusted arbitrarily and easily The optical path in each sub-pixel is long.

又,於上述顯示裝置之製造方法中,較佳為上述第1及第2透明電極層為氧化銦錫。 Further, in the method of manufacturing the display device, it is preferable that the first and second transparent electrode layers are indium tin oxide.

非晶質之氧化銦錫可藉由熱處理而容易地轉化為多晶之氧化銦錫。多晶之氧化銦錫係耐蝕刻性高於非結晶之氧化銦錫,於非結晶之氧化銦錫之蝕刻步驟(第2透明電極層圖案化步驟、第2透明電極層積層步驟)中,其未被蝕刻或蝕刻速度明顯較慢。因此,於非結晶之氧化銦錫之蝕刻步驟中,可選擇性地僅對非結晶之氧化銦錫進行蝕刻。 Amorphous indium tin oxide can be easily converted into polycrystalline indium tin oxide by heat treatment. The polycrystalline indium tin oxide is higher in etching resistance than the amorphous indium tin oxide, and in the etching step of the amorphous indium tin oxide (the second transparent electrode layer patterning step and the second transparent electrode layer layering step), Not etched or the etch rate is significantly slower. Therefore, in the etching step of the amorphous indium tin oxide, only the amorphous indium tin oxide can be selectively etched.

又,於上述第2透明電極層圖案化步驟中,較佳為於上述含有非晶質之透明電極材料之第2透明電極層上形成抗蝕圖案,該抗蝕圖案俯視時與上述反射電極層及上述含有多晶之透明電極材料之第1透明電極層重疊,且形成為俯視時較上述反射電極層及上述含有多晶之透明電極材料之第1透明電極層大,將該抗蝕圖案作為遮罩對上述第2透明電極層進行蝕刻而將其圖案化。 Further, in the second transparent electrode layer patterning step, it is preferable that a resist pattern is formed on the second transparent electrode layer containing the amorphous transparent electrode material, and the resist pattern is formed in a plan view and the reflective electrode layer And the first transparent electrode layer containing the polycrystalline transparent electrode material is superposed, and is formed to be larger than the first transparent electrode layer of the reflective electrode layer and the polycrystalline transparent electrode material in plan view, and the resist pattern is used as the resist pattern The second transparent electrode layer is etched by the mask to pattern it.

根據反射電極材料之種類,若上述反射電極層處於暴露狀態(即露出狀態),則有當例如為了提高抗蝕劑之濕潤性而進行紫外線照射時發生氧化而反射特性降低,或耐溶劑性較低而溶劑滲入之可能性。因此,於如上所述之反射電極層含有如上所述之反射電極材料之情形時,不理想的是反射電極層成為暴露狀態。 According to the type of the reflective electrode material, when the reflective electrode layer is in an exposed state (that is, in an exposed state), for example, when ultraviolet light is irradiated to improve the wettability of the resist, oxidation occurs to lower the reflection property, or the solvent resistance is lowered. Low and the possibility of solvent penetration. Therefore, in the case where the reflective electrode layer as described above contains the reflective electrode material as described above, it is not preferable that the reflective electrode layer is in an exposed state.

然而,根據上述構成,由於可利用含有多晶之透明電極材料之第1透明電極層及第2透明電極層包圍上述反射電極 層,故於製造上述顯示裝置時,可保護上述反射電極層免受有損壞該反射電極層之品質之虞之上述要因的影響。 However, according to the above configuration, the first transparent electrode layer and the second transparent electrode layer which are made of a polycrystalline transparent electrode material can surround the reflective electrode. Since the layer is formed, when the display device is manufactured, the reflective electrode layer can be protected from the above-mentioned factors that are detrimental to the quality of the reflective electrode layer.

又,於上述顯示裝置之製造方法中,較佳為上述第2透明電極層為含有組成與上述第1透明電極層不同之透明電極材料之層。 Further, in the method of manufacturing the display device, it is preferable that the second transparent electrode layer is a layer containing a transparent electrode material having a composition different from that of the first transparent electrode layer.

根據上述方法,可不將含有非結晶之透明電極材料之透明電極層轉化為含有多晶之透明電極材料之透明電極層,而利用含有多晶之透明電極材料之第1透明電極層與上述第2透明電極層之耐蝕刻性之差異所致之蝕刻選擇性之差異,進行透明電極層之堆積。 According to the above method, the transparent electrode layer containing the amorphous transparent electrode material can be converted into the transparent electrode layer containing the polycrystalline transparent electrode material, and the first transparent electrode layer containing the polycrystalline transparent electrode material can be used and the second The deposition of the transparent electrode layer is performed by the difference in etching selectivity due to the difference in etching resistance of the transparent electrode layer.

於此情形時,較佳為上述第1透明電極層為氧化銦錫,上述第2透明電極層為氧化銦鋅。 In this case, it is preferable that the first transparent electrode layer is indium tin oxide and the second transparent electrode layer is indium zinc oxide.

非晶質之氧化銦錫可藉由熱處理而容易地轉化為多晶之氧化銦錫。多晶之氧化銦錫係耐蝕刻性高於氧化銦鋅,當於第2透明電極層之蝕刻步驟(第2透明電極層積層步驟)中對氧化銦鋅進行蝕刻時,其未被蝕刻或蝕刻速度明顯較慢。因此,於第2透明電極層之蝕刻步驟中,僅含有氧化銦鋅之第2透明電極層被選擇性地蝕刻。 Amorphous indium tin oxide can be easily converted into polycrystalline indium tin oxide by heat treatment. The polycrystalline indium tin oxide is higher in etching resistance than indium zinc oxide, and when indium zinc oxide is etched in the etching step (second transparent electrode layer lamination step) of the second transparent electrode layer, it is not etched or etched. The speed is significantly slower. Therefore, in the etching step of the second transparent electrode layer, the second transparent electrode layer containing only indium zinc oxide is selectively etched.

又,於上述第2透明電極層積層步驟中,較佳為將抗蝕圖案用作遮罩而對上述第2透明電極層進行蝕刻,該抗蝕圖案俯視時與上述反射電極層及上述含有多晶之透明電極材料之第1透明電極層重疊,且形成為俯視時較上述反射電極層及上述含有多晶之透明電極材料之第1透明電極層大。 Further, in the second transparent electrode layer stacking step, it is preferable that the second transparent electrode layer is etched by using a resist pattern as a mask, and the resist pattern is formed in a plan view and the reflective electrode layer and the plurality of layers. The first transparent electrode layer of the transparent electrode material of the crystal is superposed, and is formed to be larger than the first transparent electrode layer of the reflective electrode layer and the polycrystalline transparent electrode material in plan view.

於此情形時,可利用含有多晶之透明電極材料之第1透明電極層及第2透明電極層包圍上述反射電極層。 In this case, the reflective electrode layer may be surrounded by the first transparent electrode layer and the second transparent electrode layer containing a polycrystalline transparent electrode material.

又,於上述顯示裝置之製造方法中,較佳為上述反射電極層含有選自由銀、銀合金及鋁合金所組成之群之任一種。 Further, in the method of manufacturing the display device, it is preferable that the reflective electrode layer contains any one selected from the group consisting of silver, a silver alloy, and an aluminum alloy.

該等材料係於與非晶質之透明電極層之間不發生電蝕反應。因此,適於上述反射電極層中之反射電極材料。 These materials are such that no electrolytic corrosion reaction occurs between the amorphous transparent electrode layers. Therefore, it is suitable for the reflective electrode material in the above reflective electrode layer.

又,於上述顯示裝置之製造方法中,較佳為上述成對電極為陽極及陰極,上述一個電極為陽極,並且以利用上述陽極與陰極夾持有機電致發光層之方式形成上述陽極、陰極及有機電致發光層。 Further, in the method of manufacturing the display device, preferably, the pair of electrodes are an anode and a cathode, the one electrode is an anode, and the anode and the cathode are formed by sandwiching an organic electroluminescent layer with the anode and the cathode. And an organic electroluminescent layer.

根據上述方法,可針對發光色不同之每一子像素容易地變更利用上述陽極與陰極夾持有機電致發光層而成之有機電致發光元件之光徑長。 According to the above method, the optical path length of the organic electroluminescence element in which the organic electroluminescent layer is sandwiched between the anode and the cathode can be easily changed for each sub-pixel having a different luminescent color.

因此,根據上述方法,可獲得具有微空腔構造之有機電致發光元件。因此,藉由微空腔效應,可提高使用上述有機電致發光元件之顯示裝置中之色純度、發光色度、發光效率等。 Therefore, according to the above method, an organic electroluminescence element having a microcavity structure can be obtained. Therefore, color purity, luminescence chromaticity, luminous efficiency, and the like in the display device using the above organic electroluminescence device can be improved by the microcavity effect.

又,如上所述,本發明之一態樣之顯示裝置係如下之顯示裝置:各子像素中之形成電場之成對電極中,一個電極包含反射電極層及形成於該反射電極層上之至少一層透明電極層,並且於至少1個子像素中之反射電極層上形成有複數層上述透明電極層,於顯示色不同之子像素間上述透明電極層之整體之膜厚不同,且上述複數之透明電極層具 有互不相同之組成,下層之透明電極層之耐蝕刻性高於上層之透明電極層之耐蝕刻性。 Further, as described above, a display device according to an aspect of the present invention is a display device in which a pair of electrodes forming an electric field in each sub-pixel includes one of a reflective electrode layer and at least a reflective electrode layer formed on the reflective electrode layer. a transparent electrode layer, wherein a plurality of the transparent electrode layers are formed on the reflective electrode layer of the at least one sub-pixel, and the film thickness of the transparent electrode layer is different between the sub-pixels having different display colors, and the plurality of transparent electrodes Layer There are mutually different compositions, and the etching resistance of the lower transparent electrode layer is higher than that of the upper transparent electrode layer.

根據上述構成,可提供一種針對顯示色不同之每一子像素而透明電極層之膜厚不同,並且可利用實用之方法製造之顯示裝置。 According to the above configuration, it is possible to provide a display device which is different in film thickness of each of the sub-pixels having different display colors and which can be manufactured by a practical method.

又,上述顯示裝置較佳為上述下層之透明電極層含有多晶之氧化銦錫,上述上層之透明電極層含有氧化銦鋅。 Further, in the above display device, it is preferable that the lower transparent electrode layer contains polycrystalline indium tin oxide, and the upper transparent electrode layer contains indium zinc oxide.

非晶質之氧化銦錫可藉由熱處理而容易地轉化為多晶之氧化銦錫。多晶之氧化銦錫係耐蝕刻性高於氧化銦鋅,當對氧化銦鋅進行蝕刻時,其未被蝕刻或蝕刻速度明顯較慢。因此,可選擇性地僅對含有氧化銦鋅之透明電極層進行蝕刻。 Amorphous indium tin oxide can be easily converted into polycrystalline indium tin oxide by heat treatment. The polycrystalline indium tin oxide is more resistant to etching than indium zinc oxide, and when indium zinc oxide is etched, it is not etched or the etching rate is significantly slower. Therefore, it is possible to selectively etch only the transparent electrode layer containing indium zinc oxide.

因此,根據上述構成,可提供一種針對顯示色不同之每一子像素而透明電極層之膜厚不同,並且可利用實用之方法製造之顯示裝置。 Therefore, according to the above configuration, it is possible to provide a display device which is different in film thickness of each of the sub-pixels having different display colors and which can be manufactured by a practical method.

又,於上述顯示裝置中,較佳為上述反射電極層含有選自由銀、銀合金及鋁合金所組成之群之任一種。 Further, in the above display device, it is preferable that the reflective electrode layer contains any one selected from the group consisting of silver, a silver alloy, and an aluminum alloy.

於如上述般對下層之透明電極層與上層之透明電極層使用具有互不相同之組成且耐蝕刻性不同之透明電極材料之情形時,根據上述透明電極材料與反射電極材料之組合,有發生電蝕反應之虞。 When a transparent electrode material having a composition different from each other and having different etching resistance is used for the lower transparent electrode layer and the upper transparent electrode layer as described above, the combination of the transparent electrode material and the reflective electrode material may occur. The enthalpy of electro-erosion reaction.

然而,於上述反射電極層含有上述反射電極材料之情形時,不存在如上所述之擔憂。因此,上述反射電極材料適於上述反射電極層中之反射電極材料。 However, in the case where the above-mentioned reflective electrode layer contains the above-mentioned reflective electrode material, there is no fear as described above. Therefore, the above-mentioned reflective electrode material is suitable for the reflective electrode material in the above-mentioned reflective electrode layer.

又,於上述顯示裝置中,較佳為上述上層之透明電極層覆蓋上述下層之透明電極層之表面及上述反射電極層之側面。 Further, in the above display device, it is preferable that the upper transparent electrode layer covers a surface of the lower transparent electrode layer and a side surface of the reflective electrode layer.

根據反射電極材料之種類,若上述反射電極層處於暴露狀態(即露出狀態),則有當例如為了提高抗蝕劑之濕潤性而進行紫外線照射時發生氧化而反射特性降低,或耐溶劑性較低而溶劑滲入之可能性。因此,於如上所述之反射電極層含有如上所述之反射電極材料之情形時,不理想的是反射電極層成為暴露狀態。 According to the type of the reflective electrode material, when the reflective electrode layer is in an exposed state (that is, in an exposed state), for example, when ultraviolet light is irradiated to improve the wettability of the resist, oxidation occurs to lower the reflection property, or the solvent resistance is lowered. Low and the possibility of solvent penetration. Therefore, in the case where the reflective electrode layer as described above contains the reflective electrode material as described above, it is not preferable that the reflective electrode layer is in an exposed state.

然而,根據上述構成,於製造上述顯示裝置時,可保護上述反射電極層免受有損壞該反射電極層之品質之虞之上述要因的影響。 However, according to the above configuration, when the display device is manufactured, the reflective electrode layer can be protected from the above-mentioned factors that are detrimental to the quality of the reflective electrode layer.

因此,根據上述構成,可提供一種包含反射特性優異之反射電極層之顯示裝置。 Therefore, according to the above configuration, it is possible to provide a display device including a reflective electrode layer having excellent reflection characteristics.

本發明並不限定於上述各實施形態,可於技術方案所示之範圍內進行多種變更,對於適當組合不同之實施形態中分別揭示之技術手段而獲得之實施形態,亦包含於本發明之技術範圍中。 The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the technical means. The embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are also included in the technology of the present invention. In the scope.

[產業上之可利用性] [Industrial availability]

本發明可較佳地用於使用可作為如有機EL元件或無機EL元件般之微小共振器而構成之發光元件之顯示裝置及其製造方法。 The present invention can be preferably applied to a display device using a light-emitting element which can be used as a minute resonator such as an organic EL element or an inorganic EL element, and a method of manufacturing the same.

1‧‧‧有機EL顯示面板 1‧‧‧Organic EL display panel

2‧‧‧電氣配線端子 2‧‧‧Electrical wiring terminals

10‧‧‧支撐基板 10‧‧‧Support substrate

11‧‧‧絕緣基板 11‧‧‧Insert substrate

12‧‧‧TFT 12‧‧‧TFT

13‧‧‧層間絕緣膜 13‧‧‧Interlayer insulating film

13a‧‧‧接觸孔 13a‧‧‧Contact hole

14‧‧‧信號線 14‧‧‧ signal line

15‧‧‧邊罩 15‧‧‧ side cover

15R‧‧‧開口部 15R‧‧‧ openings

15G‧‧‧開口部 15G‧‧‧ openings

15B‧‧‧開口部 15B‧‧‧ openings

20‧‧‧有機EL元件 20‧‧‧Organic EL components

21‧‧‧第1電極 21‧‧‧1st electrode

22‧‧‧電洞注入層 22‧‧‧ hole injection layer

23‧‧‧電洞傳輸層 23‧‧‧ hole transport layer

24‧‧‧第1發光層 24‧‧‧1st luminescent layer

25‧‧‧電子傳輸層 25‧‧‧Electronic transport layer

26‧‧‧載子產生層 26‧‧‧Carrier generation layer

27‧‧‧電洞傳輸層 27‧‧‧ hole transport layer

28‧‧‧第2發光層 28‧‧‧2nd luminescent layer

29‧‧‧電子傳輸層 29‧‧‧Electronic transport layer

30‧‧‧電子注入層 30‧‧‧Electronic injection layer

31‧‧‧第2電極 31‧‧‧2nd electrode

41‧‧‧密封樹脂層 41‧‧‧ sealing resin layer

42‧‧‧填充樹脂層 42‧‧‧filled resin layer

43‧‧‧有機EL層 43‧‧‧Organic EL layer

50‧‧‧密封基板 50‧‧‧Seal substrate

51‧‧‧絕緣基板 51‧‧‧Insert substrate

52‧‧‧CF層 52‧‧‧CF layer

53‧‧‧BM 53‧‧‧BM

60‧‧‧連接部 60‧‧‧Connecting Department

70‧‧‧像素 70‧‧‧ pixels

71‧‧‧子像素 71‧‧‧Subpixel

71B‧‧‧子像素 71B‧‧‧Subpixel

71G‧‧‧子像素 71G‧‧‧Subpixel

71R‧‧‧子像素 71R‧‧‧Subpixel

72‧‧‧發光區域 72‧‧‧Lighting area

73B‧‧‧光徑長 73B‧‧‧ long path length

73G‧‧‧光徑長 73G‧‧‧ long path length

73R‧‧‧光徑長 73R‧‧‧ long path length

81‧‧‧電洞注入層兼電洞傳輸層 81‧‧‧ hole injection layer and hole transmission layer

82B‧‧‧發光層 82B‧‧‧Lighting layer

82G‧‧‧發光層 82G‧‧‧Lighting layer

82R‧‧‧發光層 82R‧‧‧Lighting layer

83‧‧‧電子傳輸層兼電子注入層 83‧‧‧Electron transport layer and electron injection layer

100‧‧‧有機EL顯示裝置 100‧‧‧Organic EL display device

101‧‧‧像素部 101‧‧‧Pixel Department

102‧‧‧電路部 102‧‧‧Development Department

103‧‧‧連接端子 103‧‧‧Connecting terminal

110‧‧‧a-ITO層 110‧‧‧a-ITO layer

111‧‧‧反射電極層 111‧‧‧Reflective electrode layer

112‧‧‧a-ITO層 112‧‧‧a-ITO layer

113‧‧‧p-ITO層 113‧‧‧p-ITO layer

114‧‧‧p-ITO層 114‧‧‧p-ITO layer

115‧‧‧a-ITO層 115‧‧‧a-ITO layer

116‧‧‧p-ITO層 116‧‧‧p-ITO layer

117‧‧‧a-ITO層 117‧‧‧a-ITO layer

118‧‧‧p-ITO層 118‧‧‧p-ITO layer

121‧‧‧透明電極層 121‧‧‧Transparent electrode layer

131‧‧‧IZO層 131‧‧‧IZO layer

132‧‧‧IZO層 132‧‧‧IZO layer

201B‧‧‧抗蝕圖案 201B‧‧‧resist pattern

201G‧‧‧抗蝕圖案 201G‧‧‧resist pattern

201R‧‧‧抗蝕圖案 201R‧‧‧resist pattern

202G‧‧‧抗蝕圖案 202G‧‧‧resist pattern

202R‧‧‧抗蝕圖案 202R‧‧‧resist pattern

211B‧‧‧抗蝕圖案 211B‧‧‧resist pattern

211G‧‧‧抗蝕圖案 211G‧‧‧resist pattern

211R‧‧‧抗蝕圖案 211R‧‧‧resist pattern

L‧‧‧密封區域 L‧‧‧ Sealed area

R1‧‧‧顯示區域 R1‧‧‧ display area

R2‧‧‧第2電極連接區域 R2‧‧‧2nd electrode connection area

R3‧‧‧端子部區域 R3‧‧‧Terminal area

圖1(a)~(i)係按步驟表示實施形態1之頂部發光型之有機 EL顯示裝置中之第1電極之製作方法之一例的剖面圖。 1(a) to (i) show the organic form of the top emission type of the first embodiment in steps. A cross-sectional view showing an example of a method of fabricating the first electrode in the EL display device.

圖2係表示實施形態1之有機EL顯示裝置之主要部分之概略構成的分解剖面圖。 FIG. 2 is an exploded cross-sectional view showing a schematic configuration of a main part of the organic EL display device of the first embodiment.

圖3係表示實施形態1之有機EL顯示裝置中之支撐基板之概略構成的俯視圖。 3 is a plan view showing a schematic configuration of a support substrate in the organic EL display device of the first embodiment.

圖4係表示圖3所示之支撐基板中之顯示區域之主要部分之構成的俯視圖。 4 is a plan view showing a configuration of a main portion of a display region in the support substrate shown in FIG. 3.

圖5係表示沿著圖4所示之A-A線切斷實施形態1之有機EL顯示面板時之有機EL顯示面板之概略構成的剖面圖。 Fig. 5 is a cross-sectional view showing a schematic configuration of an organic EL display panel in the case where the organic EL display panel of the first embodiment is cut along the line A-A shown in Fig. 4 .

圖6係對實施形態1之有機EL顯示裝置之圖像顯示方法進行說明之模式圖。 Fig. 6 is a schematic view for explaining an image display method of the organic EL display device of the first embodiment.

圖7係按步驟表示實施形態1之有機EL顯示裝置之製造步驟之一例之流程圖。 Fig. 7 is a flow chart showing an example of a manufacturing procedure of the organic EL display device of the first embodiment in steps.

圖8係按步驟表示實施形態1之有機EL層之製作步驟之一例之流程圖。 Fig. 8 is a flow chart showing an example of the steps of producing the organic EL layer of the first embodiment in steps.

圖9(a).(b)係模式性地表示於圖1(i)所示之第1電極上製作有邊罩時之第1電極之概略構成的圖,(a)為剖面圖,(b)為俯視圖。 Figure 9 (a). (b) is a view schematically showing a schematic configuration of a first electrode when a side cover is formed on the first electrode shown in Fig. 1(i), (a) is a cross-sectional view, and (b) is a plan view.

圖10(a)~(h)係按步驟表示自實施形態2之頂部發光型之有機EL顯示裝置00中之第1電極之製作直至邊罩之製作為止之步驟之一例的剖面圖。 (a) to (h) are cross-sectional views showing an example of the steps from the production of the first electrode in the top emission type organic EL display device 00 of the second embodiment to the production of the side mask.

圖11係表示實施形態3之有機EL顯示面板之概略構成之剖面圖。 Figure 11 is a cross-sectional view showing a schematic configuration of an organic EL display panel of a third embodiment.

圖12係按步驟表示圖11所示之有機EL層之製作步驟之一 例之流程圖。 Figure 12 is a diagram showing one of the steps of producing the organic EL layer shown in Figure 11 in steps. Flow chart of the example.

圖13(a)~(f)係按步驟表示針對每一子像素而變更陽極之反射電極層上之透明電極層之合計膜厚之方法之一例的剖面圖。 13(a) to (f) are cross-sectional views showing an example of a method of changing the total film thickness of the transparent electrode layer on the reflective electrode layer of the anode for each sub-pixel in steps.

10‧‧‧支撐基板 10‧‧‧Support substrate

71B‧‧‧子像素 71B‧‧‧Subpixel

71G‧‧‧子像素 71G‧‧‧Subpixel

71R‧‧‧子像素 71R‧‧‧Subpixel

110‧‧‧a-ITO層 110‧‧‧a-ITO layer

111‧‧‧反射電極層 111‧‧‧Reflective electrode layer

112‧‧‧a-ITO層 112‧‧‧a-ITO layer

113‧‧‧p-ITO層 113‧‧‧p-ITO layer

114‧‧‧p-ITO層 114‧‧‧p-ITO layer

115‧‧‧a-ITO層 115‧‧‧a-ITO layer

116‧‧‧p-ITO層 116‧‧‧p-ITO layer

117‧‧‧a-ITO層 117‧‧‧a-ITO layer

118‧‧‧p-ITO層 118‧‧‧p-ITO layer

121‧‧‧透明電極層 121‧‧‧Transparent electrode layer

201B‧‧‧抗蝕圖案 201B‧‧‧resist pattern

201G‧‧‧抗蝕圖案 201G‧‧‧resist pattern

201R‧‧‧抗蝕圖案 201R‧‧‧resist pattern

202G‧‧‧抗蝕圖案 202G‧‧‧resist pattern

202R‧‧‧抗蝕圖案 202R‧‧‧resist pattern

Claims (14)

一種顯示裝置之製造方法,其特徵在於:該顯示裝置中各子像素中之形成電場之成對電極中,一個電極包含反射電極層及形成於該反射電極層上之至少一層透明電極層,並且於至少1個子像素中之反射電極層上形成有複數層上述透明電極層,於顯示色不同之子像素間上述透明電極層之整體之膜厚不同,該顯示裝置之製造方法包含如下步驟:成膜反射電極層;第1透明電極層成膜步驟,其係於上述反射電極層之上層成膜含有非晶質之透明電極材料之第1透明電極層;圖案化步驟,其係藉由光微影術對上述含有非晶質之透明電極材料之第1透明電極層及上述反射電極層統括地進行蝕刻而將其等圖案化;第1透明電極層結晶化步驟,其係使上述圖案化步驟中經圖案化之上述含有非晶質之透明電極材料之第1透明電極層結晶化,而轉化為含有多晶之透明電極材料之第1透明電極層;及第2透明電極層積層步驟,其係於上述含有多晶之透明電極材料之第1透明電極層上成膜含有耐蝕刻性低於上述含有多晶之透明電極材料之第1透明電極層之透明電極材料的第2透明電極層,並藉由光微影術選擇性地對上述第2透明電極層進行蝕刻而將其圖案化。 A manufacturing method of a display device, wherein one of the pair of electrodes forming an electric field in each sub-pixel of the display device comprises a reflective electrode layer and at least one transparent electrode layer formed on the reflective electrode layer, and A plurality of the transparent electrode layers are formed on the reflective electrode layer of the at least one sub-pixel, and the film thickness of the transparent electrode layer is different between the sub-pixels having different display colors, and the manufacturing method of the display device includes the following steps: film formation a reflective electrode layer; a first transparent electrode layer forming step of forming a first transparent electrode layer containing an amorphous transparent electrode material on the upper surface of the reflective electrode layer; and a patterning step by photolithography The first transparent electrode layer and the reflective electrode layer containing the amorphous transparent electrode material are collectively etched and patterned, and the first transparent electrode layer crystallization step is performed in the patterning step. The patterned first transparent electrode layer containing the amorphous transparent electrode material is crystallized and converted into a polycrystalline transparent electrode material. a transparent electrode layer; and a second transparent electrode layer stacking step, wherein the first transparent electrode layer containing the polycrystalline transparent electrode material is formed to have a film having a lower etching resistance than the polycrystalline transparent electrode material The second transparent electrode layer of the transparent electrode material of the transparent electrode layer is selectively patterned by photolithography to etch the second transparent electrode layer. 如請求項1之顯示裝置之製造方法,其中上述第2透明電極層積層步驟係變更形成抗蝕圖案之子像素而進行複數次,並且包含如下步驟:於藉由光微影術選擇性地對上述第2透明電極層進行蝕刻而將其圖案化時,僅於1個子像素形成抗蝕圖案,並將該抗蝕圖案作為遮罩而對上述第2透明電極層進行蝕刻,藉此僅於上述1個子像素形成上述第2透明電極層之圖案。 The method of manufacturing the display device according to claim 1, wherein the step of depositing the second transparent electrode layer is performed by changing a sub-pixel forming a resist pattern, and comprising the steps of: selectively performing the above by photolithography When the second transparent electrode layer is etched and patterned, a resist pattern is formed only on one sub-pixel, and the second transparent electrode layer is etched by using the resist pattern as a mask, thereby only the above 1 The sub-pixels form a pattern of the second transparent electrode layer. 如請求項1或2之顯示裝置之製造方法,其中上述第2透明電極層係含有非晶質之透明電極材料之透明電極層,上述第2透明電極層積層步驟包含如下步驟:第2透明電極層成膜步驟,其係成膜上述含有非晶質之透明電極材料之第2透明電極層;第2透明電極層圖案化步驟,其係藉由光微影術對上述含有非晶質之透明電極材料之第2透明電極層進行蝕刻而將其圖案化;及第2透明電極層結晶化步驟,其係使經圖案化之上述含有非晶質之透明電極材料之第2透明電極層結晶化而轉化為含有多晶之透明電極材料之第2透明電極層;於上述第2透明電極層積層步驟中,藉由重複進行上述第2透明電極層成膜步驟、第2透明電極層圖案化步驟及第2透明電極層結晶化步驟,對任意之子像素積層任意數量之含有多晶之透明電極材料之透明電極層。 The method of manufacturing a display device according to claim 1 or 2, wherein the second transparent electrode layer comprises a transparent electrode layer of an amorphous transparent electrode material, and the second transparent electrode layer stacking step comprises the following steps: a second transparent electrode a layer forming step of forming a second transparent electrode layer containing the amorphous transparent electrode material; and a second transparent electrode layer patterning step of transparently containing the amorphous layer by photolithography The second transparent electrode layer of the electrode material is etched and patterned, and the second transparent electrode layer crystallization step is to crystallize the patterned second transparent electrode layer containing the amorphous transparent electrode material. And converting into a second transparent electrode layer containing a polycrystalline transparent electrode material; and repeating the second transparent electrode layer forming step and the second transparent electrode layer patterning step in the second transparent electrode layer stacking step And a second transparent electrode layer crystallization step of laminating an arbitrary number of transparent electrode layers containing a polycrystalline transparent electrode material to any sub-pixel. 如請求項3之顯示裝置之製造方法,其中上述第1及第2透明電極層為氧化銦錫。 The method of manufacturing a display device according to claim 3, wherein the first and second transparent electrode layers are indium tin oxide. 如請求項3或4之顯示裝置之製造方法,其中於上述第2透明電極層圖案化步驟中,於上述含有非晶質之透明電極材料之第2透明電極層上形成抗蝕圖案,該抗蝕圖案俯視時與上述反射電極層及上述含有多晶之透明電極材料之第1透明電極層重疊且形成為俯視時較上述反射電極層及上述含有多晶之透明電極材料之第1透明電極層大,將該抗蝕圖案作為遮罩對上述第2透明電極層進行蝕刻而將其圖案化。 The method of manufacturing a display device according to claim 3 or 4, wherein in the second transparent electrode layer patterning step, a resist pattern is formed on the second transparent electrode layer containing the amorphous transparent electrode material. The first transparent electrode layer of the reflective electrode layer and the polycrystalline transparent electrode material is formed in a plan view when the etching pattern is superposed on the reflective electrode layer and the first transparent electrode layer containing the polycrystalline transparent electrode material. When the resist pattern is used as a mask, the second transparent electrode layer is etched and patterned. 如請求項1或2之顯示裝置之製造方法,其中上述第2透明電極層係含有組成與上述第1透明電極層不同之透明電極材料之層。 The method of manufacturing a display device according to claim 1 or 2, wherein the second transparent electrode layer contains a layer of a transparent electrode material having a composition different from that of the first transparent electrode layer. 如請求項6之顯示裝置之製造方法,其中上述第1透明電極層為氧化銦錫,上述第2透明電極層為氧化銦鋅。 The method of manufacturing a display device according to claim 6, wherein the first transparent electrode layer is indium tin oxide, and the second transparent electrode layer is indium zinc oxide. 如請求項6或7之顯示裝置之製造方法,其中於上述第2透明電極層積層步驟中,將抗蝕圖案用作遮罩而對上述第2透明電極層進行蝕刻,上述抗蝕圖案係俯視時與上述反射電極層及上述含有多晶之透明電極材料之第1透明電極層重疊且形成為俯視時較上述反射電極層及上述含有多晶之透明電極材料之第1透明電極層大。 The method of manufacturing a display device according to claim 6 or 7, wherein in the step of depositing the second transparent electrode layer, the second transparent electrode layer is etched by using the resist pattern as a mask, and the resist pattern is viewed from above When it overlaps with the reflective electrode layer and the first transparent electrode layer containing the polycrystalline transparent electrode material, it is formed larger than the first transparent electrode layer of the reflective electrode layer and the polycrystalline transparent electrode material in plan view. 如請求項1至8中任一項之顯示裝置之製造方法,其中上述反射電極層包含選自由銀、銀合金及鋁合金所組成之群中之任一種。 The method of manufacturing a display device according to any one of claims 1 to 8, wherein the reflective electrode layer comprises any one selected from the group consisting of silver, a silver alloy, and an aluminum alloy. 如請求項1至9中任一項之顯示裝置之製造方法,其中上述成對電極為陽極及陰極,且上述一個電極為陽極, 並且以利用上述陽極與陰極夾持有機電致發光層之方式形成上述陽極、陰極及有機電致發光層。 The method of manufacturing the display device according to any one of claims 1 to 9, wherein the pair of electrodes are an anode and a cathode, and the one electrode is an anode. Further, the anode, the cathode, and the organic electroluminescent layer are formed by sandwiching the organic electroluminescent layer with the anode and the cathode. 一種顯示裝置,其特徵在於:各子像素中之形成電場之成對電極中,一個電極包含反射電極層及形成於該反射電極層上之至少一層透明電極層,並且於至少1個子像素中之反射電極層上形成有複數層上述透明電極層,於顯示色不同之子像素間上述透明電極層之整體之膜厚不同,上述複數之透明電極層具有互不相同之組成,下層之透明電極層之耐蝕刻性高於上層之透明電極層之耐蝕刻性。 A display device, characterized in that: among the pair of electrodes forming an electric field in each sub-pixel, one of the electrodes includes a reflective electrode layer and at least one transparent electrode layer formed on the reflective electrode layer, and is in at least one sub-pixel a plurality of layers of the transparent electrode layer are formed on the reflective electrode layer, and the thickness of the entire transparent electrode layer is different between sub-pixels having different display colors, and the plurality of transparent electrode layers have different compositions, and the lower transparent electrode layer The etching resistance is higher than the etching resistance of the upper transparent electrode layer. 如請求項11之顯示裝置,其中上述下層之透明電極層含有多晶之氧化銦錫,上述上層之透明電極層含有氧化銦鋅。 The display device of claim 11, wherein the lower transparent electrode layer contains polycrystalline indium tin oxide, and the upper transparent electrode layer contains indium zinc oxide. 如請求項11或12之顯示裝置,其中上述反射電極層包含選自由銀、銀合金及鋁合金所組成之群中之任一種。 The display device of claim 11 or 12, wherein the reflective electrode layer comprises any one selected from the group consisting of silver, a silver alloy, and an aluminum alloy. 如請求項11至13中任一項之顯示裝置,其中上述上層之透明電極層覆蓋上述下層之透明電極層之表面及上述反射電極層之側面。 The display device according to any one of claims 11 to 13, wherein the upper transparent electrode layer covers a surface of the lower transparent electrode layer and a side surface of the reflective electrode layer.
TW101135184A 2011-09-30 2012-09-25 Method for manufacturing display device, and display device TW201320429A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011218362 2011-09-30

Publications (1)

Publication Number Publication Date
TW201320429A true TW201320429A (en) 2013-05-16

Family

ID=47995490

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101135184A TW201320429A (en) 2011-09-30 2012-09-25 Method for manufacturing display device, and display device

Country Status (2)

Country Link
TW (1) TW201320429A (en)
WO (1) WO2013047457A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412793B2 (en) 2014-03-07 2016-08-09 Semiconductor Energy Laboratory Co., Ltd. Light-emitting element, light-emitting device, electronic device, and lighting device

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015187982A (en) * 2014-03-13 2015-10-29 株式会社半導体エネルギー研究所 Light-emitting element, light-emitting device, electronic apparatus, and lighting system
US10529780B2 (en) * 2017-02-28 2020-01-07 Semiconductor Energy Laboratory Co., Ltd. Display device, display module, and electronic device
KR20210069289A (en) * 2019-12-03 2021-06-11 엘지디스플레이 주식회사 Display device
FR3112243A1 (en) * 2020-07-02 2022-01-07 Microoled THIN-LAYER MATRIX OPTOELECTRONIC DEVICE
CN112599703B (en) * 2020-12-14 2022-08-23 深圳市华星光电半导体显示技术有限公司 Display substrate, preparation method thereof and display panel
WO2025253474A1 (en) * 2024-06-04 2025-12-11 シャープディスプレイテクノロジー株式会社 Method for manufacturing display device, and display device
WO2025253473A1 (en) * 2024-06-04 2025-12-11 シャープディスプレイテクノロジー株式会社 Method for producing display device, and display device
WO2026022893A1 (en) * 2024-07-22 2026-01-29 シャープディスプレイテクノロジー株式会社 Display device and method for manufacturing same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4453316B2 (en) * 2003-09-19 2010-04-21 ソニー株式会社 ORGANIC LIGHT EMITTING DEVICE, ITS MANUFACTURING METHOD, AND DISPLAY DEVICE
JP4475942B2 (en) * 2003-12-26 2010-06-09 三洋電機株式会社 Display device and manufacturing method thereof
JP4439260B2 (en) * 2003-12-26 2010-03-24 三洋電機株式会社 Manufacturing method of display device
WO2005086539A1 (en) * 2004-03-05 2005-09-15 Idemitsu Kosan Co., Ltd. Organic electroluminescence display device
JP4548253B2 (en) * 2005-07-15 2010-09-22 セイコーエプソン株式会社 ORGANIC ELECTROLUMINESCENT DEVICE AND METHOD FOR MANUFACTURING ORGANIC ELECTROLUMINESCENT DEVICE
KR100932940B1 (en) * 2008-05-28 2009-12-21 삼성모바일디스플레이주식회사 Organic light emitting display device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412793B2 (en) 2014-03-07 2016-08-09 Semiconductor Energy Laboratory Co., Ltd. Light-emitting element, light-emitting device, electronic device, and lighting device
US10033016B2 (en) 2014-03-07 2018-07-24 Semiconductor Energy Laboratory Co., Ltd. Light-emitting element, light-emitting device, electronic device, and lighting device
US10418594B2 (en) 2014-03-07 2019-09-17 Semiconductor Energy Laboratory Co., Ltd. Light-emitting element, light-emitting device, electronic device, and lighting device

Also Published As

Publication number Publication date
WO2013047457A1 (en) 2013-04-04

Similar Documents

Publication Publication Date Title
JP5722453B2 (en) Manufacturing method of display device
CN104009186B (en) Organic light-emitting display device and manufacture method thereof
JP6479738B2 (en) Non-common capping layer on organic devices
KR100961343B1 (en) Organic EL display and manufacturing method thereof
TW201320429A (en) Method for manufacturing display device, and display device
KR101349143B1 (en) Method of manufacturing organic light emitting display device
TWI500144B (en) Organic light emitting display device and method of manufacturing same
US8878206B2 (en) Organic light emitting display apparatus including an auxiliary layer and method for manufacturing the same
US10381600B2 (en) Organic electroluminescence device, illumination device, and display device
KR101976829B1 (en) Large Area Organic Light Emitting Diode Display And Method For Manufacturing The Same
CN102184937B (en) Organic electroluminescence device and preparation method thereof
JP4775863B2 (en) Organic EL display device and manufacturing method thereof
US20180212198A1 (en) Organic electroluminescence device and illumination device
JP5094477B2 (en) Organic light-emitting display device and method for manufacturing the same
US10826021B2 (en) Organic electroluminescence device including a plurality of unit regions each including a light emitting area and a transmissive area
US10516131B2 (en) Organic electroluminescence device, method for producing organic electroluminescence device, illumination device, and display device
WO2020233284A1 (en) Display panel and preparation method therefor, and display device
CN103299712B (en) By substrate for film deposition and organic EL display
JP2008108530A (en) Organic EL display device
KR102315824B1 (en) Organic light emitting display device and method of fabricating the same
WO2013047621A1 (en) Display device and method for manufacturing display device
JP2003257665A (en) Organic electroluminescence display device and its manufacturing method
WO2013047622A1 (en) Display device and display device manufacturing method
US9129915B2 (en) Organic EL display device and method of manufacturing the same
KR20140087993A (en) Organic light emitting display and manufactucring method of the same