TW201327787A - NAND flash with non-trapping switch transistors - Google Patents

Abstract

A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.

Description

Anti-flash memory with non-capturing switching transistor

The present invention relates to flash memory technology.

Flash memory is a non-volatile integrated circuit memory technology. Traditional flash memory systems use floating gate memory cells. However, as the density of the memory device increases, the floating gate memory cells get closer to each other, and the interface between the extremely stored charges of the adjacent two floating gates becomes a problem and limits the floating gate memory cells. The flash memory continues to increase in density. Another type of memory cell used in flash memory can be referred to as a charge trapping memory cell, replacing the floating gate with a dielectric charge trapping structure. Charge trapping memory cells use a dielectric material to store charge and therefore do not have a memory intercellular interface like floating gate technology.

A typical charge trapping flash memory cell is composed of a field effect transistor structure (FET) having a source and a drain separated by a channel, and a gate separated from the channel by a charge storage structure, wherein the charge storage structure A dielectric layer, a charge storage layer and a blocking dielectric layer are included. The early traditional charge trapping memory was called SONOS device because of its design. According to the SONOS design, the source, drain and channel are formed on a substrate (S), and the dielectric layer is formed of yttrium oxide (O). The charge storage layer is formed of tantalum nitride (N), the barrier dielectric layer is formed of ruthenium oxide (O), and the gate includes polysilicon (S).

While other types of architectures, such as the AND architecture, are also used in flash memory devices, they are usually reversed (NAND) or reverse (NOR) architectures. The NAND architecture is prevalent due to the high density and high speed of data storage applications, while the NOR architecture is more suitable for applications that focus on random access, such as coded storage. In a NAND architecture, memory cells with switching transistors are arranged in a NAND string, and NAND strings including series memory cells are used to connect the strings to, for example, bit lines and common source lines. A switching transistor is generally used as a general term for a series selection transistor and a ground selection transistor, and may be composed of a FET transistor in series with a memory cell string and having a corresponding serial select line (SSL) or a ground selection line ( Gates in GSL); SSL and GSL are arranged in parallel with the word lines of the memory array. Switching transistors can also be used in other architectures as a selection block for memory cells.

In high density charge trapping memory cells comprising a three dimensional array, the switching cell system essentially uses the same FET structure as the memory cell, although sometimes with wider channels or other types of adjustment. As such, the switching transistors have a charge trapping structure within the gate dielectric layer. In fabricating this type of charge trapping memory device, charge can accumulate in the gate dielectric layer of the switching transistor and result in a broad distribution of switching transistor thresholds across the device as a whole. This situation will cause many effects on the device that people do not want to happen.

Accordingly, it would be desirable to provide a new memory technology suitable for use in a switching transistor for a charge trapping memory device and including a device arranged in a NAND architecture.

An embodiment relates to a memory device comprising a three-dimensional memory cell array. The three-dimensional memory cell array includes a dielectric charge trapping structure and has a plurality of switching transistors, the switching transistors comprising a gate dielectric structure different from the dielectric charge trapping structure. In some examples, the gate dielectric structure includes a modified dielectric charge trapping structure that is modified to reduce or eliminate the ability of the dielectric charge trapping structure to capture charge.

Another embodiment relates to a three-dimensional inverse (NAND) architecture array comprising a surrounding gate switch transistor.

Yet another embodiment relates to a fabrication method that can be used to form a gate dielectric structure of the memory array of the present invention, the memory array comprising a three dimensional NAND architecture array.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

The embodiments of the present invention will be described in detail in conjunction with Figures 1-24 of the accompanying drawings.

Figure 1 is based on Lue et al ., "A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device," 2010 Symposium on VLSI Technology Digest of A three-dimensional memory (3D memory) diagram drawn by the memory of the Technical Papers, pages 131-132 (Symposium held in June 2010), wherein the dielectric filler is omitted in the figure to clearly reveal the three-dimensional memory Structure. The structure shown in FIG. 1 includes a 3D array of memory cells having a plurality of dielectric charge trapping structures 30 in a (NAND) architecture, wherein the NAND architecture includes A plurality of stacks of NAND strings arranged by memory cells. The structure shown in FIG. 1 includes a plurality of switch transistors coupled to the NAND string, the switch transistors including gate dielectric layers 31 and 32, and gate dielectric layers 31 and 32. It is different from the dielectric charge trapping structure in memory cells.

The three-dimensional memory cell array of FIG. 1 includes a plurality of stacks of semiconductor strips 11, 12, 13 on a substrate 10, the semiconductor strips being arranged to provide a semiconductor for the series memory cells in the NAND string Ontology. In this architecture, the semiconductor strips 11, 12, 13 in each layer of a memory cell are connected in the region 15, forming a single layer bit line layer structure BL(1) which can be used to decode the memory cell. , BL (2), BL (3). The contact structure connecting the bit line layer structures BL(1), BL(2), BL(3) and the upper global bit line (not shown in the figure) is not shown in the figure. The contact structure can be implemented in a patterned metal layer.

A plurality of word lines 17, 18 are orthogonally arranged on the stacks, such that a plurality of interface regions are formed at the intersection of the surface of the semiconductor strips 11, 12, 13 in the stack and the surface of the word line, and The interface areas establish a three dimensional array. The word lines 17, 18 may be formed using polycrystalline germanium by conformally depositing polycrystalline germanium onto the stack and patterning the polycrystalline germanium to define word lines. A vapor layer 22, 23 may be formed on top of the patterned polysilicon, such as tungsten telluride. In Figure 1, the two word line structures are represented by element symbols WL ₁ and WL ₃₂ , wherein the use of element symbol WL ₃₂ indicates that typically a larger number (for example, 32) can be used in a NAND string. ) as the number of the word line. The dielectric charge trapping structure 30 is, for example, an ONO or ONONO multilayer structure deposited in an interface region between a word line and a semiconductor strip to form a memory cell in the structure. The dielectric charge trapping structure 30 can be a blanket layer over a memory cell or a patterned layer. In such a configuration, source/drain ion implantation may be formed between word lines, although such source/drain ion implantation may not be employed in some embodiments.

In this embodiment, a ground select transistor (having a gate in the ground selection line 19) is located at the first end of each NAND string, and a string select transistor (string select transistor, A series of select gates 20) are located at the second end of each NAND string. The ground selection electro-optic system operates to couple the semiconductor strips 11, 12, 13 to a source side bias structure. In this embodiment, the source side bias structure is a common source line. (common source line)16 provided. The tandem selective cell system operates to couple the semiconductor strips 11, 12, 13 to a contact region located in region 15 for connection to a drain side bias structure, such as the aforementioned overall bit line. In this example, a ground select line 19 is orthogonally arranged on the stack and parallel to the word lines 17, 18 and serves as a gate conductor for the ground selection transistor, providing a memory region in response to a single signal. All ridge ridges within the block are connected to the source side biasing structure. A germanide layer 21 can be formed over the ground selection line 19.

Moreover, in this example, the series select gate 20 includes one element that bypasses a single ridge stack at a time. The serially selectable gates 20 that are independently addressable are established to select rows within the memory block. A vapor layer 24, 25 can be formed on top of the tandem select gate 20. The transistors are selected in series to form ends of the strings in the semiconductor strip ridge stack. The series select gates 20 are coupled to the upper source select lines 26, 27 via contact structures 28, 29 such that each ridge stack in the individual selected memory blocks is enabled.

The decoding structure allows the following selection actions to be performed: one word line WL ₁ -WL _{32 is used to} select one of the memory cell XZ planes, and one bit line structure such as BL(1), BL(2), etc. is used to select the memory. One of the XY planes of the cell, and one of the YZ planes of the memory cell is selected using the tandem select line SSL _n ; thereby locating individual memory cells in the selected NAND string.

The gate dielectric layer 32 of the ground selection transistor is different from the dielectric charge trap structure 30 in the memory cell. Similarly, the gate dielectric layer 31 of the serial selection transistor is also different from the dielectric charge trapping structure 30 in the memory cell. The gate dielectric layers 31 and 32 may include a structure for removing a capacitance of a dielectric charge trapping structure for trapping charges, or for making the capacitors by adjusting a dielectric charge trapping structure located in the transistor region of the switch. The structure is obtained by reducing the capacity.

Figure 2 is a schematic diagram of a circuit showing two memory planes each having nine dielectric charge trapping memory cells arranged in a NAND configuration. The circuit depicted in Figure 2 represents a configuration within a memory block or block that can include a number of planes and word lines. Such a circuit can be used, for example, in the structure shown in Fig. 1 or in other types of structures. The two planes formed by the memory cells are accessed by the word lines WL _n-1 , WL _n , WL _n+1 .

The first memory plane formed by the memory cell comprises: memory cells 70, 71, 72 in a NAND string of semiconductor strips, memory cells 73, 74, 75 in a NAND string of another semiconductor strip, And memory cells 76, 77, 78 in a further NAND string of semiconductor strips. The second memory plane formed by the memory cells, in this example, corresponds to the bottom surface of the memory block, and includes memory cells (eg, memory cells 80, 82, 84) arranged in the NAND string, and the memory cells are in the second The arrangement in the memory plane is similar to the arrangement in the first memory plane. Each NAND string is connected at its one end to a ground selection transistor 90-95, and to a common source line (CSL) 99 via a ground selection transistor 90-95.

As shown in FIG. 2, the word line 161 is used as the word line WL _n to extend longitudinally between the stacks such that the word line 161 is coupled to the memory cell in the interface region in the trench (the memory cell of the first plane 71) , 74, 77 and the memory cells 80, 82, 84) of the second plane, the trenches are present between the semiconductor strips in all planes.

In other embodiments, the memory cell strings in adjacent stacks may be alternately arranged in two directions, one direction being the direction from the bit line terminal to the source line terminal, and the other direction being the source line terminal. Point to the direction of the bit line terminal.

The end of the bit line layer structure and the overall bit lines BL _N , BL _N-1 terminate at the memory cell string adjacent to the string selection device. For example, at the top of the memory plane, bit line BL _N terminates in a memory cell string having series select transistors 85, 88, and 89.

In such a configuration, the serial selection transistors 85, 88, and 89 are connected between the individual NAND strings and the string selection lines SSL _n-1 , SSL _n , and SSL _n+1 . The string select lines 106, 107, 108 are connected to the gates of the series select transistors in each NAND string.

The ground selection transistors 90-95 are arranged at the other end of each NAND string. The ground selection transistors couple the strings to a common source line 99.

In this example, ground select line (GSL) 159 is coupled to the gate of ground select transistor 90-95 and may be similar to word line 160, 161, 162. The tandem selection transistor and the ground selection transistor may use a gate dielectric layer including a modified dielectric charge trapping stack, such as the difference between the switching transistor and the symbol of the memory cell shown in FIG. In addition, the length and width of the channels of the switching transistor can be adjusted as desired by the designer to provide a switching function to the transistor.

Figure 3 is a cross-sectional view of a NAND string used in the prior art, the NAND string being formed by a series of dielectric charge trapping flash cells arranged in series. One implementation technique for NAND flash memory uses the band gap engineered SONOS (BE-SONOS) charge trapping technique, as described in Lue's patented technology (U.S. Patent No. 7,315,474). NAND strings can be configured in a variety of ways, including fin field effect transistor (finFET) technology, shallow trench isolation technology, vertical NAND technology, and thin film cell technology. For example, the patented vertical NAND structure proposed by Kim et al. in "Non-Volatile Memory Device and Method of Manufacture and Operation" (European Patent Application Publication No. 2048709).

Referring to FIG. 3, the memory cell system is formed in a semiconductor body 100. For an n-channel memory cell located in an n-type well deep in the semiconductor wafer, the semiconductor body 100 can be an insulated p-well. Alternatively, the semiconductor body 100 can be isolated using an insulating layer or other form. In some embodiments, the semiconductor body is an n-type semiconductor, and a p-channel memory cell is employed.

A plurality of memory cells are arranged in a string extending in the direction of the bit line and orthogonal to the word line. Word lines 202-207 extend across a plurality of NAND strings arranged in parallel. The terminals 212-218 are selectively formed from n-type regions in the semiconductor body 100 (for n-type channel devices) and serve as source/drain regions for the memory cells. A first open relationship is formed by having a gate MOS transistor in the ground select line (GSL) 201 and connected to the memory cell corresponding to the first word line 202 and the n-type region of the semiconductor body 100. Formed between the contact areas 211. Contact region 211 is connected to common source (CS) line 230. A second open relationship is formed by a MOS transistor having a gate in the tandem select line (SSL) 208, and is connected to the memory cell corresponding to the last word line 207 and the n-type region of the semiconductor body 100. Formed between the contact areas 219. The contact area 219 is connected to a one-dimensional line (BL) 231. In the embodiment depicted in FIG. 3, the first and second switches are MOS transistors and have gate dielectric layers 197 and 198 formed by a multilayer structure; and the multilayer structure and memory forming the gate dielectric layers 197, 198 The multilayer structure used in the charge trapping structure in the cell is the same.

For the sake of simplicity, only six memory cells are represented as representatives in the series of FIG. Typically a NAND string can include 16, 32 or more memory cells arranged in series. The memory cells corresponding to word lines 202-207 have a dielectric charge trapping structure between the word lines and the channel regions of semiconductor body 100. In addition, embodiments of the NAND flash architecture have now developed a junction-free architecture, meaning that either endpoints 213-217 and endpoints 212 and 218 in Figure 3 may be omitted from the architecture.

Fig. 4 depicts a NAND string similar to that shown in Fig. 3, and has the same component symbols as those of Fig. 3. In FIG. 4, the gate dielectric layer 258 of the serial selection transistor and the gate dielectric layer 257 of the ground selection transistor are different from the charge trapping structure used by the memory cell. In this example, the gate dielectric layers 257, 258 can be fabricated by a dielectric charge trapping structure forming process, wherein the dielectric charge trapping structure is composed of a dielectric dielectric layer and a charge trapping layer (charge). The trapping layer is composed of a tunneling layer, such as a SONOS-type yttria/tantalum nitride/anthracene oxide (ONO) structure. The dielectric charge trapping structure can be deposited on a blanket deposited layer on the array of memory regions. After deposition of the dielectric charge trapping structure, a patterned mask is used to expose the switching transistor regions of the gate dielectric layers 257, 258. The upper portion (blocking layer and charge trapping layer, such as the oxide and nitride layers of the ONO structure) is removed, leaving a tunneling layer closer to the bottom; the tunneling layer typically includes a germanium oxide Or a layer of ruthenium oxynitride. Next, the overall structure is exposed to an oxidizing gas to increase the thickness of the oxide layer of the tunneling layer and consume a portion of the semiconductor body to form yttrium oxide to form a thicker gate dielectric layer. This configuration enhances the ability of the tandem selection transistor and the ground selection transistor to handle higher voltages and avoids charge trapping conditions that can result in uneven distribution of threshold values of the device.

Fig. 5 depicts a tandem selection terminal similar to the NAND string shown in Fig. 3, and having the same component symbols as those of Fig. 3. In FIG. 5, a gate dielectric layer 268 of a serial selection transistor and optionally a gate dielectric layer of a ground selection transistor (not shown) includes a modified dielectric charge trapping structure, The dielectric charge trapping structure is modified to differ from the charge trapping structure used by the memory cell. In this example, the gate dielectric layer 268 can be fabricated by a dielectric charge trapping structure forming process, wherein the dielectric charge trapping structure is composed of a dielectric barrier layer, a charge trapping layer and a tunneling layer, for example SONOS type yttria/tantalum nitride/anthracene oxide (ONO) structure. The dielectric charge trapping structure can be deposited on a blanket deposited layer on the array of memory regions. After deposition of the dielectric charge trapping structure, a patterned mask is used to expose the switching transistor region of the gate dielectric layer 268. The upper portion (the barrier layer, such as the oxide layer on top of the ONO structure) is removed, leaving a charge trapping layer and a tunneling layer closer to the bottom; the charge trapping layer may comprise about 5-8 nm thick tantalum nitride The tunneling layer typically includes a layer of tantalum oxide or hafnium oxynitride. Since the top barrier is removed, this modified structure does not retain enough charge to affect the overall device. Charge trapping situations that result in uneven distribution of threshold values of the device are therefore avoided.

Fig. 6 depicts a tandem selection terminal similar to the NAND string shown in Fig. 3, and having the same component symbols as those of Fig. 3. In FIG. 6, a gate dielectric layer 278 of a serial selection transistor and optionally a gate dielectric layer of a ground selection transistor (not shown) includes a modified dielectric charge trapping structure, The dielectric charge trapping structure is modified to differ from the charge trapping structure used by the memory cell. In this example, the gate dielectric layer 278 can be fabricated by a dielectric charge trapping structure forming process, wherein the dielectric charge trapping structure is composed of a dielectric layer, a charge trapping layer, and a tunneling layer, such as SONOS. Type of yttria/tantalum nitride/yttria (ONO) structure. The dielectric charge trapping structure can be deposited on a blanket deposited layer on the array of memory regions. After deposition of the dielectric charge trapping structure, a patterned mask is used to expose the switching transistor region of the gate dielectric layer 278. The upper portion (the barrier layer, such as the oxide layer on top of the ONO structure) is removed, leaving a charge trapping layer and a tunneling layer closer to the bottom; the charge trapping layer may comprise about 5-8 nm thick tantalum nitride The tunneling layer typically includes a layer of tantalum oxide or hafnium oxynitride. In addition, a portion of the charge trapping layer is removed to reduce the thickness of the layer. In the case of the tantalum nitride charge trap layer, the thickness of the charge trap layer tends to be reduced to less than 3 nm. Since the barrier layer is removed and the thickness of the charge trapping layer is reduced, this modified structure cannot retain an amount of charge sufficient to affect the overall device. Charge trapping situations that result in uneven distribution of threshold values of the device are therefore avoided.

Fig. 7 depicts a tandem selection terminal similar to the NAND string shown in Fig. 3, and having the same component symbols as those of Fig. 3. In FIG. 7, a gate dielectric layer 288 of a serial selection transistor and optionally a gate dielectric layer of a ground selection transistor (not shown) includes a modified dielectric charge trapping structure, The dielectric charge trapping structure is modified to differ from the charge trapping structure used by the memory cell. In this example, the gate dielectric layer 288 can be fabricated by a dielectric charge trapping structure forming process, wherein the dielectric charge trapping structure is composed of a dielectric layer, a charge trapping layer and a tunneling layer, such as SONOS. Type of yttria/tantalum nitride/yttria (ONO) structure. The dielectric charge trapping structure can be deposited on a blanket deposited layer on the array of memory regions. After deposition of the dielectric charge trapping structure, a patterned mask is used to expose the switching transistor region of the gate dielectric layer 288. The upper portion (the barrier layer, such as the oxide layer on top of the ONO structure) is removed, leaving a charge trapping layer and a tunneling layer closer to the bottom; the charge trapping layer may comprise about 5-8 nm thick tantalum nitride The tunneling layer typically includes a layer of tantalum oxide or hafnium oxynitride. In addition, all or nearly all of the charge trapping layer is removed. Since the charge trapping layer is removed, this modified structure does not retain enough charge to affect the overall device. Charge trapping situations that result in uneven distribution of threshold values of the device are therefore avoided. As mentioned in the related discussion of Fig. 4, the tunneling oxide layer in some embodiments is very thin and has a thickness of only about 3 nm or less. Therefore, it can be further processed to increase the thickness of the tunneling oxide layer to improve performance under high voltage conditions. In addition, a dielectric material that does not capture an amount of charge sufficient to affect it can be additionally deposited to increase the thickness of the gate dielectric layer.

If an oxidation step is used to thicken the gate dielectric layer 288, a portion of the germanium substrate can be consumed. In a generally employed process for oxidizing and exposing a silicon layer to form an oxide, the germanium layer is consumed such that the thickness ratio d2/d1 is about 55/45, wherein the thickness d2 is greater than the oxide layer. The thickness of the initial level of the layer, the thickness d1 is the thickness of the oxide layer below the initial level of the ruthenium layer. By applying an oxidation step to the structure having a thin tunnel oxide layer thereon at the beginning as shown in Fig. 7, a thicker oxide layer having a thickness ratio d2/d1 greater than 55/45 can be formed. This result is quite important for the embodiment of the thin film transistor and the three-dimensional embodiment below.

In other embodiments, the tunnel oxide layer can be replaced by a BE-SONOS multilayer tunneling layer, as described in more detail below. Modification of the charge trapping structure may use a method similar to that described above, including removing only the barrier layer, removing the barrier layer and completely or partially oxidizing the thicker charge trapping nitride layer, removing the barrier layer, and all of the charge trapping layer. A plurality of tunneling layers are left, and the multilayer tunneling layer is exposed and oxidized to transform the thinner tantalum nitride layer into an oxide layer, or to diffuse oxygen to the substrate, or both.

Figures 8-10 depict one embodiment of a memory array in which a switched transistor (not shown) may employ a modified gate dielectric layer. Figure 8 is a perspective view of a 2x2 portion of a three-dimensional charge trapping memory array, the filler being omitted from the figure to show the components of the three-dimensional array, the constituent portion including the semiconductor strip stack and the word lines orthogonal thereto . The three-dimensional array of Fig. 8 only shows a two-layer structure as a representative, whereas a three-dimensional array may contain many layers. As shown in Fig. 5, the memory array is formed on an integrated circuit substrate and has an insulating layer 810 on the underlying semiconductor or other structure (not shown). The memory array includes a plurality of stacks (two are shown), and is composed of semiconductor strips 811, 812, 813, and 814 and insulating materials 821, 822, 823, and 824 separating the semiconductor strips. The stacks are ridged stacks extending along the Y-axis direction of the illustration, so the semiconductor strips 811-814 can be configured as a memory cell string. The semiconductor strips 811 and 813 can serve as a memory cell of a first memory plane, and the semiconductor strips 812 and 814 can serve as a memory cell of a second memory plane.

The insulating material 821 between the semiconductor strips 811 and 812 in the first stack and the insulating material 823 between the semiconductor strips 813 and 814 in the second stack have an effective oxide thickness of about 40 nm or more ( Effective oxide thickness (abbreviated as EOT), EOT is a standardization of the thickness of the insulating material based on the ratio of the dielectric constant of the cerium oxide to the dielectric constant of the selected insulating material. The aforementioned "about 40 nm" indicates that there is a standard deviation of about 10% in the manufacture of this type of structure. The thickness of the insulating material is the key to the reduction interface between adjacent memory cells in this structure. In some embodiments, the EOT of the insulating material can be as small as 30 nanometers while still providing sufficient insulation between the layers.

In this example, a memory material layer 815, such as a dielectric charge trapping structure, is coated onto a plurality of semiconductor strip stacks. A plurality of word lines 816, 817 are orthogonally arranged over the plurality of semiconductor strip stacks. The word lines 816, 817 have surfaces conformal to the semiconductor strip stack and fill the trenches defined by the stacks (eg, trenches 820) and define a semiconductor strip 811-814 located in the stack. The intersection of the side surface and the word lines 816, 817 constitutes a multilayer array of interface areas. A vapor layer (e.g., tungsten telluride, cobalt telluride, titanium telluride layer) 818, 819 may be formed on top of word lines 816, 817.

Therefore, a three-dimensional array composed of SONOS-type memory cells disposed in the NAND flash array can be formed. The source, drain and channel are formed in the bismuth (S) semiconductor strips 811-814, and the memory material layer 815 comprises a tunneling layer 837 formed of yttrium oxide (O), which may be formed by tantalum nitride (N). A charge storage layer 838 and a dielectric barrier layer 839 formed of ruthenium oxide (O). The gate of the memory cell includes polysilicon (S) of word lines 816, 817.

The semiconductor strips 811-814 can be p-type semiconductor materials. The word lines 816, 817 can be semiconductor materials having the same or different conductivity types (e.g., p+ type) as the semiconductor strips 811-814. For example, the semiconductor strips 811-814 may use p-type polycrystalline germanium or p-type epitaxial single crystal germanium as the material, while the word lines 816, 817 may use relatively heavily doped p+ type polycrystalline germanium as the material.

Alternatively, the semiconductor strips 811-814 can be n-type semiconductor materials. The word lines 816, 817 can be semiconductor materials having the same or different conductivity types (e.g., p+ type) as the semiconductor strips 811-814. This n-type semiconductor strip layout results in a latent channel depletion charge trapping memory cell. For example, the semiconductor strips 811-814 can use n-type polycrystalline germanium or n-type epitaxial single crystal germanium as the material, while the word lines 816, 817 can use relatively heavily doped p+ type polycrystalline germanium as the material. The doping concentration of the n-type semiconductor strips is usually about 10 ¹⁸ per cubic centimeter, and in the examples which may be used, the concentration may range from 10 ¹⁷ to 10 ¹⁹ per cubic centimeter. The use of n-type semiconductor strips is particularly advantageous for endless embodiments, which increase the conductivity along the NAND string direction, allowing for higher read currents.

Thus, a memory cell having a charge storage structure and including a field effect transistor is formed in a three dimensional array of the intersections. The width of the semiconductor strips and word lines is about 25 nm, and the ridge stacks are also about 25 nm apart. Devices with tens of layers (for example, 32 layers) are in a single wafer. Capacity up to megabits (10 ¹² bit).

Memory material layer 815 can include other charge storage structures. For example, a gap-gap engineering SONOS (BE-SONOS) charge storage structure comprising a tunneling layer 837 can be used, wherein the tunneling layer 837 comprises a material that forms an inverted U-shaped valence band with a bias voltage of zero. The composite structure composed. In one embodiment, the composite structure tunneling dielectric layer includes a first layer called a hole tunneling layer, and a second layer called a band offset layer. A layer and a third layer called an isolation layer. In this embodiment, the hole tunneling layer of the memory material layer 815 includes cerium oxide on the side surface of the semiconductor strip, formed by, for example, in-situ steam generation (ISSG), on-site vapor generation technology. Selective nitridation by post deposition of NO anneal or by addition of NO to the surrounding environment by deposition. The first layer composed of cerium oxide has a thickness of less than 20 angstroms ( The thickness of the layer is preferably 15 angstroms or less. In a representative embodiment, the thickness can be 10 angstroms or 12 angstroms.

In this embodiment, the energy band offset layer is composed of tantalum nitride on the tunneling layer, and is formed by, for example, low-pressure chemical vapor deposition (LPCVD) using, for example, dichlorosilane. , DCS) and ammonia (NH ₃ ) are precursors for LPCVD at 680 °C. Alternatively, in an alternative process, the band offset layer comprises bismuth oxynitride and is formed in a similar manner using a nitrous oxide (N ₂ O) precursor. The tantalum nitride band offset layer has a thickness of less than 30 angstroms, and preferably 25 angstroms or less.

In this embodiment, the spacer layer is composed of cerium oxide on the tantalum nitride band offset layer, and is formed by, for example, LPCVD or high temperature oxide (HTO) deposition. The thickness of the ceria barrier layer is less than 35 angstroms, and preferably 25 angstroms or less. This three-layer structure tunneling layer results in an inverted U-shaped valence band energy level.

a valence band energy level at the first location, such as an electric field generated by tunneling a hole through a thin region between the semiconductor body and the first location interface, and sufficient to increase the valence band energy level after the first location to The extent to which the hole tunneling barrier of the composite tunneling dielectric located at the first location can be effectively eliminated. The structure establishes an inverted U-shaped valence band energy level in the tunneling dielectric layer having a three-layer structure, and enables the electric field to be assisted by tunneling at a high speed, and the electric field is reduced in the absence of an electric field or for other operational purposes. In a small situation, the charge leakage through the composite tunneling dielectric layer is effectively avoided; the aforementioned situation in which the electric field is reduced for other operational purposes is, for example, reading data from a memory cell or writing to an adjacent memory cell.

In a representative device, the memory material layer 815 comprises a band gap engineering composite tunneling dielectric layer, the composite tunneling dielectric layer comprising a cerium oxide layer greater than 2 nm thick and a nitrogen layer less than 3 nm thick The ruthenium layer and a layer of ruthenium dioxide less than 4 nm thick. In one embodiment, the composite tunneling dielectric layer is formed of an ultra-thin yttria layer (hereinafter referred to as an O1 layer, having a thickness of, for example, less than or equal to 15 angstroms), and an ultra-thin tantalum nitride layer (hereinafter referred to as an N1 layer, thickness) For example, less than or equal to 30 angstroms) and another ultra-thin yttria layer (hereinafter referred to as an O2 layer, the thickness is, for example, less than or equal to 35 angstroms), such that the valence band energy is less than or equal to 15 from the semiconductor body interface. One of the angstroms increased by about 2.6 eV (eV) from the zone. The O2 layer has a lower valence band energy level (having a higher hole tunneling energy barrier) and a region of a higher conductivity band energy level, and is in a second offset region (for example, the distance from the interface is about 30~) 45 angstroms) Separating the N1 layer from the charge trapping layer. Since the second offset region is far away from the interface, the electric field of the tunnel tunneling is sufficient to increase the valence band energy level after the second offset region to the extent that the tunnel tunneling energy barrier can be effectively eliminated. Therefore, the O2 layer does not significantly interfere with the electric field of the auxiliary hole tunneling, and at the same time improves the charge leakage of the energy gap engineering composite tunneling dielectric layer under the condition of a small electric field.

In this embodiment, the charge trapping layer of memory material layer 815 comprises tantalum nitride having a thickness greater than 5 nanometers, such as tantalum nitride containing 7 nanometers thick, in this embodiment, for example, formed by LPCVD. Other charge trapping materials and structures may also be employed, including, for example, silicon oxynitride (Si _x O _y N _z ), silicon-rich nitride, silicon-rich oxide (silicon-rich). Oxide), as well as capture layers containing embedded nanoparticles, and so on.

In this embodiment, the barrier dielectric layer of the memory material layer 815 comprises cerium oxide having a thickness greater than 5 nanometers, for example, 9 nm thick cerium oxide in this embodiment, and can be processed in a vapor oxidizing furnace ( Wet furnace oxidation process) is formed by wet conversion of nitride. Other embodiments may employ cerium oxide formed by HTO deposition or LPCVD. Other barrier dielectric materials may comprise a high-kappa material, such as alumina.

In a representative embodiment, the tunneling layer may be 1.3 nm thick ruthenium oxide, the offset layer may be 20 angstroms of tantalum nitride, and the isolation layer may be 2.5 nm thick ruthenium dioxide, charge The capture layer can be 7 nm thick tantalum nitride and the barrier dielectric layer can be 9 nm thick tantalum oxide. The gate material is a p+ type polysilicon used in word lines 816, 817 with a work function of about 5.1 electron volts.

FIG. 9 is a cross-sectional view showing the charge trapping memory cell formed at the interface between the word line 816 and the semiconductor strip 814 in FIG. 8 taken along the X-Z plane. An active charge trapping region 825, 826 is formed on both sides of the semiconductor strip 814 and between the word line 816 and the semiconductor strip 814. In the embodiment described herein, each of the memory cells is a dual gate field effect transistor having charge trapping active regions 825, 826, wherein the charge trapping active regions 825, 826 are respectively located on opposite sides of the semiconductor strip 814. The electron flow is indicated by a dashed arrow in Fig. 9 flowing in the direction of the p-type semiconductor strip to the sense amplifier, and the state of the selected memory cell can be indicated by the sense amplifier for the quantity side of the electron current.

FIG. 10 is a cross-sectional view showing the charge trapping memory cell formed at the interface between the word lines 816, 817 and the semiconductor strip 814 in FIG. 8 taken along the X-Y plane. The flow of electrons flowing along the semiconductor strip 814 is depicted in FIG. The source/drain regions 828, 829, 830 between the word line 816 and the word line 817 can be in the form of no end points, and do not need to dope the source and the drain so that they have a bit in the word line. The opposite channel is of the opposite conductivity type. In an endless embodiment, the charge trapping field effect transistor can have a p-type channel structure. In some embodiments, after the word line is defined, the source and drain can also be doped with a self-aligned implant.

In an alternate embodiment, a lightly doped n-type semiconductor body can be used in the endless layout as the semiconductor strips 811-814, which results in the formation of a depleted mode of operation of the buried channel field effect transistor, and Charge trapping memory cells naturally transition to a lower critical value distribution.

Figures 11-19 depict a basic flow of steps for fabricating a three-dimensional memory array as described above, the array comprising a gate dielectric layer of a switching transistor, and the switching transistor comprising a modified charge trapping structure. FIG. 11 illustrates a structure formed by alternately deposited insulating layers (labeled at 406, 408, 410, 412, 414) and semiconductor layers (labeled at 407, 409, 411, 413), wherein 407, The semiconductor layer formed at 409, 411, 413 is formed by depositing a doped semiconductor, for example, on a blanket deposition layer of a substrate array region. The substrate in this example includes an underlying insulating layer 405 and a semiconductor wafer 404. Depending on the fabrication process, the semiconductor layer can be fabricated using deposited or grown n-type or p-type polycrystalline germanium or single crystal germanium. For the production of the interlayer insulating layer, for example, cerium oxide, other kinds of cerium oxide or cerium nitride can be used. The semiconductor layers and insulating layers described herein can be formed in a variety of ways, including LPCVD processes well known to those of ordinary skill in the art to which the present invention pertains.

Figure 12 illustrates the result of a first lithographic patterning step for defining a plurality of ridge stacks 450-1, 450 formed by semiconductor strips as local bit lines. 2, 450-3. In Fig. 12, the semiconductor strips 407, 409, 411, 413 are formed of a material of a semiconductor layer separated from each other by an insulating material (e.g., portions indicated by 408, 410, 412, 414) and dielectrically insulated. The material strip 406 is separated from the substrate (404, 405). A trench having a certain depth and a high aspect ratio can form and support a plurality of layers between the stacks, and the trench is formed by using a carbon hard mask and reactive ion etching. ) lithography based processes.

FIG. 13 illustrates the result of depositing a blanket deposited layer of a multilayer charge trapping structure 315; as described above, the multilayer charge trapping structure 315 includes a tunneling layer 397, a charge trapping layer 398, and a Barrier layer 399. As shown in FIG. 13, tunneling layer 397, charge trapping layer 398, and barrier layer 399 are deposited in a conformal blanket over semiconductor elongated ridge stacks 450-1, 450-2, 450-3. The tunneling layer 397, the charge trapping layer 398, and the barrier layer 399 may include a BE-SONOS charge trapping structure as described above, and the tunneling layer (eg, 397) in the BE-SONOS charge trapping structure is composed of a multilayer tunneling structure composition.

Figure 14 depicts the photomask fill after application and patterning of the photoresist fill in the structure shown in Figure 13 to form a mask region for protecting the multilayer charge trapping structure 315 on the memory cell ( The mask block 430 protects the multilayer charge trapping structure 315 from being altered during the process of forming the gate dielectric layer of the switching transistor.

Figure 14 provides a simplified perspective view of the structure in which the reticle block 430 exposes the switching transistor region of the multilayer charge trapping structure 315; the switching transistor region will be modified to, for example, as shown in Figure 1 The switching transistor at the string selection line SSL and the ground selection line GSL forms a gate dielectric layer. Although in FIG. 15, the opening extends to the end of the semiconductor strip; in a preferred embodiment, the opening is confined to the switching transistor region in a more rigorous manner, and the opening includes orthogonal to the semiconductor layer The trenches of the semiconductor strips 407, 409, 411, 413 are formed to form a ground selection line in a subsequent process, and include openings corresponding to the gate structure layout to facilitate formation of a tandem selection transistor similar to the embodiment shown in FIG. .

Figure 15 depicts the resulting structure from the next step of the process after the top barrier layer 399 of the multilayer charge trapping structure 315 is removed from the exposed areas of the reticle block 430. In embodiments where the barrier layer 399 is yttria, the removal of the barrier layer 399 can be, for example, a buffered oxide etch (BOE) dip process.

Figure 16 depicts the structure formed by a step below the process after removal of the reticle block 430. In embodiments where the reticle block includes a light group reticle, the photomask reticle can be removed using a photoresist strip process. The resulting structure includes a ridge stack 450-1, 450-2, 450-3 formed by semiconductor strips having a dielectric charge trapping structure in the memory cell regions (ie, sidewalls of the semiconductor strips 407, 409, 411, 413). And the top layer of the dielectric charge trapping structure at the switching transistor of the tandem select line and the ground select line is removed, exposing the intermediate layer charge trapping layer 398 (nitride in this example). With this configuration, the gate dielectric layer at the switching transistor of the series select line and the ground select line in the semiconductor strip can be completed, for example, as described in the related discussion section of Figures 4-7.

Figure 17 depicts the resulting structure via the next step in the process, removed from the charge trapping layer 398 from the switching transistor of the tandem select line and the ground select line, exposing the underlying tunneling layer 397 (e.g., oxide tunneling) After the layer, or the tunneling layer of the ONO structure of BE-SONOS). Wherein the charge trapping layer 398 comprises a tantalum nitride layer, which can be removed, for example, by hot phosphoric acid dip, which is highly selective for the removal of tantalum nitride without Etching yttrium oxide. This step leaves the multi-layer (dielectric) charge trapping structure 315 of the memory cell region leaving only the bottom tunneling layer 397 at the switching transistor of the string select line and the ground select line.

Figure 18 depicts the results of the structure after passing through a process associated with the multilayer charge trapping structure 315. As described above, the exposed portions of the multilayer charge trapping structure 315 at the switching transistor gate dielectric layer are removed and modified to form a gate dielectric overlying the sidewalls of the semiconductor strips 407, 409, 411, 413. Electrical layer 490. The modifications may be made to any of a variety of processes, such as those described in the related discussion section of Figures 4-7 above. As shown in Fig. 16, the multi-layer charge trapping structure 315 of the memory cell region is unmodified as it is. In this example, a process is employed to increase the thickness of the tunneling layer 397. By applying a thermal oxidation process to the tunneling layer oxide, the germanium of the semiconductor strip sidewall is converted into cerium oxide to form a thicker layer. The gate dielectric layer 490. In this embodiment, in the embodiment described herein, the gate dielectric layer at the switching transistor of the serial selection line and the ground selection line has a thickness d2, d2 exceeding the initial level of the germanium layer. The sum of the thickness of the oxide layer and the tunneling layer, and the thickness d1 below the initial level of the germanium layer, so that the thickness ratio d2/d1 is greater than 55/45. As described above, the application of an oxidation process to the tunneling oxide allows a relatively thick gate dielectric layer to be formed while converting germanium in the semiconductor strip. Alternatively, a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process may be employed to increase the thickness of the tunneling layer and form the gate dielectric layer 490. For embodiments with smaller pitches, it may be more desirable to use either CVD or ALD to preserve germanium in the semiconductor strips, since germanium in the semiconductor strip is required to provide the switching transistor Channels and connections to local bit line structures.

Figure 19 is a diagram showing the result of applying a high aspect ratio fill step to the structure, and showing the position of the memory array region 600 and the tandem selection line/ground selection line region 601 in the structure; The high aspect ratio filling step deposits and patterns a conductive material such as an n-type or p-type doped polysilicon, and an n-type or p-doped polycrystalline germanium is used as the word line and the select line. High aspect ratio deposition techniques such as the deposition of polysilicon by the LPCVD method described above, as shown in Figure 17, are used to completely fill the trenches between the ridge stacks, even fully filled, for example, having a width of only about 10 nm and having Very narrow groove with high aspect ratio. A lithography patterning step can be used to define a plurality of word line lines 460-1, 460-2 and a ground selection line 461 for the three dimensional memory array. The word lines 460-1, 460-2 and the ground selection line 461 may have the same or different widths. In this step, the gate structure controlled by the string selection line (not shown) (as in Fig. 1, the structure of the series selection gate 20) can also be defined. The lithography patterning step uses a single mask to form the critical dimension of the array, etching trenches with high aspect ratios between word lines, without etching through the ridge stack. The polysilicon can be etched using an etch process that is highly selective for polycrystalline germanium on yttrium oxide or tantalum nitride. An alternative etch process can therefore be used to etch through the semiconductor layer and the insulating layer with the same mask and terminate at or near the bottom insulating layer 405 on the substrate.

An optional process step includes forming a hard mask over the plurality of word lines and forming a hard mask over the gate structure. The hard mask can be formed using a layer of tantalum nitride (or other material) that is relatively thick to block the ion implantation process. After the hard mask is formed, an ion implantation can be employed to increase the doping concentration of the semiconductor strip and the stair step structure, thereby reducing the resistance of the current path along the semiconductor strip. By using controlled implant energy, ions can be implanted deep into the bottom of the semiconductor strip and the semiconductor strips on the stack. In some embodiments, germanides can be used for word lines and ground select lines to increase the electrical conductivity of the structure.

The hard mask is then removed to expose the surface of the word line on the gate structure. After an interlayer dielectric is formed on top of the array, a plurality of vias are formed, and a contact plug formed, for example, by tungsten filling, is formed in the vias and extends to the gate structure. Upper surface. The overlying metal lines are patterned to connect and serve as a series select line and an overall bit line.

Figures 20 through 23 depict the steps of one of the variations of the process shown in Figures 11-19, which can be used to form a surrounding gate switch transistor in a three dimensional array. The process can perform the process described above to the step of FIG. 17, which is to remove the barrier layer 399 and the charge trapping layer 398 at the switching transistor of the serial selection line and the ground selection line of the multilayer charge trapping structure. the result of. Figure 20 illustrates the length of the polycrystalline germanium semiconductor from the dielectric material strips 406, 408, 410, 412, 414 (in this case, hafnium oxide) from the ridge stacks 450-1, 450-2, 450-3. Strip 407, 409, 411, 413 are removed between the switching transistor of the serial selection line and the ground selection line, leaving a complete strip of dielectric material 406, 408, 410, 412, 414 in the memory cell region. After the step, the structure presented. In the case where the dielectric material strips 406, 408, 410, 412, 414 are tantalum oxide, the barrier layer 399 in the dielectric charge trapping structure includes tantalum oxide, the intermediate layer includes tantalum nitride, and the tunneling layer includes tantalum oxide. Such a structure can be accomplished by the application of a buffered oxide (hydrogen fluoride) etch which is highly selective for the removal of yttrium oxide. In the case where the multilayer dielectric charge trapping structure includes a multi-layer tunneling layer, such as a BE-SONOS type structure, an additional step may be required to remove those that cannot be removed using the dielectric strip. Material removed by etching. After removing the strip of dielectric material from the structure, the semiconductor strips 407, 409, 411, 413 float across openings in the switching transistor at the string select line and the ground select line, the semiconductor strips 407, 409 The surfaces of 411, 413 are exposed in all directions.

Figure 21 illustrates the result of the structure after forming a wraparound gate dielectric layer (e.g., 500a, 500b, 500c, 500d); a wraparound gate dielectric layer (500a, 500b, 500c, 500d) The semiconductor strips 407, 409, 411, 413 are exposed on the outer surface of the switching transistor formed at the tandem selection line and the ground selection line. To this end, a thermal oxidation process that consumes germanium strips 407, 409, 411, 413 can be employed. For embodiments with smaller pitches, CVD or ALD processes are preferred. Other gate dielectric materials other than yttrium oxide, such as aluminum oxide or dielectric materials having a high dielectric constant, may also be employed in conjunction with certain embodiments. This step also forms a gate dielectric layer 501 on the charge trapping layer 398 of the dielectric charge trapping structure of the memory cell. The gate dielectric layer 501 can serve as a barrier layer for the dielectric charge trapping structure. Alternatively, a material other than the material used for the surrounding gate dielectric layer can be used as the barrier dielectric material using suitable photomask techniques and deposition techniques.

Figure 22 depicts the structure formed by the next steps in the process, including a memory array region 600 and a tandem select line/ground select line region 602 having a wraparound gate without a capture structure. It is applied in a manner similar to filling a gap of the surrounding gate dielectric layers (500a, 500b, 500c, 500d) on the semiconductor strips 407, 409, 411, 413, for example, including polycrystalline germanium. A conductive fill is patterned and patterned to form word lines 510 and 511, a ground select line 512, and a tandem select line gate structure (not shown) to form a wraparound gate transistor. In embodiments where the electrically conductive filler comprises polycrystalline germanium, a vaporized layer (not shown) may be formed on the electrically conductive filler.

Figure 23 provides a cross-sectional view of the structure of Figure 22, which is a section of the ridge stack 405-3 along the ground select line switching transistor (GSL swich) portion to show the memory cell structure in the memory array region. As shown, the ground select line switch transistor has a wraparound gate structure, and the memory cell system includes a plurality of charge trapping structures on the sidewalls of the semiconductor strips 407', 409', 411', and 413' (397, 398, 399).

The process of adjusting according to Figures 20-23 is a method of forming a memory device, the memory device comprising a three-dimensional memory cell array and a plurality of switching transistors, wherein the three-dimensional memory cell array is connected to the stack of NAND strings including The electric charge trapping structure is a double-gate thin film transistor, and the switching transistor system is coupled to the NAND strings including the surrounding gate transistors.

The wraparound gate transistor increases the conductivity of the switch during operation, reduces power consumption, and increases speed. In an example of configuring a NAND flash memory, a program that relies on self-boosting of unselected strings to suppress program disturb, such as an incremental step pulse program (incremental) Step pulse programming), the string selection line and the ground selection line wrap-around gate transistor can improve the efficiency of the program operation. In order to have good self-boosting efficiency, a low leakage current is quite important. The wraparound gate embodiment described herein provides a tandem select line/ground select line switch transistor with very low leakage current. For example, a wraparound gate transistor can help reduce sub-threshold swing (SS), thereby reducing leakage.

Figure 24 is a simplified block diagram of an integrated circuit 975 comprising a NAND flash memory array 960, wherein the switching transistor of the NAND flash memory array 960 has a gate dielectric layer different from the charge trapping structure. In some embodiments, NAND flash memory array 960 can include multiple layers of memory cells. A column of decoders 961 is coupled to a plurality of word lines 962 arranged along a column of NAND flash memory arrays 960. Row decoder 966 is coupled to a set of page buffers 963 via data bus 967 in this example. The overall bit line 964 is coupled to local bit lines (not shown) arranged along the rows of the NAND flash memory array 960. The address is provided by bus bar 965 to row decoder 966 and column decoder 961. The data is provided by other circuits 974 (including, for example, input/output ports) of the integrated circuit that can be used for data input, such as a general-purpose processor or a special purpose application circuit (special). Purpose application circuitry), or a combination of multiple modules that provide system-on-a-chip functionality supported by NAND flash memory array 960. The data is provided via line 973 to an input/output port or other data destination located inside or outside of integrated circuit 975.

A controller, in this example a state machine 969, provides signals to control the application of the bias configuration supply voltage to perform various operations described herein, the bias configuration supply voltage being located at block 968 Generated or provided by one or more voltage supplies. These jobs include erase, write, and level reads, which are read with different read bias conditions to read the layers of NAND flash memory array 960. The controller may also be a special-purpose logic circuitry known to those of ordinary skill in the art to which the invention pertains. In an alternate embodiment, the controller includes a general purpose processor that can be in the same integrated circuit and that executes a computer program to control the operation of the device. In another alternative embodiment, a combination of special purpose logic circuitry and a general purpose processor can be used as a controller.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10. . . Substrate

11, 12, 13, 407, 407', 409, 409', 411, 411', 413, 413', 811, 812, 813, 814. . . Semiconductor strip

15. . . region

16, 99, 230. . . Common source line

17, 18, 160, 161, 162, 202, 203, 204, 205, 206, 207, 460-1, 460-2, 510, 511, 816, 817, 962. . . Word line

19, 159, 201, 461, 512. . . Ground selection line

20. . . Tandem selection gate

21, 22, 23, 24, 25, 818, 819. . . Telluride layer

26, 27. . . Source selection line

28, 29. . . Contact structure

30. . . Dielectric charge trapping structure

31, 32, 197, 198, 257, 258, 268, 278, 288, 490, 501. . . Gate dielectric layer

70, 71, 72, 73, 74, 75, 76, 77, 78, 80, 82, 84. . . Memory cell

85, 88, 89. . . Tandem selection transistor

90, 91, 92, 93, 94, 95. . . Ground selection transistor

100. . . Semiconductor body

106, 107, 108, 208. . . Serial selection line

211, 219. . . Contact area

212, 213, 214, 215, 216, 217, 218. . . End point

231. . . Bit line

315. . . Multilayer charge trapping structure

397, 837. . . Tunneling layer

398. . . Charge trapping layer

399. . . Barrier layer

404. . . Semiconductor wafer

405. . . Insulation

406, 408, 410, 412, 414. . . Dielectric material strip

430. . . Mask block

450-1, 450-2, 450-3. . . Ridge stack

500a, 500b, 500c, 500d. . . Wraparound gate dielectric

600. . . Memory array area

601, 602. . . Tandem select line / ground select line area

810. . . Insulation

815. . . Memory material layer

820. . . Trench

821, 822, 823, 824. . . Insulation Materials

825, 826. . . Charge trapping active region

828, 829, 830. . . Source/bungee area

838. . . Charge storage layer

839. . . Dielectric barrier

960. . . NAND flash memory array

961. . . Column decoder

963. . . Page buffer

964. . . Overall bit line

965. . . Busbar

966. . . Row decoder

967. . . Data bus

968. . . Block

969. . . state machine

973. . . line

974. . . Other circuit

975. . . Integrated circuit

BL(1), BL(2), BL(3). . . Bit line layer structure

BL, BL _N , BL _N-1 . . . Bit line

CS. . . Common source

CSL. . . Common source line

E-current. . . electron flow

GSL. . . Ground selection line

Source Line. . . Source line

SSL, SSL _n , SSL _n+1 , SSL _n-1 . . . Serial selection line

WL, WL ₁ , WL ₃₂ , WL _n , WL _n+1 , WL _n-1 . . . Word line

Figure 1 is a perspective view of the basic structure of a three-dimensional NAND architecture charge trapping memory device.

Figure 2 is a simplified schematic diagram of a three-dimensional NAND architecture charge trapping memory device.

Figure 3 is a simplified cross-sectional view of a NAND string drawn in accordance with prior art embodiments in which the charge trapping structure acts as a gate dielectric layer for the tandem select transistor and the ground select transistor.

4 is a simplified cross-sectional view of a NAND string having a tandem selection transistor and a ground selection transistor according to an embodiment of the present specification.

Figure 5 is a simplified cross-sectional view of a tandem select terminal of a NAND string, the tandem select terminal being located within a tandem select transistor and a ground select transistor according to another embodiment of the present specification.

Figure 6 is a simplified cross-sectional view of a tandem selection terminal of a NAND string, the serial selection terminal being located in a tandem selection transistor and a ground selection transistor according to yet another embodiment of the present specification.

Figure 7 is a simplified cross-sectional view of a tandem selection terminal of a NAND string, the serial selection terminal being located in a tandem selection transistor and a ground selection transistor according to yet another embodiment of the present specification.

Figure 8 is a perspective view of a three-dimensional NAND flash memory structure including a plurality of planes formed by semiconductor strips parallel to the Y-axis and arranged in a plurality of ridge stacks, one of the side surfaces of the semiconductor strips A charge trapping memory layer and a plurality of word lines arranged on the ridge stack and having a bottom surface conformal to the ridge stack.

Fig. 9 is a sectional view of the memory cell obtained by cutting the structure shown in Fig. 8 along the X-Z plane.

Fig. 10 is a sectional view of the memory cell obtained by cutting the structure shown in Fig. 8 along the X-Y plane.

Figure 11 depicts the first step in the fabrication of a memory device as shown in Figure 1.

Figure 12 depicts a second step in the fabrication of a memory device as shown in Figure 1.

Figure 13 depicts a third step in the fabrication of a memory device as shown in Figure 1.

Figure 14 depicts a fourth step in the fabrication of a memory device as shown in Figure 1.

Figure 15 depicts a fifth step in the process of fabricating a memory device as shown in Figure 1.

Figure 16 depicts a sixth step in the process of fabricating a memory device as shown in Figure 1.

Figure 17 depicts a seventh step in the fabrication of a memory device as shown in Figure 1.

Figure 18 depicts an eighth step in the process of fabricating a memory device as shown in Figure 1.

Figure 19 depicts the ninth step of fabricating the process of the memory device as shown in Figure 1.

Figures 20 through 23 depict an alternative step in the fabrication of a memory device as shown in Figure 1 for fabricating a wraparound gate switch transistor.

Figure 24 is a schematic illustration of an integrated circuit comprising a three-dimensional NAND flash memory array having a modified gate dielectric layer on the switching transistor of the NAND flash memory array.

100. . . Semiconductor body

201. . . Ground selection line

202, 203, 204, 205, 206, 207. . . Word line

208. . . Serial selection line

211, 219. . . Contact area

212, 213, 214, 215, 216, 217, 218. . . End point

230. . . Common source line

231. . . Bit line

257, 258. . . Gate dielectric layer

BL. . . Bit line

CS. . . Common source

GSL. . . Ground selection line

SSL. . . Serial selection line

WL. . . Word line

Claims (33)

A memory device comprising: a three-dimensional memory cell array comprising a plurality of dielectric charge trapping structures, the three-dimensional memory cell array comprising a plurality of NAND strings arranged by memory cells And a plurality of switching transistors coupled to the plurality of switching gates, the switching transistors comprising a plurality of gate dielectric structures, wherein the gate dielectric structures are different from the dielectrics Charge trapping structure. The memory device of claim 1, wherein the switch transistors comprise a plurality of serial selection transistors and a plurality of ground selection transistors, and the series selection transistors are disposed on the opposite gates At one end of the series, the ground selection transistors are coupled to the other ends of the anti-gate columns. The memory device of claim 1, wherein the dielectric charge trapping structure comprises a tunneling layer, a charge trapping layer and a barrier layer, and the gate dielectric structures comprise the tunneling layer And some or all of the charge trapping layer, but not including the barrier layer. The memory device of claim 1, wherein the dielectric charge trapping structure comprises a tunneling layer, a charge trapping layer and a barrier layer, and the gate dielectric structures comprise the tunneling layer And a layer containing the charge trapping layer completely or partially oxidized, but does not include the barrier layer. The memory device of claim 1, wherein the dielectric charge trapping structure comprises a tunneling layer, a charge trapping layer and a barrier layer, and the gate dielectric structures comprise the tunneling layer But does not include the charge trapping layer and the barrier layer. The memory device of claim 1, wherein the dielectric charge trapping structure comprises a tunneling layer, a charge trapping layer and a barrier layer, and the gate dielectric structures are included in the tunneling An oxide layer obtained by oxidation in the presence of a layer, but not including the charge trapping layer and the barrier layer, such that the thickness d2 of the oxide layer beyond the initial level of the tunnel of the switching transistor and the oxide layer being lower than the initial layer The thickness d1 of the thickness is greater than the thickness d2/d1 is greater than 55/45. The memory device of claim 1, wherein the dielectric charge trapping structures comprise a tunneling layer, a charge trapping layer and a barrier layer, and the gate dielectric structures comprise germanium oxide Or a layer of bismuth oxynitride. The memory device of claim 1, wherein the dielectric charge trapping structures have a first thickness between the corresponding semiconductor strips and the word lines, and the gate dielectric structures are in phase A second thickness is formed between the corresponding semiconductor strip and the select line, and the second thickness is less than the first thickness. The memory device of claim 1, wherein the switching transistors comprise a plurality of surrounding gate transistors. The memory device of claim 1, wherein the material of the gate dielectric structures surrounds a plurality of semiconductor strips located in the stacks; and at least one of the select lines is filled in the stacks Among these semiconductor strips. A memory device comprising: a plurality of stacks, consisting of semiconductor strips, ridge-shaped, and comprising at least two semiconductor strips separated by different layers of a plurality of layers of an insulating material, The stack has a first end and a second end; a plurality of word lines are disposed on the stack and orthogonally arranged with the stacks to make the stack surfaces and the surface of the word lines Forming a plurality of interface regions at the intersection, the interface regions establishing a three-dimensional array; a plurality of dielectric charge trapping structures comprising a plurality of dielectric layers located in the interface regions, the dielectric charge trapping structures establishing a three-dimensional memory The cell array, the three-dimensional memory cell array is accessible through the semiconductor strips and the word lines; the plurality of source-side bias structures and the plurality of drain-side bias structures are disposed adjacent to the stacks a plurality of semiconductors; at least one select line disposed on the stacks and orthogonally arranged with the stacks, the select lines being disposed between the word lines or the word lines and the first end or the second One of the ends And a plurality of gate dielectric structures are disposed between the select lines and the plurality of semiconductor strips in the stacks such that a plurality of switch transistors are established on the semiconductor or drain side of the source side bias structures Any one of the semiconductors of the bias structure and the plurality of semiconductor strips; wherein the gate dielectric structures are different from the dielectric charge trapping structures. The memory device of claim 11, wherein the at least one select line comprises a first select line at the first end and a second select line at the second end, and the gates are dielectrically The structure is disposed between the first selection line, the second selection line, and the semiconductor strips located in the stacks, such that a plurality of switching transistors are established in the semiconductors of the source side bias structures Between the semiconductor strips or the semiconductors of the drain side bias structures and the semiconductor strips. The memory device of claim 11, wherein the semiconductors of the drain side bias structures comprise a plurality of bit lines, and the semiconductors of the source side bias structures comprise a plurality of common source lines. The memory device of claim 11, wherein the semiconductors of the drain side bias structures comprise a plurality of bit lines, and the semiconductors of the source side bias structures comprise a plurality of bit lines. The memory device of claim 11, wherein the dielectric charge trapping structures comprise a tunneling layer, a charge trapping layer and a barrier layer, and the gate dielectric structures comprise the tunneling layer And some or all of the charge trapping layer, but not including the barrier layer. The memory device of claim 11, wherein the dielectric charge trapping structures comprise a tunneling layer, a charge trapping layer and a barrier layer, and the gate dielectric structures comprise the tunneling layer And a layer containing the charge trapping layer completely or partially oxidized, but does not include the barrier layer. The memory device of claim 11, wherein the dielectric charge trapping structures comprise a tunneling layer, a charge trapping layer and a barrier layer, and the gate dielectric structures comprise the tunneling layer But does not include the charge trapping layer and the barrier layer. The memory device of claim 11, wherein the dielectric charge trapping structure comprises a tunneling layer, a charge trapping layer and a barrier layer, and the gate dielectric structures are included in the tunneling An oxide layer obtained by oxidation in the presence of a layer, but not including the charge trapping layer and the barrier layer, such that the thickness d2 of the oxide layer beyond the initial level of the tunnel of the switching transistor and the oxide layer being lower than the initial layer The thickness d1 of the thickness is greater than the thickness d2/d1 is greater than 55/45. The memory device of claim 11, wherein the dielectric charge trapping structures comprise a tunneling layer, a charge trapping layer and a barrier layer, and the gate dielectric structures comprise germanium oxide Or a layer of bismuth oxynitride. The memory device of claim 11, wherein the dielectric charge trapping structures have a first thickness between the corresponding semiconductor strips and the word lines, and the gates are The electrical structure has a second thickness between the corresponding semiconductor strips and the select line, the second thickness being less than the first thickness. The memory device of claim 11, wherein the materials of the gate dielectric structures surround a plurality of semiconductor strips located in the stacks; and wherein the at least one selected line is filled in the Between the semiconductor strips in the stack. A method of fabricating a memory array, comprising: forming a plurality of semiconductor strips each having a first end and a second end; forming a plurality of layers of a plurality of dielectric materials on the plurality of semiconductor strips Forming a reticle on the plurality of layers of the dielectric material, the reticle exposing the plurality of stacked layers in a switch transistor region of the corresponding semiconductor strip; developing the exposed portions of the switch transistor regions Multi-layer stacking to form a plurality of gate dielectric structures different from the dielectric charge trapping structure; removing the mask; forming a plurality of characters on the semiconductor strips and orthogonally arranged with the semiconductor strips a line having a conformal surface with the plurality of stacked layers on the plurality of semiconductor strips; and forming one of the semiconductor strips and arranged orthogonally to the plurality of semiconductor strips A select line having a surface conformal to the gate dielectric structures on the plurality of semiconductor strips. The method of claim 22, wherein the multilayer stack comprises a tunneling layer, a charge trapping layer and a barrier layer, and the developing comprises removing the barrier layer. The method of claim 22, wherein the multilayer stack comprises a tunneling layer, a charge trapping layer and a barrier layer, and the developing comprises removing the barrier layer and the portion of the charge trapping layer. The method of claim 22, wherein the multilayer stack comprises a tunneling layer, a charge trapping layer and a barrier layer, and the developing comprises removing the barrier layer and oxidizing the charge trapping layer. The method of claim 22, wherein the multilayer stack comprises a tunneling layer, a charge trapping layer and a barrier layer, and the developing comprises removing the barrier layer and the charge trapping layer. The method of claim 22, wherein the multilayer stack comprises a tunneling layer, a charge trapping layer and a barrier layer, and the developing comprises removing the barrier layer and the charge trapping layer and oxidizing the layer Tunneling. The method of claim 22, wherein the developing comprises removing the plurality of stacked layers and forming a gate dielectric layer. The method of claim 22, wherein the developing comprises removing the plurality of stacked layers and forming a gate dielectric layer by oxidizing the semiconductor strips of the semiconductor strips. The method of claim 22, wherein the forming the plurality of semiconductor strips comprises: forming a stack consisting of a layer of interleaved semiconductor material and a layer of insulating material; and etching the stack to form A plurality of stacks of semiconductor strips, the stacks being ridged and comprising at least two semiconductor strips separated by different layers of the plurality of layers by an insulating material. The method of claim 30, wherein the developing comprises removing an insulating material between the semiconductor strips in the stacks of the switching transistor regions, and forming in the semiconductor strips. Surrounding a gate dielectric material of the plurality of semiconductor strips; and wherein the selected lines are filled between the plurality of semiconductor strips in the stack. A memory device comprising: a memory cell array comprising a plurality of dielectric charge trapping structures; and a plurality of switching transistors located in the memory cell array, the switching transistors comprising a plurality of gate dielectric structures, The gate dielectric structures include a plurality of modified dielectric charge trapping structures. A memory device includes: a three-dimensional memory cell array comprising a plurality of double gate thin film transistors, the double gate thin film transistors having a dielectric charge trapping structure, the three-dimensional memory cell array comprising an array of memory cells And a plurality of switching transistors are coupled to the plurality of switching transistors, and the switching transistors comprise a plurality of surrounding gate transistors.