TW201310189A - Dynamic bias circuit and associated method - Google Patents

Abstract

Dynamic bias circuit and associated method providing a bias according to a first clock. The dynamic bias circuit includes a first reference generator, a second reference generator, a comparator and a tuning circuit. The first reference circuit provides a first reference signal according to a feedback signal, and the second reference circuit provides a second reference signal. The comparator compares the first reference signal and the second reference signal, and the tuning circuit provides the feedback signal and the bias according to comparison result; wherein the first reference signal is in association with the first clock.

Description

Dynamic bias circuit and related methods

The present invention relates to a dynamic bias circuit and related method, and more particularly to a method for isolating clock noise in a bias voltage by digital adjustment when biasing according to a clock is provided to eliminate low noise. A dynamic bias circuit and associated method that pass filters and maintain an appropriate minimum bias voltage at low frequency clocks.

A variety of electronic circuits, especially those based on clock operation, have become the most important hardware foundation of the modern information society. For various clock operation circuits, the frequency of the clock is related to the power required; when the frequency of the pulse is high, the clock operation circuit requires a large bias (such as a large bias current) to provide More power. Conversely, when the frequency of the current pulse is low, the power required by the clock operation circuit is also low, and the lower bias voltage can satisfy its power requirement.

Therefore, in order to improve the power utilization performance of the clock operation circuit, a dynamic bias circuit emerges as the times require. The dynamic bias circuit adjusts the bias voltage (such as bias current) of the clock operation circuit according to the clock. For example, when the frequency is high, the dynamic bias circuit can provide a higher bias voltage to transmit higher power to the clock operation circuit; otherwise, when the pulse operation circuit operates at a lower frequency, the dynamic bias voltage The circuit adaptively reduces the bias voltage.

Referring to Figure 1, a dynamic bias circuit 10 of the prior art is illustrated, as disclosed by Andersen et al., July 2005, IEEE Journal of solid-state circuits, vol. 40, no. The paper "A Cost-Efficient High-Speed 12-bit Pipeline ADC in 0.18-μm Digital CMOS". The conventional dynamic bias circuit 10 is provided with an amplifier 12, two transistors PL and PR (p-channel MOS transistors), a load 14 and a low-pass filter LPF to adjust the position according to a clock CK. The bias current Io1 is provided. The dynamic bias circuit 10 operates between the operating voltages Vcc and G.

In the dynamic bias circuit 10, the positive and negative input terminals of the amplifier 12 are respectively coupled to the node nb and a reference voltage VBG, and the output terminal is coupled to the gate of the transistor PL at the node na, so that the voltage of the node nb is virtual grounded. Equal to voltage VBG. The voltage VBG can be a constant constant voltage, for example, a voltage generated by a bandgap circuit, such that the voltage value of the voltage VBG is resistant to temperature, operating voltage, and drift/variation of the process.

The capacitor 14 is provided with a capacitor Cp and two switches SpB and Sp; the switches SpB and Sp are controlled by the clocks CK and CKB, respectively, and the clock CKB is the inversion of the clock CK. That is, when the switch SpB turns on the node nb to the node nc, the switch Sp does not conduct between the node nc and the operating voltage G; at this time, the current of the node nb charges the capacitor Cp. When the current pulse CKB causes the switch SpB to be non-conducting, the switch Sp turns on the node nc to the operating voltage G, and discharges the capacitor Cp to the operating voltage G. Therefore, in one period Ts of the clock CK, the charge change amount of the capacitor Cp is Cp*VBG, and the average current is Cp*VBG/Ts; in other words, the load 14 can be equivalent to a resistor Req whose resistance is VBG/ Ix=Ts/Cp=1/(Cp*Fck), where Fck is the frequency of the clock CK and its value is 1/Ts.

As can be seen from the above discussion, the equivalent resistance Req of the load 14 changes at the frequency Fck of the pulse CK. When the pulse CK is faster (the frequency Fck is higher), the resistance of the resistor Req will be lower, and the equivalent current Ix flowing through the load 14 is higher (because the voltage of the node nb is fixed); via the transistors PL and PR In the current mirror configuration, the bias current Io1 provided by the transistor PR is also increased. In contrast, when the pulse CK is slow, the resistance of the resistor Req is high, and the current Ix is low, so the current Io1 provided by the dynamic bias circuit 10 is also reduced. As such, the conventional dynamic bias circuit 10 can implement the function of dynamic bias.

However, the conventional dynamic bias circuit 10 also has disadvantages. First, since the switches SpB and Sp periodically switch between on/off during the pulse CK, a periodic transient change is caused in the load 14, which in turn causes clock noise. At this time, the pulse noise is coupled to the node na via the transistor PL, and further coupled to the gate of the transistor PR, so that the bias current Io1 is also affected by the clock noise. Therefore, the conventional dynamic bias circuit 10 must provide a low-pass filter LPF between the node na and the gate of the transistor PR to suppress the clock noise of the node na and reduce the influence of the clock noise on the transistor PR. .

However, the setting of the low pass filter LPF derives other problems. Since the low-pass filter LPF is an analog circuit (such as a resistor-capacitor analog circuit), it will occupy an extra layout area; if the frequency variation range of the clock CK has a lower lower limit frequency, in order to filter out low-frequency clock noise The layout area of the low-pass filter LPF is even larger, which is difficult to achieve.

Furthermore, when the frequency of the pulse CK is lower than the lower limit frequency, the equivalent resistance of the load 14 is too high and the current Ix is too low, and the bias current Io1 is too low to provide an appropriate bias voltage. For the timing operation circuit (not shown in Figure 1) that depends on the current Io1, if the bias current Io1 is too low, the operation of the transistor cannot be maintained in the normal operating region (such as the saturation region); thus, The timing operation circuit will not work properly.

To overcome the shortcomings of the prior art, one object of the present invention is to provide a dynamic bias circuit that provides a bias voltage (e.g., bias current) in accordance with a first clock. The dynamic bias circuit includes a first reference generator, a comparator and an adjustment circuit. The first reference generator provides a first reference signal according to a feedback signal. The comparator compares the first reference signal with a second reference signal and provides a comparison result. The adjustment circuit provides a feedback signal and generates a bias voltage based on the comparison result. The first reference signal is dynamically associated with the first clock.

A further object of the present invention is to provide a method for dynamically providing a bias voltage (such as a bias current) according to a first clock, comprising: providing a first reference signal according to a feedback signal and the first clock; Comparing the first reference signal with a second reference signal and providing a comparison result; and providing a feedback signal and generating a bias according to the comparison result.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

Please refer to FIG. 2, which illustrates a dynamic bias circuit 20 according to an embodiment of the present invention; the dynamic bias circuit 20 can provide a clock operation circuit (not shown) according to a first clock. A bias voltage (such as bias current Io), when the pulse operation circuit operates based on the trigger of the first clock. The dynamic bias circuit 20 is provided with a first reference generator 22a, a second reference generator 22b, a comparator 24 and an adjustment circuit 26; wherein the comparator 24 is coupled to the first reference generator 22a, the second Between the reference generator 22b and the adjustment circuit 26, the first reference generator 22a is also coupled to the adjustment circuit 26.

In the dynamic bias circuit 20, the first reference generator 22a is a dynamic reference generator, and provides a signal Sr1 as a first reference signal according to a signal Sf (ie, a feedback signal). The second reference generator 22b is another reference generator that provides a signal Sr2 as a second reference signal. The signal Sr1 may be a reference signal associated with the first clock, and the signal value changes with the first clock; for example, the signal Sr1 may be a voltage signal that changes the voltage value with the first clock, and/or A current signal that changes the current value with the first clock. The signal Sr2 can be a constant value (fixed value) signal, for example, a voltage signal of a constant voltage value, and/or a current signal of a constant current value.

The comparator 24 receives the signals Sr1 and Sr2, compares the signal sizes of the two, and provides a signal CMP to the adjustment circuit 26 to reflect the comparison result. For example, the comparator 24 can sample the trigger of a comparison clock (not shown), compare the result of the latch signal Sr1 and the signal Sr2, and represent the comparison result by the digital signal CMP. Therefore, the signal CMP Timing is associated with the period of the comparison clock. Wherein, the comparison clock system is associated with the first clock; for example, the frequency of the first clock may be K times the comparison clock, and K may be an integer or rational number greater than 1, equal to 1 or less than 1. That is to say, the frequency of the comparison clock can be increased as the frequency of the first clock increases, and decreases as the frequency of the first clock decreases.

The adjustment circuit 26 can be an adjustment circuit based on the digital circuit, which can provide the feedback signal Sf and generate the bias current Io according to the comparison result in the signal CMP. The feedback signal Sf can be a digital signal carrying a digit value. In an embodiment, the adjustment circuit 26 can generate the signal Sf according to the comparison result in the signal CMP, so that the timing of the signal Sf is also associated with the comparison clock.

In an embodiment, when the first reference generator 22a generates the signal Sr1 according to the signal Sf, the change rate of the signal Sr1 is adjusted according to the value of the signal Sf (ie, the signal value change amount per unit time); the adjustment circuit 26 is based on The value of the signal Sf provides the current Io. For example, when the value of the signal Sf enhances the rate of change of the signal Sr1, the adjustment circuit 26 also enhances the current Io accordingly; conversely, when the value of the signal Sf decreases the rate of change of the signal Sr1, the adjustment circuit 26 also reduces the current accordingly. Io.

In a certain period of the comparison clock, if the signal CMP reflects that the signal Sr1 is greater than the signal Sr2, the value of the signal Sf causes the first reference generator 22a to change the signal value of the signal Sr1 at a lower rate of change during the period. To suppress the signal Sr1. On the other hand, if the signal CMP reflects the signal Sr1 is smaller than the signal Sr2, the signal Sf causes the first reference generator 22a to change the signal value of the signal Sr1 at a higher rate of change to enhance the signal Sr1. After the feedback of the signal Sf, the signal value of the signal Sr1 is gradually locked to the signal value of the signal Sr2.

If the first clock is slower, the period of the comparison clock is longer; therefore, even in the periods of the comparison clock, even if the value of the signal Sf causes the rate of change of the signal Sr1 to be low, the signal Sr1 can still accumulate enough changes. The amount is locked to the fixed value signal Sr2, so the current Io will also be lower to respond to the first clock of the low frequency. If the frequency of the first clock is higher, the period of the comparison clock will be shortened. The value of the signal Sf should increase the rate of change of the signal Sr1 to quickly accumulate enough change amount to lock the signal Sr2, so the current Io will also improve. In this way, the function of dynamic bias can be realized.

Please refer to FIG. 3 and FIG. 4; FIG. 3 is a schematic diagram of a dynamic bias circuit 30 according to an embodiment of the invention, and FIG. 4 is a diagram showing the waveform timing of the associated signal in FIG. The dynamic bias circuit 30 provides a bias voltage for the clock operation circuit 56 according to a clock CK (first clock), for example, a bias current Io; the clock operation circuit 56 is based on the trigger of the clock CK. Operation. For example, the clock operation circuit 56 can include an n-channel MOS transistor N1; the transistor N1 must be able to obtain sufficient drain bias current to maintain normal operation (for example, operation of the saturation of the transistor). Area). In one embodiment, the clock operation circuit 56 can be a pipeline analog to digital converter.

The dynamic bias circuit 30 operates between the operating voltages Vcc and G. For example, the nodes n0 and n4 are respectively coupled to the operating voltages Vcc and G. For example, the operating voltage G can be a ground terminal voltage, and the operating voltage Vcc is a positive voltage higher than the ground terminal voltage.

The dynamic bias circuit 30 includes a first reference generator 32a, a second reference generator 32b, a comparator 34 and an adjustment circuit 36. The first reference generator 32a provides a voltage VC as a first reference signal according to a signal Df (ie, a feedback signal). The second reference generator 32b then provides a voltage VR as a second reference signal.

Comparator 34 can be a voltage mode comparator to compare the two voltage signals. The comparator 34 has a first comparison input terminal, a second comparison input terminal and a comparison output terminal; the first comparison input terminal and the second comparison input terminal (indicated by "+" and "-" respectively in FIG. The first reference generator 32a and the second reference generator 32b are coupled to the nodes n3 and n2 respectively, and the voltages VR and VC are compared under the trigger of a clock CKcmp (comparison clock) and the comparison result is sampled to be compared by the node n6. The comparison output provides a signal CMP to reflect the comparison. For example, when the current pulse CKcmp is converted from the low level to the high level, the rising edge can trigger the comparator 34 to sample and latch the comparison result of the voltage VC and the VR: if the voltage VC is greater than the voltage VR, the comparator 34 is in the signal CMP. The logic is maintained (latched) until the next rising edge; conversely, when the rising edge is triggered, if the voltage VC is less than the voltage VR, the comparator 34 maintains a logic 0 in the signal CMP until the next rising edge. Wherein, the clock CKcmp is associated with the clock CK; for example, the frequency of the clock CK may be K times the clock CKcmp, and K may be an integer or rational number greater than 1, equal to 1 or less than 1. That is to say, the frequency of the clock CKcmp can rise as the frequency of the pulse CK rises, and decreases as the frequency of the first clock decreases.

The adjusting circuit 36 is coupled to the comparison output of the comparator 34 at the node n6, and provides a signal Df and another signal Do (ie, an output signal) according to the signal CMP, and generates a bias current Io according to the signal Do. The signals Df and Do can be digital signals carrying multi-bit values.

The first reference generator 32a includes two current sources 48a, 50a and a load 54. The current source 48a is a variable current source (first variable current source) coupled between the nodes n0 and n3, and is provided with a controlled terminal 58a (first controlled terminal) and a current terminal (first current) The former is coupled to the signal Df, and the latter is coupled to the first comparison input of the comparator 34 at the node n3. The current source 48a supplies the current Itune1 to the node n3 according to the data value in the signal Df; when the value of the signal Df changes, the current of the current Itune1 also changes.

For example, the data in the signal Df may be an N-bit value, and the value may be from 0 to (2^N-1); correspondingly, the current provided by the current source 48a, Itune1 may also be from 0 to (2). ^N-1) current per unit. In one embodiment, the current source 48a may include (2^N-1) current source units that can provide the same current, and each current source can be selectively turned on to the node n3 according to the signal Df; the larger the value of the signal Df, The more current source cells that are turned on to node n3, the more the current Itune1 increases. For example, each current source unit can provide a current of Iu1/(2^N) (where Iu1 is a constant), and the current Itune1 can be: Itune1=Df*Iu1/(2^N).

The other current source 50a is a constant current source (first constant current source), and is also coupled between the nodes n0 and n3. The node n3 is coupled to the first comparison input of the comparator 34 and provides a fixed current value. Current Ifx1. The currents Itune1 and Ifx1 merge into the current Ix1 at node n3 and inject into the load 54.

The load 54 (the first load) is coupled to the first comparison input of the comparator 34 at the node n3, and coupled to the operating voltage G at the node n4. The load 54 establishes a voltage VC (first voltage) at the node n3 in accordance with the current Ix1 of the clock CK and the first comparison input (node n3). The load 54 includes a capacitor C (first capacitor) and a switch S. The capacitor C is coupled between the nodes n3 and n4. The switch S is also coupled between the nodes n3 and n4 to selectively turn on the node n3 to the operating voltage G according to a clock CKc (switching clock). For example, when the current pulse CKc is low, the switch S stops conducting between the nodes n3 and n4, so that the current Ix1 can charge the capacitor C; relatively, when the current pulse CKc is high, the switch S turns the node n3 to the node. The operating voltage G of n4 bypasses the current Ix1 to the capacitor C, and the capacitor C can also be reset to the voltage of the node n4. Among them, the clock CKc is associated with the clock CKcmp, so it is also associated with the clock CK. The frequency of the clock CKcmp and the clock CKc may be the same, but the phase between them is 90 degrees out of phase.

The second reference generator 32b includes an amplifier 52 (such as a differential amplifier), a transistor P1 and a resistor Rset. The amplifier 52 has a first amplifier input terminal, a second amplifier input terminal (indicated by "+" and "-" in FIG. 3) and an amplifier output terminal; the second amplifier input terminal is coupled to a voltage VBG (ie, A reference voltage), the first amplifier input is coupled to node n2. In one embodiment, voltage VBG is a bandgap reference voltage provided by a bandgap circuit (not shown).

The transistor P1 can be a p-channel MOS transistor, which can be equivalent to a controlled current source. The gate of the transistor P1 at the node n1 can be regarded as a reference control terminal, and is coupled to the amplifier output of the amplifier 52. The source of the transistor P1 is coupled to the operating voltage Vcc at the node n0, and the drain is used as a reference current terminal, and coupled to the first amplifier input terminal at the node n2.

The resistor Rset can be regarded as a reference load, coupled between the nodes n2 and n4, and provides a voltage VR according to the current Ix2 provided by the transistor P1 at the node n2. In one embodiment, the resistor Rset is an external precision resistor. That is, in addition to the resistor Rset, the dynamic bias circuit 30 and the clock operation circuit 56 can be integrated in the same wafer, and the resistor Rset is coupled to the node n2 in the wafer via the external pin of the chip (and N4).

In the embodiment of Figure 3, the adjustment circuit 36 includes a decision circuit 38 and two current sources 48b and 50b. The determining circuit 38 is coupled to the comparison output of the comparator 34 at the node n6 to provide the signal Df and the signal Do according to the comparison result in the signal CMP. The current source 48b can be regarded as a second variable current source coupled between the nodes n0 and n7, and has a controlled end 58b (second controlled end) and a current end (second current end) coupled to the former. Signal Do, the latter is coupled to node n7. The current source 48b supplies the current Itune2 to the node n7 according to the signal Do; when the value of the signal Do changes, the current of the current Itune2 also changes. For example, the data in the signal Do may be an N-bit value, and the value may be from 0 to (2^N-1); correspondingly, the current Itune2 provided by the current source 48b may also be from 0 to (2) ^N-1) current per unit. For example, similar to the current source 48a, the current Itune2 of the current source 48b may also be: Itune2=Do*Iu2/(2^N), where Iu2 is a constant.

The other current source 50b can be used as a second constant current source, and is also coupled between the nodes n0 and n7, and provides a current Ifx2 at the node n7. The currents Itune2 and Ifx2 combine to sink the current Io at node n7, that is, the bias current to be supplied to the clock operation circuit 56.

In the embodiment of FIG. 3, the determining circuit 38 is provided with a counter 40, an overflow detector 42 and a lock detector 46, which may be digital logic circuits. The counter 40 is coupled to the comparator 34 at the node n6 to selectively increase and decrease the count value Dv of one digit according to the comparison result in the signal CMP. For example, the count value Dv may be a value of one N-bit, so the value may be 0 to (2^N-1). If the signal CMP is logic 0 (ie, the voltage VR is less than VC), the counter value Dv of the counter 40 is increased by 1; in contrast, if the signal CMP is logic 1 (voltage VR is greater than VC), the count value Dv is decreased by one. The adjustment circuit 36 provides the signals Df, Do and the current Io based on the value Dv. For example, when the count value Dv increases, the adjustment circuit 36 also increases the value of the signal Df; conversely, when the count value Dv decreases, the adjustment circuit 36 also reduces the value of the signal Df.

The lock detector 46 is coupled to the counter 40 and the comparator 34 at nodes n5 and n6, respectively, and is coupled to the overflow detector 42 and the controlled terminal 58b of the current source 48b. The lock detector 46 detects whether the count value Dv has approached a steady state value according to the comparison result in the signal CMP, and accordingly provides the signal Do. For example, when the magnitude of the count value Dv changes with time is still large, the lock detector 46 does not change the value of the signal Do. On the contrary, when the increase or decrease of the count value Dv on a steady state value is less than a tolerance range for a predetermined period of time, it can be determined that the count value Dv has approached the steady state value, so the lock detector 46 will be based on The steady state value sets the value of the signal Do, and the adjustment circuit 36 controls the current source 48b according to the signal Do to generate the bias current Io.

The overflow detector 42 is coupled to the counter 40 and the lock detector 46, and is coupled to the controlled terminal 58a of the current source 48a to provide a signal Df to the current source 48a. The overflow detector 42 detects whether the count value Dv will exceed a predetermined range; if so, the count value Dv remains unchanged. For example, for the N-bit count value Dv, the aforementioned preset range may be defined by 0 and (2^N-1). If the N-bit count value Dv is already equal to 0, but the signal CMP still has to decrease the count value Dv, the count value Dv will be cycled to (2^N-1) due to underflow; to prevent this A situation occurs when the count value Dv is to continue to decrease by 0, the overflow detector 42 maintains the count value Dv at zero. When the count value Dv remains unchanged, the value of the signal Df remains unchanged. Corresponding to the count value Dv of the value 0, the signal Df will make the current value of the current Itune1 of the current source 48a zero, and the signal Do will make the current Itune2 of the current source 48b zero; however, since the current sources 50a and 50b will continue to provide The currents Ifx1 and Ifx2, the current Io will continue to maintain a minimum value, that is, current Ifx2.

In contrast, when the signal CMP is to continuously increase the count value Dv from (2^N-1), the overflow detector 42 maintains the count value Dv at (2^N-1), preventing the count value Dv from being incremented. After 1, it loops back to 0.

The principle of operation of the dynamic bias circuit 30 can be illustrated in FIG. In the example of Fig. 4, the frequency of the clocks CKc and CKcmp is 1/2 of the clock CK, that is, if the period of the clock CK is Ts, the period of the clocks CKc and CKcmp is 2*Ts. The phase of the clock CKcmp can be ahead of the phase of the clock CKc, which differs by 90 degrees, that is, there is a difference in Ts/2 on the time axis.

Since the voltage VR is established based on the voltage VBG with a fixed voltage value, the voltage VR is also a constant voltage and does not change with time, and is shown as a horizontal line in FIG. Between the time points t1m and t1p, the low level of the clock CKc causes the switch S to be non-conducting, and the current Ix1 charges the capacitor C, so that the voltage VC starts to rise from the operating voltage G of the node n4. At time t1, the rising edge of the clock CKcmp triggers the comparator 34; since the comparison result sampled by the comparator 34 is that the voltage VC is less than the voltage VR, the signal CMP will maintain a logic 0 at the time point t1 to t2, and the counter 40 will The count value Dv is increased by 1, which in turn increases the value of the signal Df, causing the current Itune1 to increase and the current Ix1 to increase. However, between the time points t1p and t2m, the high level of the signal CKc turns on the switch S, the capacitor Cf discharges, and the voltage VC is reset to the voltage of the node n4. Between the time points t2m and t2p, the low level of the signal CKc again causes the switch S to be non-conducting, and the current Ix1 will again charge the capacitor C to raise the voltage VC. Since the current Ix1 has increased after the time point t1, the rate of change of the voltage VC (the speed at which the voltage rises with time) increases between the time points t2m and t2p, causing the voltage VC to increase more rapidly.

At time t2, the rising edge of the clock CKcmp triggers the comparator 34 again, assuming that the signal CMP still reflects that the voltage VC is less than the voltage VR. Therefore, the count value Dv is incremented again after the time point t2, and the current Itune1 supplied from the current source 48a is further increased by the value of the signal Df, and the current Ix1 is also increased.

Through the reset between the time points t2p and t3m, the voltage VC rises again due to the charging of the current Ix1 between the time points t3m and t3p, and the rate of change of the voltage VC is further enhanced by the increase of the current Ix1, so that the voltage value of the voltage VC is increased. Accumulate more quickly. Assume that the enhanced current Ix1 causes the voltage VC to exceed the voltage VR at time t3 (as shown in Fig. 4). When the rising edge of the pulse CKcmp triggers the comparator 34 again at the time point t3, the signal CMP of the comparator 34 is at the time point. Change to logic 1 after t3. Incidentally, after the time point t3, the count value Dv is decreased by 1, the value of the signal Df is also decreased, and the currents Itune1 and Ix1 are also reduced accordingly.

Waiting until the time point t4m to t4p, since the current Ix1 is reduced, the voltage VC is again smaller than the voltage VR at the time point t4; the signal Df causes the current Ix1 to increase again via the operation of the comparator 34 and the counter 40. Therefore, between the time point t5m to t5p and the time point t7m to t7p, the voltage VC repeats the waveform between the points t3m and t3p. Similarly, between time t6m and t6p, the voltage VC will repeat the waveform between the points t4m and t4p, and so on. In other words, after the time point t3m, the voltage VC is alternately greater than and less than the voltage VR at each rising edge of the clock CKcmp, the signal CMP is alternated between logic 1 and logic 0, and the count value Dv is alternately decreased by 1 and incremented by 1. . This means that the count value Dv has reached a steady state value and a lock is achieved, and the lock detector 46 can set the value of the signal Do according to the steady state value, thereby causing the current source 48b to generate a corresponding bias current Io. In one embodiment, the lock detector 46 can calculate whether the consecutive number of consecutive times between the logic 0 and the logic 1 of the signal CMP has been greater than a predetermined number of times, and if so, it is determined that the steady state lock has been achieved, and according to the count value Dv The steady state value sets the value of the signal Do.

If the clock CK is faster, the period Ts will be shorter, and the larger value Dv and the signal Df are required to enable the voltage VC to rapidly accumulate in the short period enough to exceed the voltage VR with a higher current Ix1; After the state is locked, the high speed clock CK will correspond to the signal Do having a higher value, and the current Io is also larger to meet the larger bias demand of the clock operation circuit 56. In contrast, if the frequency of the clock CK is low and the period Ts is long, the steady state lock can be achieved by the lower value of the count value Dv and the signal Df, so that the value of the signal Do is also lower, and the current Io is also smaller.

It can be seen from the steady-state locking condition that, during steady-state locking, the voltage VC obtained by charging the capacitor C for Ts/2 cycles after the current Ix1 is charged will approach the voltage VR; at this time, the voltage VC=(Ix1/C)*Ts/ 2. The fixed voltage VR=Ix2*Rset (please refer to Figure 3). Let the voltage VC=VR, get C*Rset=(Ix1/Ix2)*Ts/2=(Kfix+Df*KR/(2^N))*Ts/2; where Ix1=Itune1+Ifx1,Itune1= Df*Iu1/(2^N), Kfix=(Ifx1/Ix2), KR=(Iu1/Ix2). In one embodiment, the current sources 48a and 48b are mutually matched and mutually replicated, and the current sources 50a and 50b are also mutually replicated; when the lock is reached, since the value of the signal Do can be equal to the signal Df, the current Itune1=Itune2 And the current Ifx1 = Ifx2. Therefore, when the lock is completed, the frequency Fck of the clock CK can be calculated as:

Fck=1/Ts=(Kfix+Do*KR/(2^N))/(2*C*Rset) -- (Formula 1).

It can be seen from (Formula 1) that the higher the frequency of the clock CK is, the larger the value of the signal Do is, and the bias current Io is correspondingly increased to realize the function of the clock dynamic bias.

The clock CK of the clock operation circuit 56 varies in a frequency variation range, that is, the frequency Fck of the clock CK varies between the upper limit frequency and the lower limit frequency of the frequency variation range. In order to dynamically adjust the bias current Io in response to the fluctuation of the clock CK, the upper and lower limits of the signal Do should correspond to the upper limit frequency and the lower limit frequency of the frequency variation range, respectively. Therefore, by substituting the upper and lower numerical limits of the signal Do into (Formula 1), the frequency variation range that the dynamic bias circuit 30 can support can be known.

In (Formula 1), assume N=5 (ie, the signals Do and Df are 5 bits of data, the value can be from 0 to 31), Kfix=1/8, KR=1, Rset*C=6.25 Second (nanosecond), when the value of the signal Do is 0, the frequency Fck of the clock CK is 10 MHz (1 MHz is 1 megahertz); when the signal Do is 31, the frequency Fck of the clock CK is 87.5 MHz. In other words, in this example, the range of frequency variation that the dynamic bias circuit 30 can support is from 10 MHz to 87.5 MHz.

In one embodiment, current sources 48a and 48b are replicated with each other and current sources 50a and 50b are also replicated. In another embodiment, the current driving capability of the current source 48a may be M times that of the current source 48b, and the current driving capability of the current source 50a may be M times that of the current source 50b.

The advantages of the dynamic bias circuit 30 of the present invention can be discussed as follows, as compared to the conventional dynamic bias circuit 10 of FIG. Since the dynamic bias circuit of the present invention can suppress the clock noise by the digital adjustment technique, the present invention does not require a low-pass filter, and does not depend on the layout area of the low-pass filter to meet the lower limit. frequency. For example, when the digital judgment circuit 38 operates, the count value Dv and the signal Df may increase or decrease in each period of the clock CKcmp to change its value, but before the lock is reached, the judgment circuit 38 does not change the signal Do. The value. Therefore, the increase or decrease of the signal Df does not affect the stability of the signal Do, and the clock noise is not coupled to the bias current Io via the signal Do. Furthermore, even if the frequency Fck of the clock operation circuit 56 is lower than the lower limit frequency, the bias current Io does not decrease, and an appropriate minimum value, that is, the current Ifx2 can be maintained. The appropriate current minimum ensures that the clock operation circuit 56 still receives sufficient bias current at low frequencies to maintain proper operation.

The present invention also provides a dynamic biasing technique that can be exemplified by the operation of the dynamic biasing circuit 30. When the bias current Io is dynamically provided according to the clock CK, the voltage (voltage signal) VR may be supplied according to the signal Df and the clock CK, and the voltage VR and the VC are compared to provide a signal CMP to reflect the comparison result, and according to the signal CMP The comparison result in the signal provides the signal Df and generates a bias current Io. If the operation of the circuit 38 is judged, it selectively increases and decreases the count value Dv according to the comparison result in the signal CMP, and provides the signals Df and Do according to the count value Dv. The determining circuit 38 also performs a lock detection according to the signal CMP to determine whether the count value Dv approaches a steady state value; if so, the signal Do is provided according to the steady state value, so that the adjusting circuit 36 generates the bias current Io according to the signal Do. . Moreover, the judging circuit 38 also performs an overflow detection to detect whether the count value Dv will exceed a predetermined range; if so, the count value Dv is kept unchanged.

Referring to FIG. 5, illustrated is a dynamic bias circuit 60 for providing a bias voltage, such as bias current Io, in accordance with the frequency of the clock CK, in accordance with yet another embodiment of the present invention. The dynamic bias circuit 60 includes a first reference generator 62a, a second reference generator 62b, a comparator 64 and an adjustment circuit 66.

The first reference generator 62a includes two current sources 70a and 74a, and the current source 70a can be a variable current source having a controlled terminal 72a and a current terminal coupled to the signal Df (return signal) and the node n3; Current source 70a provides current Itune1 at node n3 based on the value of signal Df. The current source 74a can be a constant current source coupled to the node n3 and provide a fixed current value Ifx1 with a fixed current value at the node n3. The currents Itune1 and Ifx1 merge at node n3 into current Ix1 as a first reference signal.

The second reference generator 62b is provided with a current source 76, for example, a constant current source, and a predetermined current Ifx0 having a fixed current value is provided as a second reference signal.

Comparator 64 can be a current mode comparator for comparing current signals Ix1 and Ifx0 and providing a signal CMP to reflect the comparison. The comparator 64 has a first comparison input, a second comparison input and a comparison output. The first two are respectively coupled to the nodes n3 and n2 to receive the currents Ix1 and Ifx0.

The adjustment circuit 66 is provided with a determination circuit 68 and two current sources 70b and 74b. The determining circuit 68 can be a digital circuit coupled to the comparison output of the comparator 64 to provide a signal Df and another signal Do (ie, an output signal) according to the comparison result reflected by the signal CMP. The current source 70b can be a variable current source having a controlled terminal 72b and a current terminal coupled to the signal Do and the node n7 respectively to provide a current Itune2 at the node n7 according to the magnitude of the signal Do. Current source 74b can be a constant current source that provides a constant current, coupled to node n7, to provide a constant current Ifx2. The currents Itune2 and Ifx2 converge at node n7 as current Io.

The operation of the dynamic bias circuit 60 can be analogized to the operation of the dynamic bias circuit 30. For example, when the first reference generator 62a generates the current Ix1, the rate of change of the current Ix1 (the amount of current change per unit time) can be set according to the magnitude of the signal Df, and the clock CK is reflected by the accumulated change amount thereof. Frequency of. The current Ifx0 is a constant current with a fixed current value. The current mode comparator 64 compares the currents of the currents Ix1 and Ifx0, and the determining circuit 68 updates the value of the signal Df according to the comparison result to feedback the change rate of the changing current Ix1, thereby enabling the current Ix1 to be locked to the current Ifx0. Current size. After the lock is reached, the judging circuit 68 sets the value of the signal Do according to the signal Df so that the bias current Io can respond to the frequency of the clock CK.

In summary, compared with the prior art, the clock dynamic bias technology of the present invention can use digital technology to isolate and suppress clock noise, eliminate the need for a low-pass filter, and avoid bias when the clock frequency is too low. Insufficient pressure.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10, 20, 30, 60. . . Dynamic bias circuit

12, 52. . . Amplifier

14, 54. . . load

22a, 32a, 62a. . . First reference generator

22b, 32b, 62b. . . Second reference generator

24, 34, 64. . . Comparators

26, 36, 66. . . Adjustment circuit

38, 68. . . Judging circuit

40. . . counter

42. . . Overflow detector

46. . . Lock detector

48a-48b, 50a-50b, 70a-70b, 74a-74b, 76. . . Battery

56. . . Clock operation circuit

58a-58b, 72a-72b. . . Controlled end

Sr1, Sr2, CMP, Sf, Df, Do. . . Signal

Dv. . . Value

LPF. . . Low pass filter

PL, PR, P1, N1. . . Transistor

Ix, Io1, Io, Ix2, Ix1, Ifx0-Ifx2, Itune1-Itune2. . . Current

Vx, VBG, VR, VC. . . Voltage

Vcc, G. . . Operating Voltage

Cp, C. . . capacitance

Req, Rset. . . resistance

Na-nc, n1-n7. . . node

Sp, SpB, S. . . switch

CK, CKB, CKc, CKcmp. . . Clock

Ts. . . cycle

T1-t7, t1m-t7m, t1p-t7p. . . Time

Figure 1 illustrates a conventional dynamic bias circuit.

Figure 2 illustrates a dynamic bias circuit in accordance with an embodiment of the present invention.

Figure 3 illustrates a dynamic bias circuit in accordance with an embodiment of the present invention.

Figure 4 is a diagram showing the waveform timing of each of the related signals in Figure 3.

Figure 5 illustrates a dynamic bias circuit in accordance with yet another embodiment of the present invention.

20. . . Dynamic bias circuit

22a. . . First reference generator

22b. . . Second reference generator

twenty four. . . Comparators

26. . . Adjustment circuit

Sr1, Sr2, CMP, Sf. . . Signal

Io. . . Current

Claims (20)

A dynamic bias circuit provides a bias voltage according to a first clock; the dynamic bias circuit includes: a first reference generator, providing a first reference signal according to a feedback signal; and a comparator having a first comparison input, a second comparison input, and a comparison output; the first comparison input and the second comparison input are respectively coupled to the first reference generator and a second reference signal, the comparison Comparing the first reference signal and the second reference signal to provide a comparison result by the comparison output, wherein the first reference signal is associated with the first clock; and an adjustment circuit coupled to the comparison output And providing the feedback signal according to the comparison result and generating the bias voltage. The dynamic bias circuit of claim 1, wherein the first reference generator comprises: a first variable current source having a first controlled end and a first current end coupled respectively The feedback signal is coupled to the first comparison input; the first variable current source supplies current to the first current terminal according to the feedback signal. The dynamic bias circuit of claim 2, wherein the first reference generator further comprises: a first constant current source coupled to the first comparison input, and at the first comparison input Provide current. The dynamic bias circuit of claim 2, wherein the first reference generator further comprises: a first load coupled to the first comparison input, according to the first clock and the first Comparing the current at the input terminal and establishing a first voltage at the first comparison input terminal as the first reference signal. The dynamic bias circuit of claim 4, wherein the first load comprises: a first capacitor coupled between the first comparison input and an operating voltage; and a switch coupled Between the first comparison input and the operating voltage, selectively switching the first comparison input to the operating voltage according to a switching clock; wherein the switching clock system is associated with the first clock . The dynamic bias circuit of claim 5, wherein the comparator compares the first reference signal with a second reference signal to provide the comparison result under a trigger of a comparison clock, the comparison The clock system is associated with the first clock, and the comparison clock has the same frequency as the switching clock and the phases are different. The dynamic bias circuit of claim 1, further comprising: a second reference generator coupled to the comparator and providing the second reference signal. The dynamic bias circuit of claim 7, wherein the second reference generator comprises a current source to provide a preset current as the second reference signal. The dynamic bias circuit of claim 8, wherein the second reference generator comprises: an amplifier having a first amplifier input, a second amplifier input, and an amplifier output; The second amplifier input end is coupled to a reference voltage; a controlled current source having a reference control end and a reference current end respectively coupled to the amplifier output end and the first amplifier input end; and a reference load coupled to the The reference current terminal provides the second reference signal according to the current supplied by the controlled current source to the reference current terminal. The dynamic bias circuit of claim 9, wherein the reference load is a resistor and the reference voltage is a bandgap reference voltage. The dynamic bias circuit of claim 1, wherein the adjustment circuit comprises: a counter coupled to the comparator, selectively increasing and decreasing a count value according to the comparison result, and the adjusting circuit The feedback signal and the bias voltage are provided according to the count value. The dynamic bias circuit of claim 11, wherein the adjusting circuit further comprises: a lock detector coupled to the comparator, and detecting whether the count value approaches a steady state according to the comparison result And an output signal is provided according to the value; and the adjusting circuit generates the bias according to the output signal. The dynamic bias circuit of claim 12, wherein the adjustment circuit further comprises: an overflow detector coupled to the counter and the lock detector to detect whether the count value exceeds one The preset range; if so, the count value remains unchanged. The dynamic bias circuit of claim 1, wherein the adjusting circuit comprises: a determining circuit coupled to the comparison output, and providing the feedback signal and an output signal according to the comparison result; a second variable current source having a second controlled end coupled to the second current end, the second controlled end coupled to the output signal; the second variable current source being coupled to the second current end according to the output signal Provide current. The dynamic bias circuit of claim 14, wherein the adjusting circuit further comprises: a second constant current source coupled to the second current terminal and providing current at the second current terminal. The dynamic bias circuit of claim 11, wherein the comparator compares the first reference signal and the second reference signal with a trigger of a comparison clock to provide the comparison result, and The comparison clock system is associated with the first clock. A method for dynamically providing a bias voltage according to a first clock includes: providing a first reference signal according to a feedback signal and the first clock; comparing the first reference signal with a second reference signal, And providing a comparison result; and providing the feedback signal according to the comparison result and generating the bias voltage. The method of claim 17, further comprising: selectively increasing and decreasing a count value according to the comparison result; and providing the feedback signal and the bias voltage according to the count value. The method of claim 18, further comprising: performing a lock detection to detect whether the count value approaches a steady state value; if yes, providing an output signal according to the steady state value, and The output signal produces the bias voltage. The method of claim 18, further comprising: performing an overflow detection to detect whether the count value will exceed a predetermined range; if so, keeping the count value unchanged.