TW201301560A - Layered semiconductor substrate and method of manufacturing same - Google Patents

Abstract

The present invention relates to a layered semiconductor substrate comprising: - a single crystal first layer 1, comprising at least 80% germanium and having a first thickness and a first lattice constant a1, the first lattice constant a1 being Determining by a first doping element and a first doping concentration; and - a single crystal second layer 2 comprising at least 80% germanium and having a second thickness and a second lattice constant a2, the first The two lattice constant a2 is determined by a second doping element and a second doping concentration, the second layer 2 is in direct contact with the first layer 1; and - a single crystal composed of a Group III nitride Three layers 4 such that the second layer 2 is located between the first layer 1 and the third layer 4; wherein the second lattice constant is greater than the first lattice constant, the first layer 1 and the second layer 2 The lattice lattice is lattice matched, and the layered semiconductor substrate has a bowness ranging from -50 micrometers to 50 micrometers. The invention further relates to a method for making the layered semiconductor substrate.

Description

Layered semiconductor substrate and method of manufacturing same

The present invention relates to a germanium-based layered semiconductor that can be used as a substrate for depositing a Group III nitride layer; and a method for fabricating the substrate.

For a gallium nitride (GaN) layer epitaxially deposited on a bismuth (Si) substrate (GaN-on-Si layer structure), due to material mismatch between GaN and Si (111), This causes a number of basic problems. For example, GaN has a coefficient of thermal expansion (TEC) greater than the coefficient of thermal expansion of tantalum. The same is true for the nitrides of the other elements of Group III in the periodic table. This difference in coefficient of thermal expansion results in a large concave curvature of the wafer during cooling from the deposition temperature of the Group III nitride layer to room temperature. The amount of bending increases as the thickness of the Group III nitride layer increases. If the curvature of the wafer is too high, no further processing will be possible. Therefore, it is necessary to maintain a low degree of curvature.

Several solutions have been proposed. The most recent technology is to deposit an intermediate layer that produces compressive stress within a stack of GaN layers, such as an aluminum nitride (AlN) intermediate layer deposited at low temperatures. For example, US 2003/0136333 A1 discloses depositing a number of AlN intermediate layers in a stack of GaN layers on a tantalum substrate. The lattice constant of AlN is smaller than the lattice constant of GaN, and therefore, the GaN layer grown on AlN is in compression during growth. This compression compensates for the tensile stress that occurs during cooling. This achieves a thick and crack-free GaN layer to be grown on the tantalum substrate.

The AlN layer must be deposited at low temperatures, which results in a low growth rate. Therefore, the deposition of the AlN layer is very time consuming. Moreover, GaN layer deposition that occurs at a relatively high temperature of about 1100 ° C has to be interrupted. The temperature reduction and increase between the deposition steps of GaN and AlN takes extra time. Another disadvantage is that the AlN interlayer is in the GaN layer. Additional stress is generated which causes an increase in the defect density in the GaN layer.

Alternatively, one or more layers may be deposited on the backside of the wafer that create a bend that is opposite to the curvature of the wafer front caused by the GaN layer. No. 4,830,984 teaches depositing a metal (e.g., tungsten) telluride layer on the back side of a germanium substrate wafer and annealing it to form a raised structure having a raised front surface. Thereafter, a gallium arsenide (GaAs) layer is deposited on the front side of the germanium substrate wafer. When the structure is cooled to room temperature, tension is applied to the sides of their respective tantalum substrate wafers on both the front GaAs layer and the back metallization layer, resulting in a substantially flat surface of the GaAs layer. . The deposition of the stress backside layer requires several processing steps (deposition of the backside layer (potentially flipping the wafer), etching of the edges and front side to remove deposits, and additional polishing of the front side), which adds cost and complexity to the fabrication. Furthermore, the back side of the non-Si is a source of contamination for all further processing steps.

Accordingly, the problem to be solved by the present invention is to improve a high quality Group III nitride layer having a small degree of curvature, which is produced in a production time less than the time required for the production of known structures.

The problem is solved by a layered semiconductor substrate comprising: - a single crystal first layer 1, comprising at least 80% germanium and having a first thickness and a first lattice constant a1, the first a lattice constant a1 is determined by a first doping element and a first doping concentration; and - a single crystal second layer 2 comprising at least 80% germanium and having a second thickness and a second lattice a constant a2, the second lattice constant a2 being determined by a second doping element and a second doping concentration, the second layer 2 being in direct contact with the first layer 1; and - comprising a Group III nitride a single crystal third layer 4 such that the second layer 2 is located between the first layer 1 and the third layer 4; wherein the second lattice constant a _{2 is} greater than the first lattice constant a ₁ , The lattice of the layer 1 and the second layer 2 are lattice matched, and the layered semiconductor substrate has a curvature ranging from -50 micrometers to 50 micrometers.

In contrast to the prior art, the present invention uses a fully ruthenium-based stacked layer to create stresses to compensate for the stress applied by the Group III nitride layer to be deposited on the substrate.

According to the invention, the composition of the second layer of the substrate is altered relative to the first layer by adding at least one element to at least one layer that creates a lattice mismatch between the first and second layers. The doping element and its concentration are selected such that the lattice constant of the second layer is greater than the lattice constant of the first layer. In the present specification, the term "lattice constant" is understood to mean the lattice constant of the material when the lattice of the material is relaxed. If the material forms a deformed epitaxial layer in the case where the second layer 2 is deposited on the first layer 1, the actual in-plane lattice constant deviates from the lattice constant of the material in the relaxed state. By adjusting the doping element, the concentration of the doping element (hereinafter referred to as "doping concentration"), and the thicknesses of the first and second layers, a specific amount of stress causing the wafer bump to be bent is generated. The amount of stress generated in the substrate is sufficient to counteract the stress generated by the Group III nitride layer deposited on or above the second layer of the substrate.

The invention may also be combined with other techniques to reduce bowing, such as the prior art described above, or the use of a preferential bow on a substrate.

An advantage of the present invention is that the III-nitride nitrogen deposited on the second layer is improved because the need for epitaxial deposition of the stress compensation layer into GaN is eliminated and the growth of the (Al)GaN buffer layer is simplified. The quality of the layer and reduces processing time (ie, reduces cost).

The lack of a stress-creating layer within the Group III nitride layer results in higher quality. This reduces the defect density in the Group III nitride layer. The first or second layer can be easily epitaxially deposited on other layers using standard Si epitaxial processing methods that result in high crystal quality of these layers.

The deposition of the doped Si layer has a higher yield (lower cost) than depositing the stress compensation layer in the (Al)GaN buffer layer. Therefore, the entire process is simplified and the manufacturing cost is reduced.

The invention will be described in detail with reference to the three drawings.

The layered semiconductor substrate according to the invention consists of at least three layers: the single crystal first layer 1 contains at least 80% and preferably at least 90% of ruthenium. (In the present specification, the composition of all layers is expressed in atomic percent.) The first layer 1 has a first thickness and a first lattice constant a ₁ . The first lattice constant a ₁ is determined by the concentration of the first doping element and the first doping element (referred to as "first doping concentration" in the present specification). The lattice orientation is preferably (111).

The second layer 2 of the single crystal also contains at least 80% and preferably at least 90% of ruthenium. It has a second thickness and a second lattice constant a ₂ . The second lattice constant a ₁ is determined by the concentration of the second doping element and the second doping element (referred to as "second doping concentration" in the present specification).

The second layer 2 is in direct contact with the first layer 1. There are no other layers between the first layer 1 and the second layer 2. The second layer 2 is deposited to form a strain-of-variant epitaxial layer having an actual in-plane lattice constant of the second layer 2 that matches the in-plane lattice constant of the first layer 1. Since the second lattice constant a _{2 is} greater than the first lattice constant a ₁ , the second layer 2 has a compressive strain with respect to the first layer 1 . This causes a convex curvature (with respect to the surface of the second layer 2 opposite the first layer 1) before depositing the third layer 4, which is shown in Fig. 2.

The third layer 4 of the single crystal (Fig. 3) is composed of an elemental nitride of Group III of the periodic table (referred to as "Group III nitride" in the present specification). Among these Group III nitrides, aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN) and mixtures thereof are particularly important. Typically, a layered semiconductor substrate includes more than one Group III nitride layer (referred to as "third layer 4"). Preferably, the stacking of the Group III nitride layer begins with an AlN layer to chemically isolate the ruthenium-based substrate, prepare for growth of the two-dimensional layer, and adjust the lattice constant from the lattice constant a _{2 of the} second layer 2 to The lattice constant of the uppermost Group III nitride layer. More preferably, the uppermost Group III nitride is composed of GaN.

In the layered semiconductor substrate according to the invention, the second layer 2 is situated between the first layer 1 and the third layer 4. The third layer 4 can be in direct contact with the second layer 2. However, it is also possible to place one or more intermediate layers 3 between the second layer 2 and the third layer 4.

The layered semiconductor structure according to the present invention preferably has the shape of a circular wafer.

Due to the mutual compensation of the strain of the first, second and third layers, the degree of curvature of the layered semiconductor substrate ranges from -50 microns to 50 microns as defined by ASTM F534 3.1.2 and SEMI MF534. As explained above, the Group III nitride has a coefficient of thermal expansion (TEC) greater than 矽. Therefore, when the Group III nitride layer 4 (Fig. 1) is epitaxially deposited on the tantalum substrate 5 at a high temperature, and thereafter cooled to room temperature, the GaN layer 4 shrinks more than the tantalum substrate 5. This results in a structure having a relatively large concave curvature as shown in Fig. 1. According to the invention, the curvature (produced by the tensile strain of the cooled GaN layer) is compensated by the reverse strain in the ruthenium-based substrate. The structure of the ruthenium-based substrate is shown in Fig. 2. The ruthenium-based substrate comprises a first layer 1 having a first lattice constant and a second layer 2 in direct contact with the first layer 1, and the crystal of the second layer 2 The lattice constant is greater than the first layer 1.

In a first embodiment of the invention, the first and second doping elements are the same and only the first and second doping concentrations are different.

In a first embodiment, if the covalent atomic radius of the doping element is less than 矽, a first doping concentration that is higher than the second doping concentration is selected. Therefore, the first lattice constant a ₁ becomes smaller than the second lattice constant a ₂ . Boron (B) is a typical doping element having a covalent atomic radius smaller than 矽, and is preferably used in this case. The second doping concentration can be as low as zero, but in this case the first doping concentration must be greater than zero.

In a first embodiment, if the doping element has a larger covalent atomic radius, a second doping concentration that is higher than the first doping concentration is selected. Therefore, the first lattice constant a ₁ becomes smaller than the second lattice constant a _{2 again} . Germanium (Ge) or germanium (Sb) is a typical doping element having a covalent atomic radius greater than 矽, and is preferably used in this case. The first doping concentration can be as low as zero, but in this case the second doping concentration must be greater than zero.

In a second embodiment of the invention, the first and second doping elements are different elements. In this case, the covalent atomic radius of the first doping element is less than 矽, and the covalent atomic radius of the second doping element is greater than 矽. Preferably, the first doping element is boron and the second doping element is lanthanum or cerium.

Determining the desired (causing the base layer 1 and the second layer 2 by the amount of strain caused by the intermediate layer 3 (if any) and the third layer 4 (resulting in a concave bend) The stacked bumps are curved). The amount of concave bending is determined in sequence by the thicknesses of the layers 3 and 4, the lattice constant, and the TEC (and thus by its composition). Similarly, the amount of convex curvature of the stack of the first layer 1 and the second layer 2 depends on the thickness and lattice constant of the layers 1 and 2 (and thus on the composition). So choose the first layer 1 And the thickness and lattice constant of the second layer 2 (and hence its composition) such that the desired number of strains is induced in the stack of the first and second layers. A suitable combination of these parameters can be determined by simple experimentation. By suitable selection of these parameters, a layered semiconductor substrate having a very small degree of curvature of from -50 microns to 50 microns, preferably from -10 microns to 10 microns, can be obtained.

As first predicted by Frank and van der Merve (FCFrank and JHvan der Merve, Proc. Roy. Soc., A198, 216 (1949)), at a given lattice constant difference, when the thickness exceeds the critical thickness At this time, the upper limit of the stack of stress layers constructing the first layer 1 and the second layer 2 will be reached. For the Si (111) layer structure, the critical thickness cannot be well established, and the upper limit must be tested experimentally, for example, by measuring the curvature of the layer stack. Below the critical thickness, the change in curvature can be adjusted to the Stoney and Freund equations (see 1987 (1999) Freund et al., Appl. Phys. Lett. 74) to promote the optimization of the final layer structure.

The layered semiconductor substrate according to the present invention can be fabricated by a method comprising the steps of: growing a single crystal comprising at least 80% germanium and a first doping element having a first doping concentration, the single crystal having a first a lattice constant; - cutting at least one wafer from a single crystal; - reducing the thickness of the wafer to a first thickness, the wafer forming a first layer 1; - epitaxial deposition on one surface of the wafer The second layer 2; and - epitaxial deposition of the third layer 4 composed of a Group III nitride.

In the first step of the process, a single crystal containing at least 80% cerium and preferably at least 90% cerium is grown. Preferably, the crystal is grown using the well-known Czochralski method. If the first doping concentration is greater than zero, then to be suitable for the first doping concentration The concentration of the grown single crystal is incorporated into the tantalum melt to dope the first doping element. The grown single crystal has a first lattice constant that is dependent on the first dopant element and the first dopant concentration. With the Chaisky method, it is currently possible to grow single crystals with a diameter of up to 450 mm.

In the second step, at least one wafer is cut from the single crystal. According to the present invention, the slicing method is not particularly limited. For economic reasons, a multi-wire saw (MWS) is preferably used to simultaneously cut a single crystal into a plurality of wafers.

In a third step, the surface layer of the single crystal wafer damaged by the slicing step is removed and the thickness of the wafer is reduced to a value equal to the desired first thickness. This is done by a combination of mechanical, chemical and chemical-mechanical processing steps. The mechanical processing steps are, for example, lapping or grinding. The chemical treatment may be liquid phase etching or vapor phase etching. Polishing is a widely used chemical-mechanical treatment. The resulting wafer constitutes the first layer 1 of the layered semiconductor substrate to be formed.

In a fourth step, a second layer 2 consisting of at least 80% germanium and preferably at least 90% germanium is epitaxially deposited on one surface of the first layer 1. Preferably, chemical vapor deposition (CVD) is used to deposit the second layer of epitaxial. The helium source gas is preferably trichlorodecane. If the second doping concentration is greater than zero, an additional source gas that supplies the doping element must be provided at a concentration suitable to incorporate the second doping concentration into the grown epitaxial layer. In the case where the second doping element is germanium, germanium tetrachloride (GeCl ₄ ) or germane (GeH ₄ ) is preferably used as the additional source gas.

One or more intermediate layers 3 may be epitaxially deposited on the surface of the second layer 2, if desired.

In the final step of the method, a third layer 4 of a Group III nitride such as AlN, GaN or InN or a mixture thereof is epitaxially deposited on the surface of the second layer 2 (or if an additional layer 3 is present, Then on the surface of the additional layer 3). It is also possible (and preferably better) to continue to grow more than one layer of the Group III nitride layer. Preferably, the AlN seed layer is first grown using trimethylaluminum (Al(CH ₃ ) ₃ ) and ammonia (NH ₃ ) as precursors. Thereafter, an AlGaN layer having an increased Ga concentration may be used as a transition layer before the GaN layer is grown. Typically, trimethylgallium (Ga(CH ₃ ) ₃ ) is used as a precursor and deposition is carried out at a growth temperature of 700 ° C and 1200 ° C using a standard MOCVD reactor.

By layering the first and second doping elements, the first and second doping concentrations, and the first and second thicknesses, a layered semiconductor substrate comprising a Group III nitride can be produced, the layered semiconductor substrate The absolute value of the curvature is 50 microns or less or even 10 microns or less.

Other steps may be included in the described fabrication method, such as one or more steps (edge trimming, edge polishing), cleaning steps, inspection steps, and packaging steps for shaping the edges of the wafer.

The layered semiconductor substrate according to the present invention can be used as a substrate for manufacturing photovoltaic elements of electronic devices (for example, power supply elements) or similar light emitting diodes (LEDs).

1‧‧‧ first floor

2‧‧‧ second floor

3‧‧‧Intermediate

4‧‧‧ third floor

5‧‧‧矽 substrate

Figure 1 diagrammatically shows a Group III nitride layer deposited on a germanium substrate (not according to the invention); Figure 2 diagrammatically shows layering according to the invention prior to deposition of a Group III nitride layer An intermediate product of a semiconductor substrate; FIG. 3 diagrammatically illustrates a layered semiconductor substrate including first and second ruthenium-based layers, an intermediate layer, and a Group III nitride layer, in accordance with the present invention .

1‧‧‧ first floor

2‧‧‧ second floor

3‧‧‧Intermediate

4‧‧‧ third floor

Claims (11)

A layered semiconductor substrate, comprising: - a first single crystal layer (1), comprising at least 80% of silicon and having a first thickness and a first lattice constant (A _1), the first lattice constant (a ₁ ) is determined by a first doping element and a first doping concentration; and - a single crystal second layer (2) comprising at least 80% germanium and having a second thickness and a second a lattice constant (a ₂ ), the second lattice constant (a ₂ ) being determined by a second doping element and a second doping concentration, the second layer (2) being associated with the first layer ( 1) direct contact; and - a single crystal third layer (4) composed of a Group III nitride such that the second layer (2) is located in the first layer (1) and the third layer (4) Where the second lattice constant (a ₂ ) is greater than the first lattice constant (a ₁ ), the lattice of the first layer (1) and the second layer (2) are lattice matched, and The layered semiconductor substrate has a bowness ranging from -50 microns to 50 microns. The layered semiconductor substrate of claim 1 wherein the first and second doping elements are the same. The layered semiconductor substrate according to claim 2, wherein the first and second doping elements are elements having a covalent atomic radius smaller than 矽, and the first doping concentration is higher than the second doping concentration. The layered semiconductor substrate of claim 3, wherein the first and second doping elements are boron. The layered semiconductor substrate of claim 3 or 4, wherein the second doping concentration is zero. The layered semiconductor substrate of claim 2, wherein the first and second blends The hetero element is an element having a covalent atomic radius greater than 矽, and the second doping concentration is higher than the first doping concentration. The layered semiconductor substrate of claim 6, wherein the first and second doping elements are tantalum or niobium. The layered semiconductor substrate of claim 6 or 7, wherein the first doping concentration is zero. The layered semiconductor substrate according to claim 1, wherein the first doping element has a covalent atomic radius smaller than 矽, and the second doping element has a covalent atomic radius greater than 矽. The layered semiconductor substrate of claim 9, wherein the first doping element is boron and the second doping element is lanthanum or cerium. A method for manufacturing the layered semiconductor substrate according to claim 1, comprising the steps of: growing a single crystal comprising at least 80% germanium and a first doping element having the first doping concentration, The single crystal has a first lattice constant; - at least one wafer is cut from the single crystal; - the thickness of the wafer is reduced to the first thickness, the wafer constitutes the first layer (1); Depositing the second layer (2) on one surface of the wafer; and - epitaxially depositing the third layer (4) composed of a Group III nitride.