TW201308063A - Energy saving management circuit - Google Patents
Energy saving management circuit Download PDFInfo
- Publication number
- TW201308063A TW201308063A TW100129659A TW100129659A TW201308063A TW 201308063 A TW201308063 A TW 201308063A TW 100129659 A TW100129659 A TW 100129659A TW 100129659 A TW100129659 A TW 100129659A TW 201308063 A TW201308063 A TW 201308063A
- Authority
- TW
- Taiwan
- Prior art keywords
- power
- pin
- switch
- voltage
- output
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Direct Current Feeding And Distribution (AREA)
- Power Sources (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
本發明涉及一種節能管理電路，尤其涉及一種應用於個人電腦（Personal Computer，PC）等電子設備的節能管理電路。The invention relates to an energy-saving management circuit, in particular to an energy-saving management circuit applied to an electronic device such as a personal computer (PC).
隨著各個國家提倡“節能減排”，低碳生活方式已逐漸成為家庭和企業的發展趨勢。例如，歐盟在個人電腦節能方面已經提出較為嚴格的強制性要求，即2010年1月以後銷售的個人電腦在關機狀態下，整機功耗不能大於1W，從2013年1月以後，關機狀態下整機功耗不能大於0.5W。惟，習知的個人電腦在關機狀態下的功耗大都約為0.5-0.8W。顯然，降低電腦等電子設備關機狀態下的整機功耗已迫在眉睫。As countries promote “energy saving and emission reduction”, low-carbon lifestyles have gradually become the development trend of families and enterprises. For example, the EU has put forward stricter mandatory requirements for personal computer energy saving. That is, when the personal computer sold after January 2010 is turned off, the power consumption of the whole machine cannot be greater than 1W. From January 2013, after shutdown, The power consumption of the whole machine cannot be greater than 0.5W. However, the power consumption of the conventional personal computer in the off state is about 0.5-0.8W. Obviously, it is extremely urgent to reduce the power consumption of the whole computer under the shutdown state of electronic devices such as computers.
鑒於以上情況，有必要提供一種可降低電子設備在關機狀態下的整機功耗的節能管理電路。In view of the above, it is necessary to provide an energy-saving management circuit that can reduce the power consumption of the entire device in the off state of the electronic device.
一種節能管理電路，其應用於一電子設備中，該節能管理電路包括電源管理單元、電源控制電路、輸入輸出晶片及南橋，該電源管理單元包括電源管理晶片，該電源管理晶片用以在電子設備執行開機操作後向電源控制電路輸出低電平的電壓控制訊號，以控制電源控制電路為輸入輸出晶片及南橋提供驅動電壓，同時該電源管理晶片通過輸入輸出晶片向南橋發送開機控制訊號或關機控制訊號，南橋接收該開機控制訊號或關機控制訊號後進一步通過輸入輸出晶片控制電子設備的系統電源上電或斷電；該電源管理晶片還用以在電子設備執行關機操作後向電源控制電路輸出高電平的電壓控制訊號，以控制電源控制電路停止為輸入輸出晶片及南橋提供驅動電壓。An energy-saving management circuit is applied to an electronic device, the power-saving management circuit includes a power management unit, a power control circuit, an input and output chip, and a south bridge, the power management unit includes a power management chip, and the power management chip is used in the electronic device. After performing the power-on operation, a low-level voltage control signal is outputted to the power control circuit to control the power control circuit to provide a driving voltage for the input/output chip and the south bridge, and the power management chip sends a power-on control signal or a shutdown control to the south bridge through the input/output chip. After receiving the power-on control signal or the power-off control signal, the south bridge further powers on or off the system power of the electronic device through the input/output chip; the power management chip is further used to output the power to the power control circuit after the electronic device performs the shutdown operation. The level voltage control signal controls the power control circuit to stop supplying the driving voltage to the input and output chips and the south bridge.
本發明的節能管理電路利用電源管理晶片與輸入輸出晶片及南橋配合控制電子設備的系統電源，並在電子設備關機後通過電源管理晶片輸出高電平的電壓控制訊號以控制電源控制電路停止對輸入輸出晶片和南橋供電，以達到降低電子裝置在關機狀態下的整機功耗的目的。The energy-saving management circuit of the invention utilizes a power management chip, an input/output chip and a south bridge to cooperate with a system power supply for controlling the electronic device, and outputs a high-level voltage control signal through the power management chip after the electronic device is turned off to control the power control circuit to stop inputting The output chip and the south bridge are powered to achieve the purpose of reducing the power consumption of the electronic device in the off state.
請參閱圖1，本發明的較佳實施方式提供一種節能管理電路100，其應用於電腦等電子設備中。該節能管理電路100包括電源管理單元10、電源控制電路20、輸入輸出（Input/Output）晶片30及南橋40。Referring to FIG. 1, a preferred embodiment of the present invention provides an energy saving management circuit 100 for use in an electronic device such as a computer. The energy saving management circuit 100 includes a power management unit 10, a power supply control circuit 20, an input/output (output) chip 30, and a south bridge 40.
該電源管理單元10包括電源管理晶片U1、電源開關SW、第一電阻R1、第二電阻R2及電容C1。在本實施例中，該電源管理晶片U1工作時的功耗為0.03W，其包括電源引腳SB、開關機訊號偵測引腳PWR、省電模式設置引腳SEL、電壓控制訊號輸出引腳OFF、開關機控制訊號輸出引腳BTN及關機識別引腳SLPS。The power management unit 10 includes a power management chip U1, a power switch SW, a first resistor R1, a second resistor R2, and a capacitor C1. In this embodiment, the power management chip U1 operates with a power consumption of 0.03 W, and includes a power pin SB, a switch signal detection pin PWR, a power saving mode setting pin SEL, and a voltage control signal output pin. OFF, switch control signal output pin BTN and shutdown identification pin SLPS.
該電源引腳SB與一電子設備的備用電源V電性連接，以獲取工作電源，同時該電源引腳SB通過電容C1接地。在本實施例中，該備用電源V約為5V。該開關機訊號偵測引腳PWR通過第一電阻R1與備用電源V電性連接，同時通過電源開關SW接地，當電源開關SW被按下或者電子設備執行關機操作時，該開關機訊號偵測引腳PWR的電壓被拉低。該省電模式設置引腳SEL通過第二電阻R2與備用電源V電性連接，該省電模式設置引腳SEL通過電子設備的基本輸入輸出系統（Basic Input Output System，BIOS，圖未示）的設定控制電源管理晶片U1處於正常工作模式或省電模式，具體地，當BIOS將省電模式設置引腳SEL設置為高電平有效時，電源管理晶片U1處於省電模式，當BIOS將省電模式設置引腳SEL設置為低電平有效時，電源管理晶片U1處於正常工作模式。該電壓控制訊號輸出引腳OFF用以在電子設備開機時輸出低電平的電壓控制訊號；在電子設備關機後，若電子設備需要處於省電模式時該電壓控制訊號輸出引腳OFF輸出高電平的電壓控制訊號，若電子設備需要處於正常工作模式時輸出低電平的電壓控制訊號。該開關機控制訊號輸出引腳BTN用以在電源開關SW按下一段時間後（本實施例中約為100ms）向輸入輸出晶片30發送開機控制訊號，進而通過南橋40執行開機命令。同時，該開關機控制訊號輸出引腳BTN用以在電子設備執行關機操作後向輸入輸出晶片30發送關機控制訊號，進而通過南橋40執行關機命令。該關機識別引腳SLPS與南橋40電性連接，用以接收南橋40觸發的電訊號，進而判斷電子設備是否關機，若南橋40觸發的電訊號為低電平則判定電子設備已經關機。The power pin SB is electrically connected to the standby power V of an electronic device to obtain the working power, and the power pin SB is grounded through the capacitor C1. In this embodiment, the backup power supply V is approximately 5V. The switch signal detection pin PWR is electrically connected to the backup power source V through the first resistor R1, and is grounded through the power switch SW. When the power switch SW is pressed or the electronic device performs a shutdown operation, the switch signal detection is performed. The voltage at pin PWR is pulled low. The power-saving mode setting pin SEL is electrically connected to the standby power source V through the second resistor R2. The power-saving mode setting pin SEL passes through a basic input/output system (BIOS, not shown) of the electronic device. Setting the control power management chip U1 to be in the normal working mode or the power saving mode, specifically, when the BIOS sets the power saving mode setting pin SEL to the active high level, the power management chip U1 is in the power saving mode, when the BIOS will save power When the mode setting pin SEL is set to active low, the power management chip U1 is in the normal operating mode. The voltage control signal output pin is OFF for outputting a low level voltage control signal when the electronic device is turned on; after the electronic device is turned off, if the electronic device needs to be in the power saving mode, the voltage control signal output pin is outputting a high voltage. A flat voltage control signal that outputs a low level voltage control signal if the electronic device needs to be in the normal operating mode. The switch control signal output pin BTN is configured to send a power-on control signal to the input/output chip 30 after the power switch SW is pressed for a period of time (about 100 ms in this embodiment), and then execute the power-on command through the south bridge 40. At the same time, the switch control signal output pin BTN is used to send a shutdown control signal to the input/output chip 30 after the electronic device performs the shutdown operation, and then execute the shutdown command through the south bridge 40. The shutdown identification pin SLPS is electrically connected to the south bridge 40 for receiving the electrical signal triggered by the south bridge 40, thereby determining whether the electronic device is turned off, and determining that the electronic device has been turned off if the electrical signal triggered by the south bridge 40 is low.
該電源控制電路20用以在電源管理晶片U1的控制下輸出或不輸出驅動電壓，該電源控制電路20包括場效應管Q、柵極電阻Rg、電壓調整器A、第一分壓電阻Rd1、第二分壓電阻Rd2及電容C2。該場效應管Q為P溝道的耗盡型金屬-氧化物-半導體型（Depletion Metal-Oxide Semiconductor），其包括柵極G、源極S及漏極D，該柵極G通過柵極電阻Rg與電源管理晶片U1的電壓控制訊號輸出引腳OFF電性連接，該源極S與備用電源V電性連接。該電壓調整器A包括電壓輸入引腳VIN、電壓調整引腳ADJ及電壓輸出引腳VOUT。該電壓調整引腳ADJ通過第一分壓電阻Rd1接地，同時該電壓調整引腳ADJ還通過第二分壓電阻Rd2及電容C2接地。該電壓輸出引腳VOUT通過電容C2接地，該電壓輸出引腳VOUT的輸出電壓作為驅動電壓，在本實施例中，該驅動電壓約為3V。The power control circuit 20 is configured to output or not output a driving voltage under the control of the power management chip U1. The power control circuit 20 includes a field effect transistor Q, a gate resistor Rg, a voltage regulator A, and a first voltage dividing resistor Rd1. The second voltage dividing resistor Rd2 and the capacitor C2. The field effect transistor Q is a P-channel depletion metal-oxide semiconductor type (Depletion Metal-Oxide Semiconductor), which includes a gate G, a source S and a drain D, and the gate G passes through a gate resistor The Rg is electrically connected to the voltage control signal output pin of the power management chip U1, and the source S is electrically connected to the backup power source V. The voltage regulator A includes a voltage input pin VIN, a voltage adjustment pin ADJ, and a voltage output pin VOUT. The voltage adjustment pin ADJ is grounded through the first voltage dividing resistor Rd1, and the voltage adjustment pin ADJ is also grounded through the second voltage dividing resistor Rd2 and the capacitor C2. The voltage output pin VOUT is grounded through a capacitor C2, and the output voltage of the voltage output pin VOUT is used as a driving voltage. In this embodiment, the driving voltage is about 3V.
該輸入輸出晶片30用以控制電子設備上電或斷電，其包括供電引腳IOVSB、開關機訊號輸入引腳PWRBTN、開關機訊號輸出引腳PWRSB、開關機識別引腳SLP及系統上電引腳PSON。該供電引腳IOVSB電性連接至電壓調整器A的電壓輸出引腳VOUT，以為該輸入輸出晶片30提供工作電壓。該開關機訊號輸入引腳PWRBTN與電源管理晶片U1的開關機控制訊號輸出引腳BTN電性連接，用以接收開機控制訊號或關機控制訊號，該開關機訊號輸出引腳PWRSB與南橋40電性連接，用以將開關機訊號輸入引腳PWRBTN接收到的開機控制訊號或關機控制訊號傳送至南橋40。該系統上電引腳PSON與電子設備的系統電源電性連接，用以控制系統電源上電或斷電，該開關機識別引腳SLP用以在南橋40的控制下進一步控制系統上電引腳PSON，具體地，當該開關機識別引腳SLP收到南橋40發出的高電平訊號後，控制系統上電引腳PSON處於低電平，進而控制電子設備系統電源上電；當該開關機識別引腳SLP收到南橋40發出的低電平訊號後，控制系統上電引腳PSON處於高電平，進而控制電子設備系統電源斷電。The input/output chip 30 is used to control power-on or power-off of the electronic device, and includes a power supply pin IOVSB, a switch signal input pin PWRBTN, a switch signal output pin PWRSB, a switch identification pin SLP, and a system power-on Foot PSON. The power supply pin IOVSB is electrically connected to the voltage output pin VOUT of the voltage regulator A to provide an operating voltage for the input and output wafer 30. The switch signal input pin PWRBTN is electrically connected to the switch control signal output pin BTN of the power management chip U1 for receiving the power-on control signal or the shutdown control signal, and the switch signal output pin PWRSB and the south bridge 40 are electrically connected. The connection is used to transmit the power-on control signal or the shutdown control signal received by the switch signal input pin PWRBTN to the south bridge 40. The system power-on pin PSON is electrically connected to the system power supply of the electronic device to control the system power supply to be powered on or off. The switch identification pin SLP is used to further control the system power-on pin under the control of the south bridge 40. PSON, specifically, when the switch identification pin SLP receives the high level signal sent by the south bridge 40, the control system power-on pin PSON is at a low level, thereby controlling the power supply of the electronic device system; After the identification pin SLP receives the low level signal from the south bridge 40, the control system power-on pin PSON is at a high level, thereby controlling the power supply of the electronic device system to be powered off.
該南橋40用以依據由輸入輸出晶片30傳送的開機控制訊號或關機控制訊號控制輸入輸出晶片30。該南橋40包括供電端子VSB、開關機訊號輸入端子PWRS及開關機使能端子SLPC。該供電端子VSB電性連接至電壓調整器A的電壓輸出引腳VOUT，以為該南橋40提供工作電壓。該開關機訊號輸入端子PWRS與輸入輸出晶片30的開關機訊號輸出引腳PWRSB電性連接，用以接收開機控制訊號或關機控制訊號。該開關機使能端子SLPC同時與輸入輸出晶片30的開關機識別引腳SLP及電源管理晶片U1的關機識別引腳SLPS電性連接，當該南橋40接收到開機控制訊號後，通過開關機使能端子SLPC向開關機識別引腳SLP觸發高電平訊號；當該南橋40接收到關機控制訊號後，通過開關機使能端子SLPC向開關機識別引腳SLP和關機識別引腳SLPS觸發低電平訊號。The south bridge 40 is used to control the input and output wafer 30 according to the power-on control signal or the power-off control signal transmitted from the input/output chip 30. The south bridge 40 includes a power supply terminal VSB, a switch signal input terminal PWRS, and a switch enable terminal SLPC. The power supply terminal VSB is electrically connected to the voltage output pin VOUT of the voltage regulator A to provide an operating voltage for the south bridge 40. The switch signal input terminal PWRS is electrically connected to the switch signal output pin PWRSB of the input/output chip 30 for receiving the power-on control signal or the shutdown control signal. The switch enable terminal SLPC is electrically connected to the switch identification pin SLP of the input/output chip 30 and the shutdown identification pin SLPS of the power management chip U1. When the south bridge 40 receives the power-on control signal, it is turned on and off. The terminal SLPC triggers the high level signal to the switch SLP pin; when the south bridge 40 receives the shutdown control signal, the low frequency is triggered by the switch enable terminal SLPC to the switch identification pin SLP and the shutdown identification pin SLPS. Ping signal.
下面以電子設備開機和電子設備關機兩個過程為例來說明該節能管理電路100控制系統電源上電、系統電源斷電及在關機狀態下省電的工作原理：The following two processes of electronic device booting and electronic device shutdown are taken as an example to illustrate the working principle of the energy-saving management circuit 100 for controlling system power-on, system power-off, and power-saving in a shutdown state:
首先，用戶通過BIOS設置電源管理晶片U1的工作模式，若需要在關機時降低電子設備的功耗，則將省電模式設置引腳SEL設置為高電平有效；若無需在關機時降低電子設備的功耗，則將省電模式設置引腳SEL設置為低電平有效。First, the user sets the operating mode of the power management chip U1 through the BIOS. If the power consumption of the electronic device needs to be reduced during the shutdown, the power saving mode setting pin SEL is set to be active high; if it is not necessary to lower the electronic device during shutdown The power consumption is set to the active mode setting pin SEL active low.
電子設備開機上電：使用者按下電源開關SW，開關機訊號偵測引腳PWR的電壓被拉低，繼而使電壓控制訊號輸出引腳OFF輸出低電平的電壓控制訊號。其後，場效應管Q導通，電壓調整器A工作並輸出驅動電壓，如此輸入輸出晶片30和南橋40均獲得驅動電壓而工作。經延時一段預定的時間（本實施例中為100ms）後，開關機控制訊號輸出引腳BTN發送開機控制訊號，該開機控制訊號通過輸入輸出晶片30傳送至南橋40，南橋40接收到開機控制訊號後，通過開關機使能端子SLPC向輸入輸出晶片30的開關機識別引腳SLP觸發高電平訊號，進而控制系統上電引腳PSON處於低電平，如此電子設備系統電源上電完成開機。The electronic device is powered on: the user presses the power switch SW, and the voltage of the switch signal detection pin PWR is pulled down, and then the voltage control signal output pin is turned OFF to output a low voltage control signal. Thereafter, the field effect transistor Q is turned on, the voltage regulator A operates and outputs a driving voltage, so that both the input/output wafer 30 and the south bridge 40 operate with the driving voltage. After a predetermined period of time (100 ms in this embodiment), the switch control signal output pin BTN sends a power-on control signal, and the power-on control signal is transmitted to the south bridge 40 through the input/output chip 30, and the south bridge 40 receives the power-on control signal. After that, the switch enable terminal SLPC triggers a high level signal to the on/off switch pin SLP of the input/output chip 30, thereby controlling the system power-on pin PSON to be at a low level, so that the electronic device system power-on is powered on.
電子設備關機斷電：使用者執行關機操作，開關機控制訊號輸出引腳BTN發送關機控制訊號，該關機控制訊號通過輸入輸出晶片30傳送至南橋40，南橋40接收到關機控制訊號後，通過開關機使能端子SLPC向輸入輸出晶片30的開關機識別引腳SLP觸發低電平訊號，進而控制系統上電引腳PSON處於高電平，如此即控制電子設備系統電源斷電完成關機。The electronic device is powered off and the power is turned off: the user performs a shutdown operation, and the switch control signal output pin BTN sends a shutdown control signal, and the shutdown control signal is transmitted to the south bridge 40 through the input/output chip 30, and the south bridge 40 receives the shutdown control signal and passes the switch. The machine enable terminal SLPC triggers a low level signal to the on/off identification pin SLP of the input/output chip 30, thereby controlling the system power-on pin PSON to be at a high level, thus controlling the power-off of the electronic device system to complete the shutdown.
另一方面，南橋40通過開關機使能端子SLPC向電源管理晶片U1的關機識別引腳SLPS觸發低電平訊號，電源管理晶片U1判定該電子設備已關機。此時，若電源管理晶片U1的省電模式設置引腳SEL設置為低電平有效，則電源管理晶片U1處於正常工作模式，此時電壓控制訊號輸出引腳OFF輸出低電平的電壓控制訊號，場效應管Q導通，電壓調整器A工作並輸出驅動電壓以維持對輸入輸出晶片30和南橋40提供驅動電壓。On the other hand, the south bridge 40 triggers a low level signal to the shutdown identification pin SLPS of the power management chip U1 through the switch enable terminal SLPC, and the power management chip U1 determines that the electronic device has been turned off. At this time, if the power-saving mode setting pin SEL of the power management chip U1 is set to the active low level, the power management chip U1 is in the normal working mode, and the voltage control signal output pin OFF outputs the low-level voltage control signal. The field effect transistor Q is turned on, the voltage regulator A operates and outputs a driving voltage to maintain the driving voltage to the input and output wafer 30 and the south bridge 40.
若電源管理晶片U1的省電模式設置引腳SEL為高電平有效，則電源管理晶片U1處於省電模式，此時電壓控制訊號輸出引腳OFF輸出高電平的電壓控制訊號，場效應管Q截止，電壓調整器A不工作以停止對輸入輸出晶片30和南橋40提供驅動電壓。顯然，此時輸入輸出晶片30和南橋40在省電模式下均無功耗，可有效的減小電子裝置在關機狀態下的整機功耗。If the power saving mode setting pin SEL of the power management chip U1 is active high, the power management chip U1 is in the power saving mode, and the voltage control signal output pin OFF outputs a high level voltage control signal, and the field effect transistor When Q is off, the voltage regulator A does not operate to stop supplying the driving voltage to the input/output wafer 30 and the south bridge 40. Obviously, at this time, the input/output chip 30 and the south bridge 40 have no power consumption in the power saving mode, and the power consumption of the whole device of the electronic device in the off state can be effectively reduced.
本發明的節能管理電路100電源管理晶片U1設置省電模式，並在省電模式下輸出高電平的電壓控制訊號以控制電源控制電路停止對輸入輸出晶片30和南橋40供電，以此降低電子裝置在關機狀態下的整機功耗。同時，該節能管理電路100還可實現正常的開關機時序。The power management chip 100 of the present invention provides a power saving mode, and outputs a high level voltage control signal in the power saving mode to control the power control circuit to stop supplying power to the input/output chip 30 and the south bridge 40, thereby reducing the electrons. The power consumption of the whole device in the off state. At the same time, the energy saving management circuit 100 can also implement normal switching sequence.
綜上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施方式，舉凡熟悉本案技藝之人士，於爰依本發明精神所作之等效修飾或變化，皆應涵蓋於以下之申請專利範圍內。In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be covered by the following claims.
100．．．節能管理電路100. . . Energy management circuit
10．．．電源管理單元10. . . Power management unit
U1．．．電源管理晶片U1. . . Power management chip
SB．．．電源引腳SB. . . Power pin
PWR．．．開關機訊號偵測引腳PWR. . . Switch signal detection pin
SEL．．．省電模式設置引腳SEL. . . Power saving mode setting pin
OFF．．．電壓控制訊號輸出引腳OFF. . . Voltage control signal output pin
BTN．．．開關機控制訊號輸出引腳BTN. . . Switching machine control signal output pin
SLPS．．．關機識別引腳SLPS. . . Shutdown identification pin
SW．．．電源開關SW. . . switch
R1．．．第一電阻R1. . . First resistance
R2．．．第二電阻R2. . . Second resistance
C1、C2．．．電容C1, C2. . . capacitance
V．．．備用電源V. . . backup power
20．．．電源控制電路20. . . Power control circuit
Q．．．場效應管Q. . . Field effect transistor
Rg．．．柵極電阻Rg. . . Gate resistance
A．．．電壓調整器A. . . Voltage regulator
Rd1．．．第一分壓電阻Rd1. . . First voltage divider resistor
Rd2．．．第二分壓電阻Rd2. . . Second voltage dividing resistor
30．．．輸入輸出晶片30. . . Input and output chip
IOVSB．．．供電引腳IOVSB. . . Power supply pin
PWRBTN．．．開關機訊號輸入引腳PWRBTN. . . Switching machine signal input pin
PWRSB．．．開關機訊號輸出引腳PWRSB. . . Switch signal output pin
SLP．．．開關機識別引腳SLP. . . Switching machine identification pin
PSON．．．系統上電引腳PSON. . . System power-on pin
40．．．南橋40. . . South Bridge
VSB．．．供電端子VSB. . . Power supply terminal
PWRS．．．開關機訊號輸入端子PWRS. . . Switching machine signal input terminal
SLPC．．．開關機使能端子SLPC. . . Switching enable terminal
圖1為本發明較佳實施方式的節能管理電路的電路圖。1 is a circuit diagram of an energy saving management circuit in accordance with a preferred embodiment of the present invention.
100．．．節能管理電路100. . . Energy management circuit
10．．．電源管理單元10. . . Power management unit
U1．．．電源管理晶片U1. . . Power management chip
SB．．．電源引腳SB. . . Power pin
PWR．．．開關機訊號偵測引腳PWR. . . Switch signal detection pin
SEL．．．省電模式設置引腳SEL. . . Power saving mode setting pin
OFF．．．電壓控制訊號輸出引腳OFF. . . Voltage control signal output pin
BTN．．．開關機控制訊號輸出引腳BTN. . . Switching machine control signal output pin
SLPS．．．關機識別引腳SLPS. . . Shutdown identification pin
SW．．．電源開關SW. . . switch
R1．．．第一電阻R1. . . First resistance
R2．．．第二電阻R2. . . Second resistance
C1、C2．．．電容C1, C2. . . capacitance
V．．．備用電源V. . . backup power
20．．．電源控制電路20. . . Power control circuit
Q．．．場效應管Q. . . Field effect transistor
Rg．．．柵極電阻Rg. . . Gate resistance
A．．．電壓調整器A. . . Voltage regulator
Rd1．．．第一分壓電阻Rd1. . . First voltage divider resistor
Rd2．．．第二分壓電阻Rd2. . . Second voltage dividing resistor
30．．．輸入輸出晶片30. . . Input and output chip
IOVSB．．．供電引腳IOVSB. . . Power supply pin
PWRBTN．．．開關機訊號輸入引腳PWRBTN. . . Switching machine signal input pin
PWRSB．．．開關機訊號輸出引腳PWRSB. . . Switch signal output pin
SLP．．．開關機識別引腳SLP. . . Switching machine identification pin
PSON．．．系統上電引腳PSON. . . System power-on pin
40．．．南橋40. . . South Bridge
VSB．．．供電端子VSB. . . Power supply terminal
PWRS．．．開關機訊號輸入端子PWRS. . . Switching machine signal input terminal
SLPC．．．開關機使能端子SLPC. . . Switching enable terminal
Claims (9)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102322913A CN102937829A (en) | 2011-08-15 | 2011-08-15 | Energy-saving management circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201308063A true TW201308063A (en) | 2013-02-16 |
Family
ID=47696730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100129659A TW201308063A (en) | 2011-08-15 | 2011-08-19 | Energy saving management circuit |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US9009501B2 (en) |
| CN (1) | CN102937829A (en) |
| TW (1) | TW201308063A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103676746B (en) * | 2013-12-20 | 2016-08-17 | 青岛歌尔声学科技有限公司 | A kind of switching on and shutting down control circuit and electronic equipment |
| TWI533580B (en) * | 2014-10-17 | 2016-05-11 | 瑞昱半導體股份有限公司 | Control chip and system thereof for power saving |
| US10667342B2 (en) * | 2015-03-31 | 2020-05-26 | Avago Technologies International Sales Pte. Limited | Configurable light source driver device |
| CN107797600A (en) * | 2017-11-02 | 2018-03-13 | 中电科技集团重庆声光电有限公司 | Power supply modulator based on integrative packaging |
| WO2021102629A1 (en) * | 2019-11-25 | 2021-06-03 | 深圳市大疆创新科技有限公司 | Power supply management apparatus, electronic device and movable platform assembly |
| CN114666943B (en) * | 2022-02-28 | 2025-09-26 | 歌尔光学科技有限公司 | Voltage drive circuits and electronic equipment |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200826409A (en) | 2006-12-07 | 2008-06-16 | Inventec Corp | Power-saving circuit and power-saving method |
| TW201020749A (en) * | 2008-11-20 | 2010-06-01 | Micro Star Int Co Ltd | Electronic device for reducing shutdown power consumption of computer motherboard |
| US20100332870A1 (en) * | 2009-06-25 | 2010-12-30 | Micro-Star International Co., Ltd. | Electronic device for reducing power consumption of computer motherboard and motherboard thereof |
| TW201115321A (en) | 2009-10-21 | 2011-05-01 | Acer Inc | Electronic device and power management method thereof |
| CN102147652A (en) * | 2010-02-09 | 2011-08-10 | 鸿富锦精密工业（深圳）有限公司 | Shut-down energy-saving system and shut-down energy-saving method |
| TWM412423U (en) * | 2010-08-13 | 2011-09-21 | Micro Star Int Co Ltd | Computer motherboard for reducing power consumption during sleep mode |
-
2011
- 2011-08-15 CN CN2011102322913A patent/CN102937829A/en active Pending
- 2011-08-19 TW TW100129659A patent/TW201308063A/en unknown
-
2012
- 2012-05-01 US US13/461,732 patent/US9009501B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20130047018A1 (en) | 2013-02-21 |
| US9009501B2 (en) | 2015-04-14 |
| CN102937829A (en) | 2013-02-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2239647B1 (en) | Motherboard with electronic device for reducing power consumption during sleep mode of computer motherboard | |
| CN103970248B (en) | power management circuit and method and computer system | |
| CN102301301B (en) | Computer system powered-off state auxiliary power rail control | |
| EP2267575A2 (en) | Electronic device for reducing power consumption of computer motherboard and motherboard thereof | |
| TW201308063A (en) | Energy saving management circuit | |
| CN101430594A (en) | Electronic system and power supply control method thereof | |
| CN102063172B (en) | Forced shutdown circuit | |
| TWI493831B (en) | Universal serial bus charging device and management method | |
| TW200928982A (en) | Host device and computer system for reducing power consumption in graphic cards | |
| CN103576816A (en) | Startup and shutdown control circuit | |
| TWI693513B (en) | Server system and power saving method thereof | |
| TW201407920A (en) | Charging method and electronic device using the same | |
| TW201416845A (en) | Motherboard | |
| KR20190054708A (en) | Method for reducing standby-power and electronic device thereof | |
| TWI493327B (en) | Power control circuit and method of notebook computer | |
| CN101556499B (en) | Current adjustment device, power supply device, and current adjustment method | |
| CN2909367Y (en) | Plate power supply protection circuit | |
| CN108988300B (en) | Self-power-off circuit structure of notebook power circuit and control method | |
| TW201131345A (en) | Power control system, power control method, and computer system having the same | |
| TWI409622B (en) | Power control circuit applied to electronic apparatus | |
| CN102799249B (en) | A kind of computing machine and power control thereof | |
| CN102193614A (en) | Power control system, power control method and computer system thereof | |
| TWI411911B (en) | Improve the standby power consumption of the power circuit | |
| CN104679210A (en) | Device and method for powering on computer on basis of CPLD controller | |
| US8542001B2 (en) | Power circuit for reducing standby power consumption |