TW201304057A - Method for manufacturing through-silicon via - Google Patents

Abstract

A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.

Description

Method for manufacturing penetrating raft channel structure

This invention relates to a wafer level packaging technique, and more particularly to a method of fabricating a Through-Silicon Via structure.

As the bulk density of electronic components (such as transistors, diodes, resistors, capacitors, etc.) continues to increase, more components are incorporated into a single die. However, as the number of components increases, the number and length of interconnects of the wafer must increase significantly, and the RC delay and energy consumption increase.

In order to solve the above limitation, the conventional technology uses a two-dimensional space or a three-dimensional space such as a system on chip (SoC) and a system in package (SiP) to package a plurality of chips into one package component. In order to accommodate more components in a single die, the need for miniaturization and high performance is achieved. However, in the conventional two-dimensional space or three-dimensional space-mounting technology, wire bonding or Flip Chip interconnection (Interconnection) is often used between the wafers. As the number of stacked wafers increases, the wafer size also increases, and the longer the required wire length, thus affecting the performance of the entire package system.

In recent years, the industry has created a new three-dimensional space interconnect technology, a Through Silicon Via (TSV) technology. The through-pass channel is a vertical electrical connection through a germanium wafer or die that provides interconnection of vertically aligned electronic components via internal wiring, which significantly increases the line width and speed of the interconnect and reduces power consumption. It also reduces the complexity and overall size of multi-chip electronic circuits.

In accordance with an object of the present invention, a method of fabricating a through-channel structure is provided, comprising the steps of: first providing a stacked structure comprising a sequentially stacked substrate and an inner layer dielectric (ILD); Wherein the stacked structure has an opening through the inner dielectric layer and extending into the substrate. Next, an isolation layer and a metal barrier layer are formed on the sidewalls of the stacked structure and the opening, and an upper metal layer is provided on the stacked structure to fill the opening. Then, using the metal barrier layer as a stop layer, a first planarization process is performed to remove a portion of the upper metal. Then, using the inner dielectric layer as the stop layer, performing a second planarization process, thereby removing a portion of the upper metal, a portion of the metal barrier layer, and a portion of the isolation layer, wherein the second planarization process has a light interferometry (light interferometry) Or the end of the grinding determined by the motor current.

In an embodiment of the invention, the first planarization process is a chemical mechanical polishing (CMP) process for removing the polishing rate of the metal barrier layer, which is substantially smaller than that for removing the upper metal layer. The polishing rate of the layer. Wherein, the polishing rate for removing the upper metal layer and the polishing rate for removing the metal barrier layer are substantially greater than two. In an embodiment of the invention, the polishing rate for removing the upper metal layer and the polishing rate for removing the metal barrier layer are substantially greater than or equal to 100.

In an embodiment of the invention, the first planarization process has a polishing end point determined by a change in light reflection occurring between the upper metal layer and the metal barrier layer. The polishing end point of the second planarization process is determined by a change in optical interference value or a change in eddy current feedback intensity occurring between the inner dielectric layer and the isolation layer. These polishing endpoints are determined by a white-light interferometer or an eddy current detector.

In an embodiment of the invention, prior to providing the upper metal layer, a seed deposition is performed on the metal barrier layer.

According to another object of the present invention, there is provided a method of fabricating a through-channel structure comprising the steps of first providing a stacked structure comprising sequentially stacked substrates and an inner dielectric layer, wherein the stacked structure has a The opening passes through the inner dielectric layer and extends into the substrate. Next, an isolation layer and a metal barrier layer are formed on the sidewalls of the stacked structure and the opening; and on the stacked structure, an upper metal layer is provided to fill the opening. Then, using the metal barrier layer as a stop layer, a first planarization process is performed to remove a portion of the upper metal. Thereafter, the isolation layer is used as a stop layer, and then a second planarization process is performed to remove a portion of the upper metal and a portion of the metal barrier layer, wherein the second planarization process is determined by optical interference values or electromechanical currents. The grinding end point. Performing a third planarization process by using the inner dielectric layer as a stop layer, thereby removing a portion of the upper metal, a portion of the metal barrier layer, and a portion of the isolation layer, wherein the third planarization process has a light interference value or The end point of the grinding determined by the electromechanical current.

In an embodiment of the invention, the first planarization process is a chemical mechanical polishing process for removing the polishing rate of the metal barrier layer, substantially less than the polishing rate used to remove the upper metal layer.

In another embodiment of the present invention, the first planarization process has a polishing end point determined by a change in light reflection value occurring between the upper metal layer and the metal barrier layer. In an embodiment of the invention, the polishing end point of the second planarization process is determined by a change in optical interference value or a change in eddy current feedback intensity occurring between the metal barrier layer and the isolation layer. In an embodiment of the invention, the polishing end point of the third planarization process is determined by a change in optical interference value or an eddy current feedback intensity occurring between the inner dielectric layer and the isolation layer. These polishing endpoints are determined by a white light interferometer.

According to still another object of the present invention, there is provided a method of fabricating a through-channel structure comprising the steps of first providing a stacked structure comprising a substrate, an inner dielectric layer and a dielectric stop layer which are sequentially stacked. Wherein the stacked structure has an opening that passes through the dielectric stop layer and the inner dielectric layer and extends into the substrate. Next, an isolation layer and a metal barrier layer are formed on the sidewalls of the stacked structure and the opening; and on the stacked structure, an upper metal layer is provided to fill the opening. Then, using the metal barrier layer as the stop layer, performing a first planarization process, thereby removing a portion of the upper metal, wherein the first planarization process is used to remove the polishing rate of the metal barrier layer, which is substantially smaller than In addition to the polishing rate of the upper metal layer. Then, using the dielectric stop layer as a stop layer, a second planarization process is performed to remove a portion of the upper metal, a portion of the metal barrier layer, and a portion of the isolation layer, wherein the second planarization process is used to remove the isolation layer The polishing rate is substantially greater than the polishing rate used to remove the dielectric stop layer. Then, using the inner dielectric layer as a stop layer, a third planarization process is performed to remove the dielectric stop layer, a portion of the upper metal layer, a portion of the metal barrier layer, and a portion of the isolation layer, wherein the third planarization layer The polishing rate used to remove the dielectric stop layer is substantially greater than the polishing rate used to remove the inner dielectric layer.

In an embodiment of the invention, the material of the dielectric stop layer is selected from the group consisting of tantalum nitride (SiN), niobium oxynitride (SiCN), tantalum carbide (SiC), and any combination thereof. .

In an embodiment of the invention, the first planarization process is a chemical mechanical polishing process for removing the polishing rate of the upper metal layer and the polishing rate for removing the metal barrier layer. The ratio is substantially greater than 2. In an embodiment of the invention, the polishing rate for removing the upper metal layer and the polishing rate for removing the metal barrier layer are substantially greater than or equal to 100.

In an embodiment of the invention, the second planarization process is a chemical mechanical polishing process for removing the polishing rate of the isolation layer and the polishing rate for removing the dielectric stop layer, the ratio of the two is substantially Greater than 2.

In an embodiment of the invention, the third planarization process is a chemical mechanical polishing process for removing the polishing rate of the dielectric stop layer and the polishing rate for removing the inner dielectric layer, both The ratio is substantially greater than 2.

According to the above, some embodiments of the present invention provide a method for determining the polishing end point by measuring the light reflection value and the light interference value or electromechanical current emitted by the structural layer that is undergoing the planarization process, and applying the same. In the process of penetrating the 矽 channel structure. Wherein, the penetrating ruthenium channel structure is formed in a stacked structure comprising a substrate and a dielectric layer which are sequentially stacked. In order to form the through-pass channel structure, at least one more planarization process must be performed to partially remove the isolation layer, the metal barrier layer and the upper metal layer which are subsequently formed on the inner dielectric layer. In the flattening process, the polishing end point of the metal barrier layer is determined by the intensity of the light reflection, and the interference end of the white layer and the eddy current feedback intensity are used to determine the polishing end point of the isolation layer and the upper layer metal. In turn, the planarization process can be accurately stopped at the interface between adjacent two layers. In other embodiments of the present invention, a dielectric stop layer is provided between the inner dielectric layer and the upper metal layer, and the different selection ratios of different materials are matched by the chemical mechanical polishing slurry. Measuring the change in the polishing rate, you can also accurately grasp the grinding end of the flattening process.

If the planarization process is divided into a plurality of polishing steps, the above method is used to determine the polishing end point, the polishing thickness can be precisely controlled, and the wafer surface flatness can be improved and the process stability can be controlled.

The following is a detailed description of the manufacture and use of the present invention in the preferred embodiments. It is to be noted that the present invention is directed to some possible inventive concepts that can be embodied in various specific embodiments. The embodiments described below are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. All figures and descriptions in the embodiments, like reference numerals, will be used to identify similar elements.

1A-1E are cross-sectional views of a process for fabricating a through-pass channel structure 116, in accordance with a preferred embodiment of the present invention. Referring to FIG. 1A, a stacked structure 12 including a tantalum substrate 102 and an inner dielectric layer 106 is first provided. The inner dielectric layer 106 is formed on the germanium substrate 102 and has integrated circuit elements 104 such as wires, transistors, diodes, resistors, and capacitors. At least one opening 108 is formed in the stacked structure. The inner dielectric layer 106 is preferably a low-k material layer, or is, for example, tantalum nitride (SiN), tantalum carbide (SiCN), tantalum carbide (SiC), dioxide. A dielectric material such as ytterbium (SiO2), undoped bismuth glass (USG), tetraethoxy decane (TEOS), or any combination thereof.

Referring to FIG. 1B, the opening 108 of the stacked structure 12 penetrates the inner dielectric layer 106 and extends into the crucible substrate 102. Next, on the stacked structure 12 and the sidewall 108b of the opening 108, an isolation layer 112 and a metal barrier layer 118 are sequentially formed. In some embodiments of the present invention, the isolation layer 112 is an insulating material such as tantalum oxide, tantalum nitride or a combination thereof to insulate the through-channel structure 116 from the tantalum substrate 102; the metal barrier layer 118 is For example, titanium nitride (TiN), titanium Titanium (Ti), tantalum nitride (TaN) or any combination of the above materials.

Next, a metal filling process is performed on the stacked structure 12, and the opening 108 is filled with a metal material such as copper (Cu) or aluminum (Al), and an upper metal layer is formed on the inner dielectric layer 106 of the stacked structure 12. 114 (as shown in Figure 1C). In some preferred embodiments of the present invention, a seed layer 122 is formed over the metal barrier layer 118 prior to the metal fill process to form the upper metal layer 114. The seed layer 112 preferably has the same material as the upper metal layer 114, such as copper (Cu) formed by electroplating.

Thereafter, a first planarization process is performed, such as performing a chemical mechanical polishing process, removing the upper metal layer 114 over the metal barrier layer 118, and terminating the chemical mechanical polishing process on the metal barrier layer 118 (FIG. 1D) Drawn). In the chemical mechanical polishing process, the polishing rate of the metal barrier layer 118 is removed differently from the polishing rate of the upper metal layer 114.

In some embodiments of the invention, the first planarization process removes the polishing rate of the metal barrier layer 118 less than the polishing rate of the upper metal layer 114. Wherein, the polishing rate for removing the upper metal layer 114 and the polishing rate for removing the metal barrier layer 118 are substantially greater than two. In a preferred embodiment of the invention, the ratio of the polishing rate used to remove the upper metal layer 114 to the polishing rate used to remove the metal barrier layer 118 is substantially greater than or equal to 100.

In general, it is quite difficult to accurately determine the polishing end of the CMP process by conventional methods. For example, if the chemical mechanical polishing process is scheduled to stop on the metal barrier layer 118, while the slurry contacts the metal barrier layer 118, the chemical mechanical polishing process is usually difficult to stop immediately, but will be in the metal. Over-grinding occurs on the barrier layer 118.

In some embodiments of the present invention, the flattening end point is determined by using the difference in the polishing rate and the In-Situ Rate Monitor (ISRM) to determine the flattening process more accurately. The grinding step is stopped on the metal barrier layer 118. Moreover, since the metal barrier layer 118 and the upper metal layer 114 are different in corrosion resistance to the same slurry, the polishing rate of the metal barrier layer 118 is removed by controlling the chemical mechanical polishing process and the polishing of the upper metal layer 114 is removed. The rate can be such that the metal barrier layer 118 after planarization has the same level as the upper metal layer 114.

On the other hand, however, the end point of the first flattening process can also be determined using other methods. In some embodiments of the present invention, the first planarization process utilizes a red laser detector to detect changes in reflected light intensity occurring between the upper metal layer 114 and the metal barrier layer 118. Determine the end point of the grinding.

Among these embodiments, an In-Situ Rate Monitor (ISRM) red laser detector is used to measure the polishing end point of the first planarization process. Since, during the first planarization process, the metal barrier layer 118 and the upper metal 114 are exposed to a red laser, different light reflection values are generated. When the first planarization process proceeds to the interface of the metal barrier layer 118 and the upper metal 114, the light reflection value changes. By measuring the change in the light reflection value, the polishing end point of the first planarization process can be determined, and the first planarization process is stopped on the interface of the metal barrier layer 118 and the upper metal 114.

Then, the inner dielectric layer 106 is used as a termination layer, and then a second planarization process, preferably a chemical mechanical polishing process, removes a portion of the upper metal layer 114, a portion of the metal barrier layer 118, and a portion of the isolation layer. 112 to form a through-pass channel structure 116 (as depicted in Figure 1E).

The second planarization process is a white light interferometer that determines the endpoint of the polishing by measuring the change in light interference. Since, during the second planarization process, the inner dielectric layer 106 and the isolation layer 112 are subjected to white light, and different light interference values are generated. When the second planarization process proceeds to the interface of the inner dielectric layer 106 and the isolation layer 112, the light interference value changes. By measuring the change in the interference value of the light, the second planarization process can be accurately stopped on the interface between the inner dielectric layer 106 and the isolation layer 112. Therefore, the inner dielectric layer 106 filled in the opening 108 can be protected from over-etching.

In the present embodiment, the polishing end point of the second planarization process is determined by observing a change in the spectral change of light interference occurring between the inner dielectric layer 106 and the isolation layer 112 using a white light interferometer.

In addition, the polishing end point of the second planarization process can also be determined by the electromechanical current change of the induction polishing machine. For example, the frictional forces experienced by the grinding machine may vary for different abrasive environments (eg, different layers). The change in frictional force can be manifested by a change in the eddy current feedback intensity of the inductive metal polishing pad. When the planarization process proceeds to the interface of the adjacent two layers, the frictional force experienced by the grinding machine changes, which in turn causes the feedback strength of the eddy current to change accordingly. That is, when the second planarization process proceeds to the interface between the inner dielectric layer 106 and the isolation layer 112, an eddy current sensor can be used to measure the variation of the eddy current feedback intensity and make the second flat The process is precisely stopped at the interface of the inner dielectric layer 106 and the isolation layer 112.

In addition, other changes in electromechanical currents released by the grinding machine, such as changes in current produced by the magnetoresistance, can be used to determine the end point of the second planarization process. The operational use of the polishing endpoint detection system, the ISRM red laser detector, the white light interferometer, and the eddy current sensor is well known to those of ordinary skill in the art and will not be described below.

2A-2C are cross-sectional views of a process for fabricating a through-pass channel structure 216, in accordance with another preferred embodiment of the present invention. This embodiment is a continuation of the structure of Fig. 1C, and the difference from the embodiment shown in Figs. 1A to 1E is only that the selected polishing stop layer is different.

Referring to FIG. 2A, a first planarization process is performed using the metal barrier layer 218 as a termination layer, such as a chemical mechanical polishing process to remove the upper metal layer 214 over the metal barrier layer 218. The polishing rate of the chemical mechanical polishing process to remove the metal barrier layer 218 is different from the polishing rate of the upper metal layer 214.

In some embodiments of the invention, the first planarization process removes the polishing rate of the metal barrier layer 218 less than the polishing rate of the upper metal layer 214. Therein, the polishing rate used to remove the upper metal layer 214 and the polishing rate used to remove the metal barrier layer 218 are substantially greater than two. In a preferred embodiment of the invention, the polishing rate used to remove the upper metal layer 214 and the polishing rate used to remove the metal barrier layer 218 are substantially greater than or equal to 100.

On the other hand, however, the end point of the first flattening process can also be determined using other methods. For example, in some embodiments of the present invention, the first planarization process is performed by measuring an optical reflection between the upper metal layer 214 and the metal barrier layer 218 by using an ISRM red laser detector. Change to determine the end of the grinding.

Then, using the isolation layer 212 as a termination layer, and then performing a second planarization process, preferably a chemical mechanical polishing process, removing a portion of the upper metal layer 214 and a portion of the metal barrier layer 218 (as shown in FIG. 2B) ). The second planarization process is a white light interferometer that determines the endpoint of the polishing by measuring the change in light interference. The polishing end point of the second planarization process is determined by the change in the interference value of the light occurring between the metal barrier layer 218 and the isolation layer 212.

Then, the inner dielectric layer 206 is used as the termination layer, and then a third planarization process, preferably a chemical mechanical polishing process, removes a portion of the isolation layer 212 above the inner dielectric layer 206, and a portion of the upper metal layer. Layer 214 and a portion of metal barrier layer 218 form a through-pass channel structure 216. (as shown in Figure 2C). Like the second planarization process, the third planarization process is also a white light interferometer that determines the endpoint of the polishing by measuring the change in optical interference. The polishing end point of the third planarization process is determined by the change in the interference value of the light occurring between the inner dielectric layer 206 and the isolation layer 212.

Similarly, the polishing end points of the second planarization process and the third second planarization process of the above embodiments may also measure the metal barrier layer 218 and the isolation layer 212 and the inner dielectric layer 206 and the isolation layer 212. The change between the eddy current feedback strength is determined.

3A through 3G are cross-sectional views of a process for fabricating a through-pass channel structure 316, in accordance with a preferred embodiment of the present invention. Referring to FIG. 3A, a stacked structure 32 including a substrate 302, an inner dielectric layer 306, and a dielectric stop layer 301 is first provided. The inner dielectric layer 306 is formed on the germanium substrate 302 and has integrated circuit elements 304 such as wires, transistors, diodes, resistors, and capacitors. An opening 308 is formed in the stacked structure. The inner dielectric layer 306 is preferably a low dielectric constant material layer, or is made of, for example, tantalum nitride, tantalum carbide, tantalum carbide, hafnium oxide, undoped germanium glass, tetraethoxy germane, and the like. Made of dielectric material. The material of the dielectric stop layer 301 is preferably selected from the group consisting of tantalum nitride (SiN), niobium oxynitride (SiCN), tantalum carbide (SiC), and any combination thereof.

Referring to FIG. 3B, the opening 308 of the stacked structure 32 penetrates the inner dielectric layer 306 and the dielectric stop layer 301 and extends into the crucible substrate 302. Next, on the stacked structure 32 and the sidewall 308b of the opening 308, an isolation layer 312 and a metal barrier layer 318 are formed in sequence (as shown in FIG. 3C). In some embodiments of the present invention, the isolation layer 312 is an insulating material such as tantalum oxide, tantalum nitride or a combination thereof to insulate the through-channel structure 316 from the tantalum substrate 302; the metal barrier layer 318 is For example, titanium nitride, titanium, tantalum nitride or any combination of the above materials is used.

Next, a metal filling process is performed on the stacked structure 32, and the opening 308 is filled with a metal material such as copper or aluminum, and the upper metal layer 314 is formed on the inner dielectric layer 306 of the stacked structure 32 (as shown in FIG. 3D). Drawn). In some preferred embodiments of the present invention, a seed layer 322 is formed over the metal barrier layer 318 prior to the metal fill process to form the upper metal layer 314. The seed layer 322 preferably has the same material as the upper metal layer 314, such as copper (Cu) formed by electroplating.

Thereafter, a first planarization process is performed, such as performing a chemical mechanical polishing process, removing the upper metal layer 314 over the metal barrier layer 318, and terminating the chemical mechanical polishing process on the metal barrier layer 318 (eg, 3E) The figure shows). Wherein, the polishing rate of the chemical mechanical polishing process removing the metal barrier layer 318 is different from the polishing rate of removing the upper metal layer 314.

In some embodiments of the invention, the first planarization process removes the polishing rate of the metal barrier layer 318 less than the polishing rate of the upper metal layer 314. Wherein, the polishing rate for removing the upper metal layer 314 and the polishing rate for removing the metal barrier layer 318 are substantially greater than two. In a preferred embodiment of the invention, the ratio of the polishing rate used to remove the upper metal layer 314 to the polishing rate used to remove the metal barrier layer 318 is substantially greater than or equal to 100.

Then, using the dielectric stop layer 301 as a termination layer, a second planarization process, preferably a chemical mechanical polishing process, is performed to remove the isolation layer 312 on the dielectric stop layer 301, a portion of the upper metal layer 314, and A portion of the metal barrier layer 318 (as depicted in Figure 3F).

Wherein, the polishing rate of the chemical mechanical polishing process removing the isolation layer 312 is different from the polishing rate of removing the dielectric stop layer 301. In some embodiments of the invention, the second planarization process removes the polishing rate of the dielectric stop layer 301 less than the polishing rate of the isolation isolation layer 312. In addition, the second planarization process removes the polishing rate of the dielectric stop layer 301, also less than the polishing rate of removing the metal barrier layer 318 and removing the upper metal layer 314. Therein, the polishing rate used to remove the spacer layer 312 and the polishing rate used to remove the dielectric stop layer 301 are substantially greater than two.

Then, the inner dielectric layer 306 is used as the termination layer, and then a third planarization process, preferably a chemical mechanical polishing process, removes the dielectric stop layer 301, a portion of the upper metal layer 314, and a portion of the metal barrier layer. A portion 318 and a portion of the isolation layer 312 are formed to form a through-pass channel structure 316. (as shown in Figure 3G).

Wherein, the CMP process removes the inner dielectric layer 306 at a different polishing rate than the removal of the dielectric stop layer 301. In some embodiments of the invention, the third planarization process removes the inner dielectric layer 306 at a polishing rate that is less than the removal rate of the dielectric stop layer 301. Wherein, the polishing rate for removing the dielectric stop layer 301 and the polishing rate for removing the inner dielectric layer 306 are substantially greater than two.

According to the above, some embodiments of the present invention provide a method for determining the polishing end point by measuring the light reflection value, the light interference value or the electromechanical current emitted by the structural layer being subjected to the planarization process, and applying the same In the process of penetrating the 矽 channel structure. Wherein, the penetrating ruthenium channel structure is formed in a stacked structure comprising a substrate and a dielectric layer which are sequentially stacked. In order to form the through-pass channel structure, at least one more planarization process must be performed to partially remove the isolation layer, the metal barrier layer and the upper metal layer which are subsequently formed on the inner dielectric layer.

In the flattening process, the polishing end point of the metal barrier layer is determined by the intensity of the light reflection, and the interference end of the white layer and the eddy current feedback intensity are used to determine the polishing end point of the isolation layer and the upper layer metal. In turn, the planarization process can be accurately stopped on these interfaces.

In other embodiments of the present invention, a dielectric stop layer is provided between the inner dielectric layer and the upper metal layer, and the different selection ratios of different materials are matched by the chemical mechanical polishing slurry. Measuring the change in the polishing rate, you can also accurately grasp the grinding end of the flattening process.

If the planarization process is divided into a plurality of polishing steps, the above method is used to determine the polishing end point, the polishing thickness can be precisely controlled, and the wafer surface flatness can be improved and the process stability can be controlled.

While the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and it is to be understood by those of ordinary skill in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

12. . . Stack structure

twenty two. . . Stack structure

32. . . Stack structure

102. . . Substrate

104. . . Integrated circuit component

106. . . Inner dielectric layer

108. . . Opening

108b. . . Side wall of the opening

112. . . Isolation layer

114. . . Upper metal layer

116. . . Penetrating tunnel structure

118. . . Metal barrier

122. . . Seed deposition

202. . . Substrate

204. . . Integrated circuit component

206. . . Inner dielectric layer

208. . . Opening

208b. . . Side wall of the opening

212. . . Isolation layer

214. . . Upper metal layer

216. . . Penetrating tunnel structure

218. . . Metal barrier

222. . . Seed deposition

301. . . Dielectric stop layer

302. . . Substrate

304. . . Integrated circuit component

306. . . Inner dielectric layer

308. . . Opening

308b. . . Side wall of the opening

312. . . Isolation layer

314. . . Upper metal layer

316. . . Penetrating tunnel structure

318. . . Metal barrier

322. . . Seed deposition

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

1A through 1E are cross-sectional views showing a process for fabricating a through-pass channel structure in accordance with a preferred embodiment of the present invention.

2A through 2C are cross-sectional views showing a process for fabricating a through-pass channel structure in accordance with a preferred embodiment of the present invention.

3A through 3G are cross-sectional views showing a process for fabricating a through-pass channel structure in accordance with a preferred embodiment of the present invention.

twenty two. . . Stack structure

202. . . Substrate

204. . . Integrated circuit component

206. . . Inner dielectric layer

212. . . Isolation layer

214. . . Upper metal layer

218. . . Metal barrier

Claims (20)

A manufacturing method of a Through-Silicon Via (TSV), comprising: providing a stacked structure, comprising a substrate stacked in sequence and an Internal Layer Dielectric (ILD), wherein the The stacked structure has an opening passing through the inner dielectric layer and extending into the substrate; forming an isolation layer and a metal barrier layer on the sidewall of the stacked structure and the opening; Structurally, an upper metal layer is provided to fill the opening; the metal barrier layer is a stop layer, a first planarization process is performed, thereby removing a portion of the upper metal; and the inner dielectric layer is After a stop, a second planarization process is performed to remove a portion of the upper metal, a portion of the metal barrier layer, and a portion of the isolation layer, wherein the second planarization process has a light interferometry (light interferometry) Or a grinding end determined by a motor current. The manufacturing method of the through-pass channel structure according to claim 1, wherein the first planarization process is a chemical mechanical polishing (CMP) process for removing the metal barrier layer. A polishing rate is substantially less than a polishing rate used to remove the upper metal layer. The manufacturing method of the through-pass channel structure according to claim 1, wherein the first planarization process is for removing the polishing rate of the upper metal layer and the method for removing the metal barrier layer The polishing rate, the ratio of the two is substantially greater than two. The manufacturing method of the through-pass channel structure according to claim 3, wherein the polishing rate for removing the upper metal layer and the polishing rate for removing the metal barrier layer are both The ratio is substantially greater than or equal to 100. The method for fabricating a through-channel structure according to claim 1, wherein the first planarization process has a change in light reflectance caused by the upper metal layer and the metal barrier layer. The determined end point of the grinding. The method for fabricating a through-channel structure according to claim 5, wherein the polishing end of the second planarization process is performed by a layer between the inner dielectric layer and the isolation layer. The change in optical interference value or the change in the intensity of an eddy current feedback is determined. The method of manufacturing a penetrating raft structure according to claim 6, wherein the polishing ends are determined by a white-light interferometer or an eddy current detector. The method of fabricating a through-pass channel structure according to claim 1, wherein before the opening is provided to fill the opening, a seed deposition is performed on the metal barrier layer. A method of fabricating a through-channel structure includes: providing a stacked structure comprising a substrate and an inner dielectric layer stacked in sequence, wherein the stacked structure has an opening through the inner dielectric layer And extending into the substrate; forming an isolation layer and a metal barrier layer on the sidewall of the stacked structure and the opening; on the stacked structure, providing an upper metal layer to fill the opening; The metal barrier layer is a stop layer, and a first planarization process is performed to remove a portion of the upper metal; and the isolation layer is a stop layer, and a second planarization process is performed to remove a portion of the upper layer. a metal and a portion of the metal barrier layer, wherein the second planarization process has a polishing end point determined by an optical interference value or an electromechanical current; and the inner dielectric layer is a stop layer a third planarization process for removing a portion of the upper metal, a portion of the metal barrier layer, and a portion of the isolation layer, wherein the third planarization process has a light interference value or an electromechanical current Given a polishing end point. The manufacturing method of the through-pass channel structure according to claim 9, wherein the first planarization process is a chemical mechanical polishing process for removing a polishing rate of the metal barrier layer, substantially less than A polishing rate used to remove the upper metal layer. The method for fabricating a through-channel structure according to claim 9, wherein the first planarization process has a change in light reflectance caused by the upper metal layer and the metal barrier layer. The determined end point of the grinding. The manufacturing method of the through-pass channel structure according to claim 11, wherein the polishing end of the second planarization process is performed by a light generated between the metal barrier layer and the isolation layer. The change in interference value or the change in the intensity of an eddy current feedback is determined. The method for fabricating a through-pass channel structure according to claim 12, wherein the polishing end of the third planarization process is performed by a layer between the inner dielectric layer and the isolation layer. The change in optical interference value or the change in the intensity of an eddy current feedback is determined. The manufacturing method of the through-pass channel structure according to claim 13, wherein the polishing end points are determined by a white light interferometer or an eddy current detector. A manufacturing method for penetrating a ruthenium channel structure, comprising: providing a stacked structure comprising a substrate, an inner dielectric layer and a dielectric stop layer stacked in sequence, wherein the stacked structure has an opening through a dielectric stop layer and the inner dielectric layer extend into the substrate; forming an isolation layer and a metal barrier layer on the stack structure and the sidewall of the opening; Providing an upper metal layer to fill the opening; using the metal barrier layer as a stop layer, performing a first planarization process to remove a portion of the upper metal, wherein the first planarization process is used to remove a polishing rate of the metal barrier layer is substantially smaller than a polishing rate for removing the upper metal layer; and the dielectric stop layer is a stop layer, and a second planarization process is performed to remove a portion of the An upper metal, a portion of the metal barrier layer, and a portion of the isolation layer, wherein the second planarization process is used to remove a polishing rate of the isolation layer, substantially larger than a study for removing the dielectric stop layer And performing a third planarization process by using the inner dielectric layer as a stop layer, thereby removing the dielectric stop layer, a portion of the upper metal layer, a portion of the metal barrier layer, and a portion of the metal layer An isolation layer, wherein the third planarization process is used to remove a polishing rate of the dielectric stop layer substantially greater than a polishing rate used to remove the inner dielectric layer. The method for manufacturing a through-pass channel structure according to claim 15, wherein the material of the dielectric stop layer is selected from the group consisting of tantalum nitride (SiN), tantalum carbide (SiCN), and tantalum carbide ( A group of SiC) and any combination thereof. The manufacturing method of the through-pass channel structure according to claim 15, wherein the first planarization process is a chemical mechanical polishing process for removing the polishing rate of the upper metal layer and for moving In addition to the polishing rate of the metal barrier layer, the ratio of the two is substantially greater than two. The method of fabricating a through-pass channel structure according to claim 17, wherein the first planarization process is for removing the polishing rate of the upper metal layer and the method for removing the metal barrier layer The polishing rate, the ratio of the two is substantially greater than or equal to 100. The manufacturing method of the through-pass channel structure according to claim 15, wherein the second planarization process is a chemical mechanical polishing process for removing the polishing rate of the isolation layer and for removing The polishing rate of the dielectric stop layer, the ratio of the two is substantially greater than two. The manufacturing method of the through-pass channel structure according to claim 15, wherein the third planarization process is a chemical mechanical polishing process for removing the polishing rate of the dielectric stop layer and for moving In addition to the polishing rate of the inner dielectric layer, the ratio of the two is substantially greater than two.