201250575 六、發明說明： 【發明所屬之技術領域】 本發明涉及基於開關的混合存儲系統 涉及關於半導體存儲裳置的基於 /、扣供方法’尤其 供方法。 私射絲統及其提 【先前技術】 隨著對更大電腦存儲空間的需求的増加 ==:/:4存儲媒介等，術= 貝枓的各種硬雜決讀，但硬碟的 ^其是’在現有驗枝中，料f料存 間的，1面’減湖不能滿足具有高速刺登錄/輸出性能的 =體磁片的資料處理速度的介面。因此，現有技術的解決方 案不能很好地利用記憶體磁片的性能。 【發明内容】 為了解決上述問題，本發明提供基於開關的混合存儲系統 及其提供方法。在具有代紐的實_巾，第—控制器 結合於系統控制板’而雙倍數據速率半導體存儲裝置（D_e201250575 VI. Description of the Invention: [Technical Field] The present invention relates to a switch-based hybrid storage system relating to a method based on /, a deduction method for semiconductor storage skirts. Private film system and its mention [prior art] With the increase in the demand for more computer storage space ==: /: 4 storage media, etc., surgery = Bellow's various hard-witted reading, but the hard disk's ^ its It is 'in the existing inspection, the material f storage, one side 'minus lake can not meet the high-speed stab registration / output performance of the body magnetic sheet data processing speed interface. Therefore, prior art solutions do not make good use of the performance of the memory disk. SUMMARY OF THE INVENTION To solve the above problems, the present invention provides a switch-based hybrid storage system and a method of providing the same. In the case of a daisy with a daisy, the first controller is coupled to the system control board' and the double data rate semiconductor memory device (D_e
Data Rate Semiconductor Storage Device (DDR SSD))模組結 合於第一 RAID控制器。DDR SSD模組包括一套DDR SSD部 件。另外’在系統控制板上結合第一開關及第二開關。結合有 硬碟驅動器（Hard Disk Drive (HDD))模組的第二raid控 制器結合於第一開關。HDD模組包括一套HDD/快閃記憶體 SDD部件。另外，在第二開關上結合包括至少一套埠的通信 201250575 為了解決上述現有技術中的問題並達到上述目的，本發明 基於開關的混合射料統及其提供方法糾—實關，包括： 第一 RAID控制器，結合於控制板；DDR SSD模組，結 合於上述第一 RAID控制器並包括一套雙倍數據速率半導體 存儲裝置（Double Data Rate Semiconductor Storage Device (DDR SSD ));第一開關’結合於上述系統控制板；第The Data Rate Semiconductor Storage Device (DDR SSD) module is combined with the first RAID controller. The DDR SSD module includes a set of DDR SSD components. In addition, the first switch and the second switch are combined on the system control board. A second raid controller incorporating a Hard Disk Drive (HDD) module is coupled to the first switch. The HDD module includes a set of HDD/flash memory SDD components. In addition, a communication including at least one set of ports 201250575 is combined on the second switch. In order to solve the above problems in the prior art and achieve the above object, the present invention is based on a switch-based hybrid projecting system and a method for providing the same, including: A RAID controller is coupled to the control board; the DDR SSD module is combined with the first RAID controller and includes a double data rate semiconductor storage device (DDR SSD); the first switch 'Combined with the above system control board;
二 RAID 控制器，結合於上述第一晶片；HDD模組，結合於上述第二 RAID控制器並包括一套硬碟驅動器（Hard Disk Drive( jjj^d )) /快閃記憶體SDD部件；第二開關’結合於上述系統控制板； 及通信模組’結合於上述第二開關。 在第一實施例中，上述第一 RAID控制器及第二尺八1£)控 制器為基於PCI-Express (PCI-E)的RAID控制器。 另外，還包括結合於上述系統控制板的電源供應部，且還 包括結合於上述HDD模組的電池模組。 另外，上述系統控制板，包括：第一晶片，結合於第一處 理器；第二晶片，結合於第二處理器；及第三晶片結合於第 一晶片。 另外，上述通信模組包括多個琿。 另外，上述第一 RAID控制器及第二raid控制器，各包 括：RAID控制器CPU ’·晶片’結合於上述rajd控制器CI>U ; 及一套輸入/輸出（I/O)連接器’結合於上述晶片。 在此’上述第一 RAID控制器及第二控制器各包括 同位及緩存（parity and cache)控制元件。 在此，本發明的第二實施例，包括：第一 ]^11)控制器， 201250575 結合於包括多個處理器及多個晶片的系統控制板；DDRSSD 模組，結合於上述第一 RAID控制器並包括一套DDR SSD部 件；第一 PCI-Express開關’結合於系統控制板；第二^]^) 控制器，結合於第一 PCI-Express開關；HDD模組，結合於上 述第二RAID控制器並包括一套HDD/快閃記憶體SDD部件； 第二PCI-Express開關，結合於上述系統控制板；及通信模組， 結合於上述第二PCI-Exp ress開關。 在第二實施例中，上述第一 RAID控制器及第二raid控 制器為基於PCI-Express的RAID控制器。 另外，還包括結合於上述系統控制板的電源供應部，且還 包括結合於上述HDD模組的電池模組。 另外，上述系統控制板，包括：第一晶片，結合於第一處 理器；第二晶片，結合於第二處理器；及第三晶片，結合於第 —晶片；而上述通信模組包括多個埠。 在第二實施例中，上述第一 RAID控制器及第二raID控 制器’各包括：RAID控制器CPU ;晶# ’結合於上述 控制器CPU ;及-套輸入/輸出⑽）連接器，結合於上述晶 片。 在此’上述第一 RAH)控制器及第二raID控制器各包括 同位元及緩存控制組件。 - 在此，本發明第三實施例的基於開關的混合存儲系 方法，包括如下步驟：將第一腿〇控制器結合於系统控制、 板；將包括-套DDR SSD的DDR SSD模組結合於上述第一 RAID控制器，將第一開關結合於上述系統控制板；將第二 201250575 RAID控制n結合於上述第—晶片；將包括— #HDD/快閃記 憶體SDD部件的HDD模組結合於上述第二从1〇㈣器；將 第二開關結合於上_統㈣板；及將通賴組結合於上述第 二開關。 在第三實施例中’上述第—控制器及第二議^控 制器為基於PCI-Express的RAJD控制器。 另外’還包括將電源供應部結合於上述系統控制板的步 驟’且還包括將電池模組結合於上述H53D模組的步驟。 根據本發_上鱗徵，本發贿絲於_的混合存儲 裝置系統及其提供方法。 【實施方式】 下面’結合附圖對本發明進行詳細說明。本發明可通過各 種方式實現，且不受本說明書中的較佳實施例的限制。另外， 在附圖中，相同的標記表示相同的原件，而且，除有特殊定義 =外’用於本說明書的所有術語的意思與本領域_人員通 :理解_容相同。在下面_容中，挪指轉體存儲裝 指雙倍數據速率（DGubleDataRate)。另外咖 才曰更碟驅動器（Hard Disk Drive )。 用於本說明書的術語的目的是說明具體實施例而非限制 重游Γ域是’在用於本說明書時，趣是指獨立.片的 列（原來指低價磁片的重複陣列）。一般而言，从仍 =在多個硬碟上的不同地點(因此，卸存儲相同資料 存儲於多個磁片，可使1/〇 (輪入㈣ 均衡的方式«，從而提高其性能。因多個磁片會姆加 201250575 平均故障間贼間，因此，重赫儲資觸可以提高耐故障性。 下面，結合附圖對一實施例中的串聯小型電腦系統介面/ 串聯南級技術接入（PCI_Express)類型的腿〇存儲系統進行 詳細說明。 ^ 如上所述，本發明涉及半導體存儲裝置，尤其涉及基於開 關的混合存儲系統。在本發明的第一實施例中，第一歸〇控 制器結合於系統控制板，而DDRSSD模組結合於第一驗〇 控制器。DDR SSD模組包括一套DDR SSD部件。另外，在系 統控制板上結合第-_及第二關。結合有模組的第 二RAH)控制器結合於第一開關。模組包括一套HDD〆 快閃記憶體SDD部件。另外，在第二開關上結合包括一套（至 少一個）埠的通信模組。 串聯小型電腦系統介面/串聯高級技術接入（ρα·Εχρ_ ) 類型的存職置’在域和記髓磁卩之間進行倾通信的過 程中，同步在主機和記憶體磁片之間發送/接收的資料信號， 從而在支援域的低速資料處理速度的同時，支援記憶體磁片 的告訴資料處理速度，以在現有技術的介面環境中支援記憶 性能以最大限度地進行高速資料處理。在較佳實施例中，刊 用PCI-Express技術但非限制。例如，在本發明中，可利用提 供利用SAS/SATA介面的SAS/SATAl|員型的存儲裝置的 SAS/SATA 技術。 如圖1所不為旨在提供本發明一實施例的串聯電腦襄置 PCMxpress _的控制型存儲裝置結構 概略示意圖。如圖所示，圖i為本發明—實施例的控制 201250575 型Ρα·Εχρ·_的存儲裝置，包括：多個記憶體磁片部 100 ’包括具備又稱高速SSD1⑻的多個揮發性半導體記憶體 的多個記憶體磁片；RAID控制器_，結合於SSD1〇〇 ;介面 部200 ’連接兄憶體磁片部和主機之間；控制部·;辅助電 源部400 ’利用通過介面部勘從主機傳遞的電力進行充電以 維持-定電力；電源控制部5〇〇，將通過介面部2〇〇從主機傳 遞的電力供應至控制部3〇〇、記憶體磁片部觸、備份保存部 600及備健制部700 ’而且，在通過介面部2〇〇從主機傳遞 的電力中斷，或在從主機傳遞的電力發生錯誤時，從辅助電源 部400接收電力並通過控制部3〇〇供應至記憶體磁片部卿及 備份控制部7〇0 ;備份保存部_，保存記憶體磁片部觸的 資料；及備份控制部700，根據來自主機的指示或在從主機傳 遞的電力發生錯誤時，將保存於記憶體磁片部1〇〇的資料備份 於備份保存部600A。 記憶體磁片部1〇〇包括具備用於高速資料登錄/輸出的多 個揮發性半導體記憶體（DDR、DDR2、DDR3、SDRAM # ：) 的多個記憶體磁片，並根據控制部3〇〇的控制輸入/輸出資料。 記憶體磁片部100可使記憶體磁片並行排列。 介面部200連接主機和記憶體磁片部100之間。主機可為 具備PCI-Expreh介面及電源裝置的電腦系統。 “ 控制部300調整在介面部200和記憶體磁片部1〇〇之間發 送/接收的資料信號的同步，以控制介面部200和記憶體磁片 部100之間的資料發送/接收速度。 圖2為RAID控制型SSD81〇的更詳細示意圖。如圖所示， 201250575 PCI-e類型raid控制器_可直接結合於任意數量的 SSD1〇〇。這可尤其實現SSD100的最佳控制。尤其是， 控制器800的使用，具有如下作用： 卜支持當前備份/恢復運行。 2、 通過完成如下事項提供得到改善的備份功能： a) 由内備份控制部決定備份與否（由使用者邀請命 令或狀態監視器決定電源問題）； b) 由内部備份控制部邀請向SSD的資料備份； c) 内部備份控制部向内部備份裝置發送邀請以立即備 份資料； d) 監視對SSD的備份及内部備份控制部的狀態； e) 報告内部備份控制部狀態並結束運行。 3、 通過完成如下事項提供得到改善的恢復功能： a) 由内邛備份控制部決定恢復與否（由使用者邀請命 令或狀態監視器決定電源問題）； b) 由内部備份控制部邀請向SSD的資料恢復； c) 内部備份控制部向内部備份裝置發送邀請以 復資料； d) 監視對SSD的恢復及内部備份控制部的狀態； e) 報告内部備份控制部狀態並結束運行。 _ 圖所示為尚速SSD100的結構概略示意圖。如圖2所 厂、:、'、馬速SSDl〇〇的結構概略示意圖。如圖 =片部刚，包括：主機介面叫這可為圖】的介面= 如圖所示的_介面）；應^㈣3Q2，與備健制部· 201250575 連接·’ ECC控制器304 ;及記憶體控制器3〇6，控制用作高速 存儲裝置的記憶體602的一個以上的區塊6〇4。 圖3為本發明基於開關的混合存儲系統概略示意圖，而圖 4為圖3中的RAID控制器概略示意圖。如圖3至圖4所示， 接入/組件當然是PCI-Express類型的。本發明的系統包括與開 關140A-N及RAID控制器108A-N結合的系統控制板1〇6。 一側或兩側RAH)控制器ι〇8Α可直接結合於系統控制板 106。通過這樣的方式’RAID控制器108A-B可成為用於基於 PCI-E的RAID控制器的PCI_E，而其中的一個可成為用於基 於SAS/SATA的RAID控制器的PCI-E。不管是那一種，系統 控制板都結合於電源供應部118。另外，如圖所示，可在一個 或兩個RAID控制器l〇8A_B上結合DDR SSD模組11〇，而 DDR SSD模組110結合於RAID控制器108A。一般而言，DDR SSD模組110包括一套DDR SSD (記憶體）部件122A-N。如 圖所示，電池模組120可結合於DDRSSD模組11〇。 如圖所示，系統控制板106，包括：第一晶片132A (例 如’ IOH)，結合於第一處理器i30A (例如，IntdXen〇na RAID controller, coupled to the first chip; the HDD module is coupled to the second RAID controller and includes a set of hard disk drives (Hard Disk Drive (jjj^d)) / flash memory SDD components; The second switch 'is coupled to the above system control board; and the communication module' is coupled to the second switch. In the first embodiment, the first RAID controller and the second size controller are PCI-Express (PCI-E) based RAID controllers. In addition, a power supply unit coupled to the system control board is further included, and a battery module coupled to the HDD module is further included. In addition, the above system control board includes: a first wafer coupled to the first processor; a second wafer coupled to the second processor; and a third wafer bonded to the first wafer. In addition, the above communication module includes a plurality of ports. In addition, the first RAID controller and the second raid controller respectively include: a RAID controller CPU '.chip' combined with the rajd controller CI>U; and a set of input/output (I/O) connectors' Combined with the above wafer. Here, the first RAID controller and the second controller each include a parity and cache control element. Here, the second embodiment of the present invention includes: a first controller; 201250575 is coupled to a system control board including a plurality of processors and a plurality of chips; and a DDRSSD module is coupled to the first RAID control And includes a set of DDR SSD components; the first PCI-Express switch is combined with the system control board; the second ^^^) controller is coupled to the first PCI-Express switch; the HDD module is coupled to the second RAID The controller includes a set of HDD/flash memory SDD components; a second PCI-Express switch coupled to the system control board; and a communication module coupled to the second PCI-Exp ress switch. In the second embodiment, the first RAID controller and the second raid controller are PCI-Express based RAID controllers. In addition, a power supply unit coupled to the system control board is further included, and a battery module coupled to the HDD module is further included. In addition, the system control board includes: a first chip coupled to the first processor; a second chip coupled to the second processor; and a third chip coupled to the first wafer; and the communication module includes a plurality of port. In the second embodiment, the first RAID controller and the second raID controller 'each include: a RAID controller CPU; a crystal #' is coupled to the controller CPU; and a set of input/output (10) connectors, combined In the above wafer. Here, the above-mentioned first RAH controller and the second raID controller each include a parity and a cache control component. - Here, the switch-based hybrid memory system method of the third embodiment of the present invention comprises the steps of: combining a first leg press controller with a system control, a board; and combining a DDR SSD module including a set of DDR SSDs The first RAID controller combines the first switch with the system control board; the second 201250575 RAID control n is coupled to the first chip; and the HDD module including the #HDD/flash memory SDD component is combined with The second slave device (4); the second switch is coupled to the upper (four) board; and the responsive group is coupled to the second switch. In the third embodiment, the above-mentioned first controller and second controller are PCI-Express based RAJD controllers. Further, 'the step of incorporating the power supply unit to the above-described system control board' also includes the step of bonding the battery module to the above-described H53D module. According to the present invention, the hybrid storage device system and the method for providing the same are provided. [Embodiment] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. The present invention can be implemented in various ways and is not limited by the preferred embodiments in the specification. In addition, in the drawings, the same reference numerals denote the same originals, and the meanings of all the terms used in the present specification are the same as those in the art. In the following _, the index finger storage refers to the double data rate (DGubleDataRate). In addition, the coffee machine is called the Hard Disk Drive. The terminology used in the specification is intended to be illustrative of specific embodiments and not to limit the scope of the re-playing field. As used in this specification, the term refers to a separate column of tiles (originally referred to as a repeating array of low-cost disks). In general, from still = on different locations on multiple hard disks (thus, unloading the same data stored in multiple floppy disks can make 1/〇 (round-in (four) equalization«), thereby improving its performance. Multiple magnetic sheets will be added to the 201250575 average faulty thief, so the heavy-duty storage can improve the fault resistance. Next, the serial small computer system interface/series south-level technology access in an embodiment is combined with the accompanying drawings. The PCI_Express) type of leg memory system is described in detail. ^ As described above, the present invention relates to a semiconductor memory device, and more particularly to a switch-based hybrid memory system. In the first embodiment of the present invention, the first homeless controller is combined In the system control board, the DDRSSD module is integrated into the first verification controller. The DDR SSD module includes a set of DDR SSD components. In addition, the first and second levels are combined on the system control board. The second RAH) controller is coupled to the first switch. The module includes a set of HDD〆 flash memory SDD components. In addition, a second (switched) communication module is included on the second switch. Computer system interface/series advanced technology access (ρα·Εχρ_) type of storage device's process of transmitting/receiving between host and memory disk in the process of tilt communication between domain and memory core The data signal supports the low-speed data processing speed of the support domain and supports the data processing speed of the memory disk to support the memory performance in the prior art interface environment to maximize high-speed data processing. In the example, PCI-Express technology is used without limitation. For example, in the present invention, SAS/SATA technology that provides a SAS/SATAl|-type storage device using a SAS/SATA interface can be utilized. A schematic diagram of a structure of a control type storage device for providing a serial computer PCMxpress _ according to an embodiment of the present invention. As shown in the figure, FIG. 1 is a storage device for controlling a 201250575 type Ρα·Εχρ·_ according to an embodiment of the present invention. The method includes: a plurality of memory magnetic disk portions 100' including a plurality of memory magnetic sheets having a plurality of volatile semiconductor memories also referred to as high speed SSD1 (8); RAID controller_, combined with SS D1〇〇; the interface 200' is connected between the brother and the magnetic disk portion and the host; the control unit; the auxiliary power supply unit 400' uses the power transmitted from the host through the face to perform charging to maintain the constant power; the power control unit 5〇〇, the power transmitted from the host through the interface 2 is supplied to the control unit 3, the memory disk unit touch, the backup storage unit 600, and the preparation unit 700'.电力The power transmitted from the host is interrupted, or when the power transmitted from the host is incorrect, the power is received from the auxiliary power supply unit 400 and supplied to the memory disk unit and the backup control unit 7〇0 through the control unit 3; The storage unit _ stores the data touched by the memory disk unit; and the backup control unit 700 backs up the data stored in the memory disk unit 1 according to an instruction from the host or when an error occurs in the power transmitted from the host. The backup storage unit 600A. The memory magnetic disk unit 1 includes a plurality of memory magnetic sheets including a plurality of volatile semiconductor memories (DDR, DDR2, DDR3, SDRAM #:) for high-speed data registration/output, and is controlled by the control unit 3〇. 〇 Control input/output data. The memory magnetic sheet portion 100 allows the memory magnetic sheets to be arranged in parallel. The interface 200 is connected between the host and the memory disk unit 100. The host computer can be a computer system with a PCI-Expreh interface and power supply unit. The control unit 300 adjusts the synchronization of the material signals transmitted/received between the dielectric surface portion 200 and the memory magnetic sheet portion 1A to control the data transmission/reception speed between the dielectric surface portion 200 and the memory magnetic sheet portion 100. Figure 2 is a more detailed schematic diagram of the RAID-controlled SSD81〇. As shown in the figure, the 201250575 PCI-e type raid controller can be directly combined with any number of SSD1〇〇. This can especially achieve optimal control of the SSD100. The use of the controller 800 has the following functions: Supporting the current backup/restore operation 2. Providing an improved backup function by completing the following items: a) The backup is determined by the internal backup control unit (by the user to invite the command or The status monitor determines the power problem); b) the data backup to the SSD is invited by the internal backup control unit; c) the internal backup control unit sends an invitation to the internal backup device to immediately back up the data; d) monitors the backup and internal backup control of the SSD The status of the department; e) Report the status of the internal backup control unit and end the operation. 3. Provide improved recovery by completing the following: a) The control department decides whether to restore or not (the user invites the command or the status monitor to determine the power problem); b) invites the data recovery to the SSD by the internal backup control unit; c) the internal backup control unit sends an invitation to the internal backup device to recover Data; d) Monitor the recovery of the SSD and the status of the internal backup control unit; e) Report the status of the internal backup control unit and end the operation. _ The figure shows a schematic diagram of the structure of the SSD 100. As shown in Figure 2, : ', Ma speed SSDl〇〇 structure schematic diagram. As shown in the figure = film section, including: the interface of the host interface called this can be a picture = _ interface as shown in the figure; should ^ (four) 3Q2, and the Ministry of Health · 201250575 connection · ' ECC controller 304 ; and memory controller 3 〇 6 , control one or more blocks 6 〇 4 of the memory 602 used as a high-speed storage device. Figure 3 is a switch-based hybrid storage system of the present invention FIG. 4 is a schematic diagram of the RAID controller of FIG. 3. As shown in FIG. 3 to FIG. 4, the access/component is of course of the PCI-Express type. The system of the present invention includes the switch 140A-N and the RAID. Controller 108A-N The system control board 1〇6. One or both sides of the RAH) controller 〇8〇 can be directly coupled to the system control board 106. In this way, the RAID controller 108A-B can be used for PCI-E based PCI_E of the RAID controller, and one of them can be PCI-E for SAS/SATA-based RAID controller. In either case, the system control board is integrated with the power supply unit 118. In addition, as shown in the figure, The DDR SSD module 11 can be combined on one or two RAID controllers 8A_B, and the DDR SSD module 110 is coupled to the RAID controller 108A. In general, DDR SSD module 110 includes a set of DDR SSD (memory) components 122A-N. As shown, the battery module 120 can be coupled to the DDRSSD module 11A. As shown, system control board 106 includes a first die 132A (e.g., 'IOH) coupled to first processor i30A (e.g., IntdXen〇n)
Quad-Core 5520系列）；第二晶片132B (例如，IOH)，結合於 第二處理器 130N (例如，Intel Xenon Quad-Core 5520 系列）； 及第三晶片132NC例如，ICH10R)，結合於第一晶片i32A。， 而且，DDR34記憶體部U8A-N可結合於一個或兩側處理器 130A_N。另外’在如圖所示的系統控制板1〇6中，提供結合 於第二晶片132N的I/O適配器/介面134及外部裝置136 (例 如’卡等）。雖然未圖示，但晶片132A-B可包括MultiPCI-E 201250575Quad-Core 5520 series); second chip 132B (eg, IOH), coupled to second processor 130N (eg, Intel Xenon Quad-Core 5520 series); and third chip 132NC (eg, ICH10R), combined with first Wafer i32A. Moreover, the DDR34 memory portion U8A-N can be coupled to one or both sides of the processor 130A_N. Further, in the system control board 1〇6 as shown, an I/O adapter/interface 134 and an external device 136 (e.g., 'cards, etc.) incorporated in the second wafer 132N are provided. Although not shown, the wafers 132A-B may include MultiPCI-E 201250575
Gen2xl6interconnect。開關140A上結合至少一個（（例如， PCI-E及/或SAS/SATA) RAID控制器i〇8C-N，而其結合於 HDD模組112。一般而言’ HDD模組112包括一套HDD/快 閃記憶體SDD(記憶體）部件124A-N。一般而言，在開關i4〇N 上結合包括一套槔126A-N的通信模組1〇4。 下面，結合圖4對RAID控制器108A-N進行更詳細的說 明。如圖所示，RAID控制器108A-N，包括：RAID控制器 CPU802 ;晶片804 ’結合於RAID控制器CPU802 ;及一套輸 入/輸出（I/O)連接器806A-N (MOLEX)，結合於晶片8〇4。 另外，同位元及緩存控制模組808可結合於rah)控制器 CPU802，而電池模組81 〇可結合於同位元及緩存控制模組 808。另外’如圖所示，記憶體模組812A_N可結合於 控制器CPU802。 又如圖1所示’辅助電源部4〇〇可由可再充的電池等哦古 城’通常利用通過介面部200從主機傳遞的電力進行充電以維 持—定的電力，而且’根據電源控制部5〇〇的控制將充電的電 力供應至電源控制部5〇〇。 電源控制部500將通過介面部2〇〇從主機傳遞的電力供應 至控制部300、記憶體磁片部1〇〇、備份保存部600及備份控 制部700。 t. 另外在通過介面部2〇〇從主機傳遞的電力中斷，或因從 為傳遞的電力超出閾值而導致主機電源錯誤時，電源控制部 5〇〇從輔助電源部働接收電力並將此電力通過控制部 300供 應至記憶體磁片部100。 12 201250575 備份保存部600由硬碟等低速揮發性存儲裝置 存記憶體磁片部觸的資料。 存儲裝置構成並保 控制°卩控制備份保存部_的資料登錄/輸出， 以將保存於記憶體磁片部觸的資料備份於備份保存部_， 根據來自主機的指示或翻從主機傳遞的電力超出間值 導致主機電源錯誤時，將保存於記憶體磁片部1〇〇的資料 份於備份保存部600。 本發明在it過PCI_Exp職介面在域和記龍磁片之間 進行資料通信的過程中，辭在主機和記髓磁片之間發送/ 接收的資料錢，從而在支援主機的低速資料處理速度_ 時’四支援記憶體磁片的告訴資料處理速度，以在現有技術的介 面環境中支援記憶體性能以最大限度地進行高速資料處理。 上述實施例僅用以說明本發明而非限制，本領域的普通技 術人員應當理解，可以對本發鴨行修改、變形或者等同替 換。而不脫離本發_精神和範圍，其均應涵蓋在本發明的權 利要求範圍當中。 【圖式簡單說明】 圖1為本發明以實施例的PCI-Express (PCI-e)類型的 RAID控制型存儲裝置結構概略示意圖； 圖2為結合於一套SSD的rah)控制器具體示意圖·， 圖3為本發明一實施例的基於開關的混合存儲農置系統 概略示意圖； 圖4為本發明一實施例的如圖3所示的RAID控制器示音 圖。 13 201250575 【主要元件符號說明】 100 : SSD (記憶體磁片部） 102 :中平面 104 :通信模組 106 :控制板 108A-N : RAID 控制器 110 : DDRSSD控制模組 112A-N : HDD 模組 114:風扇模組 118 :電源供應部 120 :電池模組 122A-N : DDRSSD 部件 124A-N : HDD/快閃記憶體SSD部件 126A-N :埠 130A-N :第N處理器 132A-N:第N晶片 134 : I/O適配器/介面 136 :外部裝置 138A-N : DDR34記憶體部 141A-N :開關 200、202 :介面部 300 :控制部 302 ·· DMA控制器 304 : ECC控制器 306 :記憶體控制器 400 :輔助電源部 500 :電源控制部 600A :備份保存部 600B :資料備份部 602 :記憶體 604 :記憶體區塊 700 :備份控制部 ^ ' 1 800 : RAID控制器 802 : RAID 控制 CPU 808 ·晶片 806A-N :輸入/輸出連接器 808 :同位元及緩存控制模組 810 :電池模組 812A-N :記憶體模組 900 :狀態監視器 14Gen2xl6interconnect. The switch 140A incorporates at least one (eg, PCI-E and/or SAS/SATA) RAID controller i〇8C-N, which is coupled to the HDD module 112. In general, the HDD module 112 includes a set of HDDs. /Flash memory SDD (memory) components 124A-N. In general, a communication module 1〇4 including a set of 槔126A-N is combined on the switch i4〇N. Next, the RAID controller is combined with FIG. 108A-N is described in more detail. As shown, the RAID controllers 108A-N include: a RAID controller CPU 802; the chip 804' is coupled to the RAID controller CPU 802; and a set of input/output (I/O) connections The 806A-N (MOLEX) is coupled to the chip 8〇4. In addition, the parity and cache control module 808 can be coupled to the rah) controller CPU 802, and the battery module 81 can be coupled to the parity and cache control module. 808. Further, as shown, the memory module 812A_N can be coupled to the controller CPU 802. Further, as shown in FIG. 1, the 'auxiliary power supply unit 4' can be charged by the power transmitted from the host through the dielectric unit 200, such as a rechargeable battery, etc., and is maintained in accordance with the power supply control unit 5 The control of 〇〇 supplies the charged power to the power supply control unit 5〇〇. The power supply control unit 500 supplies the power transmitted from the host through the interface 2 to the control unit 300, the memory disk unit 1A, the backup storage unit 600, and the backup control unit 700. t. In addition, when the power transmitted from the host through the interface 2 is interrupted, or the host power supply error occurs due to the power exceeding the threshold for the transmitted power, the power supply control unit 5 receives power from the auxiliary power unit 并将 and the power The control unit 300 supplies the magnetic disk unit 100 to the memory. 12 201250575 The backup storage unit 600 stores data touched by the memory disk unit from a low-speed volatile storage device such as a hard disk. The storage device is configured to control the data registration/output of the backup storage unit _ to back up the data stored in the memory disk portion to the backup storage unit _, according to instructions from the host or to transfer power from the host When the excess value causes the host power supply error, the data portion stored in the memory disk unit 1 is stored in the backup storage unit 600. In the process of data communication between the domain and the Kelon magnetic disk, the present invention resigns the data sent/received between the host and the memory disk, thereby supporting the low-speed data processing speed of the host. _ 'four support memory disk tells the data processing speed to support memory performance in the prior art interface environment to maximize high-speed data processing. The above-described embodiments are only intended to illustrate the invention, and are not intended to be limiting, and those skilled in the art will understand that modifications, variations, or equivalents may be substituted. It is intended to be included within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing the structure of a PCI-Express (PCI-e) type RAID-controlled storage device according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a rah) controller combined with a set of SSDs. FIG. 3 is a schematic diagram of a switch-based hybrid storage farm system according to an embodiment of the present invention; FIG. 4 is a schematic diagram of a RAID controller shown in FIG. 3 according to an embodiment of the invention. 13 201250575 [Description of main component symbols] 100 : SSD (memory disk section) 102 : midplane 104 : communication module 106 : control board 108A-N : RAID controller 110 : DDRSSD control module 112A-N : HDD mode Group 114: Fan Module 118: Power Supply Unit 120: Battery Module 122A-N: DDRSSD Parts 124A-N: HDD/Flash Memory SSD Parts 126A-N: 埠130A-N: Nth Processor 132A-N : Nth wafer 134 : I/O adapter / interface 136 : External device 138A - N : DDR34 memory portion 141A - N : Switch 200 , 202 : Dielectric face 300 : Control unit 302 · · DMA controller 304 : ECC controller 306 : Memory controller 400 : Auxiliary power supply unit 500 : Power supply control unit 600A : Backup storage unit 600B : Data backup unit 602 : Memory 604 : Memory block 700 : Backup control unit ^ 1 800 : RAID controller 802 : RAID Control CPU 808 · Wafer 806A-N : Input/Output Connector 808 : E-cell and Cache Control Module 810 : Battery Module 812A-N : Memory Module 900 : Status Monitor 14