TW201241929A - Thin film transistor and method for fabricating the same - Google Patents

Abstract

A method of fabricating a thin film transistor (TFT) and a TFT are provided. In the method, a gate is formed on a substrate. A gate insulation layer is formed on the substrate to cover the gate. An oxide semiconductor layer is formed on the gate insulation layer which is above the gate. An etching stopper is formed on the oxide semiconductor layer. A source and a drain electrically isolated from each other are formed at two sides of the etching stopper and expose a part of the oxide semiconductor layer disposed at two sides of the etching stopper. A protection layer is formed to cover the source and the drain. The oxide semiconductor layer exposed by the source and the drain are transformed into two ohmic contact layers during the protection layer forming process. The two ohmic contact layers are electrically connected to the source and the drain respectively.

Description

201241929

H /uuiiW 36985twf.docA VI. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly to a thin film transistor having an oxide semiconductor layer and its manufacture method. [Prior Art] Recently, liquid crystal display panels with superior power consumption, high space utilization efficiency, no radiation, and high image quality have become mainstream in the market. In the past, liquid crystal display panels have mostly used amorphous 矽0_&) thin film dielectrics or low-temperature polysilicon (LTPS) thin film transistors as switching elements for individual halogen structures. However, in recent years, studies have indicated that oxide semiconductor thin film transistors have higher carrier mobility than amorphous germanium thin film transistors; and, compared to low temperature polycrystalline thin films The transistor 'oxide semiconductor thin film transistor has a better threshold voltage (Vth) uniformity. Therefore, oxide semiconductor thin film transistors have the potential to become key components of next-generation flat panel displays. In general, the manufacturing process of an oxide semiconductor thin film transistor generally uses a five-mask process. First, a gate is formed on the substrate using the first mask process. Then, a gate insulating layer is formed on the substrate in a comprehensive manner to cover the gate. Next, an oxide semiconductor layer is formed on the gate insulating layer above the gate using a second mask process. Then, use the third mask 4 201241929

117013ITW 36985twf.doc/I = absolute shatter layer. Then, the 介^+ conductor layer and the engraved blocking layer are formed with a "Thunder:==:=:rtr semiconductor layer on the hydrogen ohmic contact layer." The shape s conductor phase transistor is complicated in production process, and the manufacturing cost is complicated. high. SUMMARY OF THE INVENTION The present invention provides a method for producing a thin film transistor, a process for fabricating the transistor, and a reduction in manufacturing cost. Low-cost invention city provides a thin film transistor, which has a simple process and is manufactured by the invention. A gate insulating layer is formed on the substrate on the substrate to cover the gate. On the gate ‘ === the semiconductor layer. In the oxide core = : source and dipole and semi-conductive layer. Forming a protective layer covering == material:: layer: = medium, the source and the drain exposed by the deuterium and 汲 2 electricity: even the i layer 'ohmic contact layer respectively and the source 201241929

U/UlJliW 36985twf.doc/I Outer Cover" provides a thin film transistor including: interpole, interlayer insulating layer, step-conducting layer, layer, smoke-resistant lion, source and city. Open insulation Γ J St. The oxide semiconductor layer is placed on the interlayer insulating layer above the gate. The outer conductor layer includes a two-ohm contact layer. Button engraved layer configuration 2 female 丨 n body layer. The source and the drain are electrically insulated from each other and are disposed on both sides of the blocking layer. The source and the secret expose the = electrical contact layer of the resistive layer and the ohmic contact layer and the source-pole respectively :::: _ real; = said: the pole has the first,,, then, the first, and the second open:; === side of the ohmic contact layer. </ RTI> The two methods of the layer form a two ohmic contact layer on the oxide half or before forming the protective layer. In one embodiment of the doping, ί:?: the hydrogen doping comprises ~ extending to the source and not The underlying impurity is formed by the impurity in the oxide semiconductor layer in the embodiment of the present invention. In the embodiment of the present invention, the upper method can further include the formation of the contact layer in the protective layer. The window is open, and the square mouth is exposed. The contact window is opened in the embodiment of the present invention, the upper method may further include forming a pixel 2 on the π substrate; and the manufacturing side is electrically connected via the contact opening of the window of the 201241929 117013ITW 36985 twf.doc/I Go to the bungee. In an embodiment of the invention, the above method of forming a protective layer comprises: plasma assisted chemical vapor deposition. In an embodiment of the invention, the gas used in the plasma-assisted chemical vapor deposition method is selected from the group consisting of tetrahydrogen hydride (SiH4), nitrous oxide (0), helium (He), and hydrogen hydride (NH3). ), hydrogen (h2), nitrogen (n2), and combinations thereof. In an embodiment of the invention, the material of the oxide semiconductor layer is selected from the group consisting of: indium gallium zinc oxide (IGZ0), indium zinc oxide (IZ〇), indium gallium oxide (IGO), and tin oxide (Zn0). In the embodiment of the invention, the forming the gate on the substrate further comprises: on the substrate A sweeping scale is formed on the scan line, and the scan line is electrically connected to the gate electrode. The source and the cathode are formed on the substrate in the (4)-actual wipes of the substrate, and the data line is formed on the substrate. The fourth embodiment is characterized in that the shape of the first opening and the second opening includes a square shape, a circular shape or a comb shape. The spoon is included in an embodiment of the above-mentioned thin film transistor. The protective layer covers the source, the θ layer has a contact opening, the contact opening of the contact window is exposed, and the electrode is included. The film transistor including the above-mentioned thin film transistor can be further rounded. Prime electrode __ window opening and electrically connected to 201241929

— — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — At the same time, the exposed oxide semiconductor of the present invention has a two-ohmic contact layer, which simplifies the above features and advantages. The above features and advantages can be more clearly understood. The drawings are described in detail below. [Embodiment] [First Embodiment] [Manufacturing method of thin film transistor j] Fig. 1A to Fig. 1A are schematic top views of a thin film transistor manufacturing process of a first embodiment of the present invention. 2A to 2B are cross-sectional side views showing the manufacturing process of the transistor according to the line Α-Α' of Figs. Referring to FIG. 1A and FIG. 1 , first, when the gate electrode G is formed on the substrate 1 〇 2, the scan line SL is formed on the substrate, and the scan line SL is electrically connected. To the gate G. The material of the substrate 102 is, for example, glass, quartz, an organic polymer, an opaque/reflective material (e.g., a conductive material, a wafer, a ceramic, etc.) or other suitable material. The material of the gate G and the sweep line SL can be made of a metal material (such as Ding, M〇, A1) alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, and the like. G and scan line sl may be a single film layer or a composite stacked film layer. The gate G and the scan line SL can be fabricated by sputtering in general 8 201241929

117013ITW 36985twf, doc / I film, with lithography money ^ ^ + film and other steps), and the shape is photoresist coating, lithography, _, stripping detailed. The pattern of the gate G and the scanning line SL is not described here with reference to Fig. 1B and the circle + edge layer ship cover trB, and a chemical vapor deposition method is formed on the substrate 1〇2. The method of insulating the insulating layer 104 may be, for example, a gas oxygen cutting or a combination of at least two materials of the above materials or a combination of an organic and inorganic dielectric material, but is not limited thereto. Referring to Figure 1C and the m-layer ΗΜ, an oxidized open insulating material is formed. More sleeved, the formation of oxygen blanket mineral film, the gas used in the splash bond method (2) 虱 (Ar), wherein the oxygen flow rate can be between 5~50 standard cubic meters / minute, and argon The flow rate may be between 20 and 50 standard cubic centimeters / then 'for the side process of the oxide semiconductor material layer, and the partial gate insulating layer 104 above the gate G is shaped with 1C and the oxide semiconductor layer shown in FIG. 2C. Reward pattern. The material of the oxide semiconductor layer 106 is selected from the group consisting of: oxidized marriage (IGZ〇), oxidized zinc ((4)), indium gallium oxide (IG0), tin oxide (Zn〇), oxidation recorded, and oxidation recorded (2Cd0' Ge02), nickel nickel oxide (Nic〇2〇4) and combinations thereof. Referring to FIG. 1D and FIG. 2D, an etching stopper layer 108 is formed on the oxide semiconductor layer 1A6. The etch stop layer 1 覆盖 8 covers the oxide semiconductor layer 106 of a portion of the region to protect the underlying oxide semiconductor layer 106 from semiconductor characteristics after subsequent processes (which can be used as a follow-up

1W 36985tw£d〇c/I 201241929 channel layer) _ _ resist layer 108 can be U 蒦 layer. _ and the production layer 1G8 is made, for example:

And the material layer, and then, the _ road-two pure engraving process, to obtain the material of FIG. 1D and FIG. 2D to be the dioxin barrier layer 108 can be laterally opened and FIG. 2E, and then, in the (four) barrier layer (10) Two warm coffee 屮 1 纟 insulation source S and secret D, source S and immersion D + way out of the two layers (10) of the etch barrier layer 〇8. In this embodiment, the source s can be made with =_^== ^ D H2, ^ , 1D H1 ^ ^;;;; ^ f side _ layer should be part of the (four) oxide semiconductor layer: shape: Figure 2E As shown, the first opening m and the second opening buckle 2 are, for example, rectangular. However, in other embodiments t, the shape of the first opening H1 and the opening H2 may be circular, comb-shaped, polygonal or combined. A palatable shape. In addition, the number of openings may be determined according to the design, and is not limited to the one of the second opening Η2, the first opening H1 or the opening (not shown), which is not limited to FIG. 1E and FIG. When the source s and the drain d are formed on the substrate 102, the data line DL is formed on the source and the data line dl is electrically connected to the source s. . Source s, bungee D and data, such as w alloy 'metal == gold: oxides of genus materials, nitrogen oxides of metal materials, etc., 201241929 117013IT W 36985twf.doc/1 pole D and data line sink can be single _ 骐 layer or composite stacked film layer. The source S, the drain D and the data line DL can be formed by a general tantalum film formation, with a lithography process (ie, a step of etching, stripping, etc.), and opening 忐, β ’,

The pattern, the original # S, and the pole D and the data line DL pole are not detailed here: in the above process steps 1E and (4), in the process step, the first opening Hi is formed together with the source port η. With the first opening Η2, no additional process is required. Referring to FIG. 1F and FIG. 2F, the squeezing, the pole S and the immersion D are used to form a protective layer 110 covering the source.

Simultaneously with the oxide exposed by the electrode D, the source S touch 106a, the ιπακ# material + the conductor layer 丨〇6 are formed into two ohmic junctions and the immersion D electrically connected two ohmic contact layer, The part of the leg corresponding to the source port H2 丄S: the second port: 1 7 and the second opening material of the pole D can be = t: r such as contact nitrogen = one of the above at least - species = (11 # ^ cut, oxygen cut , a layer of oxynitride or a stack of iltl, an organic material or a combination of the above. In addition, in the shape of the "protection layer 1G6a, 1G61 ^ method package for the oxide semiconductor layer before the formation of the protective layer 110" semiconductor 106 open / Λ 1 row 虱 doping, and make part of the oxide ^position , PECVD ν&quot;Ρ〇Γ 札体疋 is selected from Sihua fossil (SiH4), nitrous oxide 11

201241929 n/uunW 36985twf.docA (ΝΑ), helium (He), hydrogenation gas (NH3), hydrogen (H2), nitrogen (N2), and combinations thereof. Therefore, when the protective layer 110 is formed, part of the oxide semiconductor layer 106 (such as indium gallium zinc oxide (IGZO)) is exposed to the electropolymerization of hydrogen ions, and is doped with hydrogen ions, thereby converting into conductive Characteristic material (ie ohmic contact layers 106a, 106b). In the plasma-assisted chemical vapor deposition method described above, the flow rate of tetrahydrogen (SiH4) may be, for example, between 5 and 10 standard cubic centimeters per minute, and the flow rate of dinitrogen oxide (NaO) may be Between 5〇〇~1〇〇〇 standard cubic centimeters/minute, the flow rate of helium (He) can be between ι〇〇〇15〇〇 standard cubic centimeters/minute 'annealing temperature can be introduced Between 2〇〇〇c~5〇〇〇c. It is worth mentioning that 'please refer to FIG. 1F, the above hydrogen doping includes cross-doping, and the doped region R formed in the oxide semiconductor layer 1〇6 via hydrogen doping extends to the source s Below the bungee D. In other words, except for the portion 骞 106 exposed by the first opening H1 and the second opening H2, which is doped with hydrogen ions, the oxide semiconductor layers of the first opening m and the second opening resistance are also hydrogen ions. Doping, that is, the contact layer and the secret layer of the contact are extended to the source s and the drain d: and the source S and the drain D are in good electrical contact. And has excellent electrical characteristics to form a phase transistor _, please refer to Figure 1G and Figure 2G, then 'can also be made into contact window opening II, contact window opening | &amp; 9-shaped window opening H exposure road out of the pole D . The method of forming the contact Η is, for example, a general lithography process, which is not referred to herein with reference to Fig. 1 and Fig. Μ, and then can be formed on the substrate 1 〇 2 201241929

117013ITW 36985twf.docA The halogen electrode 112, the halogen electrode 112 is electrically connected to the drain D through the contact opening H. The halogen electrode U2 is, for example, a transparent conductive layer, and the material may be a metal oxide such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide, or other suitable oxide. Or a stacked layer of at least two of the above. The pixel electrode 112 can be formed by a general sputtering film formation process and a lithography process (ie, photoresist coating, lithography, etching, film stripping, etc.) to form a pattern of the halogen electrode 112. Will not be detailed. Thus far, the thin film transistor 1 and the pixel electrode 112 can constitute a pixel structure PIXEL for displaying image data. The method for manufacturing the thin film transistor 100 is formed by exposing the source s and the drain D to expose the oxide semiconductor layer 106 on both sides of the etch barrier layer 〇8 so as to be exposed to the source S and the immersion D. The oxide semiconductor layer 106 can be formed into two ohmic contact layers 10a, 6b, 6b while forming the protective layer 11?, which simplifies the fabrication process of the thin film transistor 1[Fig. 2F A schematic cross-sectional view of a thin film transistor of the first embodiment of the invention. Referring to FIG. 2F, the thin film transistor 1 〇〇 includes: a gate 〇, a gate insulating oxide semiconductor layer 1 〇 6 , a surname blocking layer 1 〇 8 , a source s and a; and a drain D gate insulating layer 104 covers the gate Extremely G. The oxide semiconductor layer is disposed on the gate insulating layer 104 above the gate G, and the oxide semiconductor layer 1 〇 6 is wrapped, and the two ohmic contact layers 1 〇 6a and 16b. The material of the oxide semiconductor layer 1〇6 is selected from the group consisting of: indium gallium zinc oxide (IGZ〇), indium zinc oxide (IZ〇), indium oxide (IG〇), tin oxide (ZnO), cadmium oxide, cerium oxide. (2Cd0.Ge02), 13

201241929 117013ITW 36985twf. doc/I Nickel oxide cobalt (NiCo204) and combinations thereof. The button barrier layer 108 is disposed on the oxide semiconductor layer. The source S and the gate D are electrically insulated from each other and disposed on both sides of the barrier layer 1〇8, and the source S and the drain D expose an oxide semiconductor located on both sides of the etching stopper layer 1〇8. The layer 106 and the ohmic contact layers 1〇6a and 1〇6b are electrically connected to the source S and the drain D, respectively. In detail, the source S has a first opening hi, and the drain d has a second opening H2'. The first opening H1 and the second opening H2 are respectively located on both sides of the engraving barrier layer 108, and the source and the drain D are The ohmic contact layers on both sides of the ifj (four) barrier layer (10) are exposed through the first opening hi and the second opening H2, respectively, K) 6b. The shape of the first opening H1 and the second opening H2 is, for example, a rectangle. However, in other embodiments, the shapes of the first opening σ m and the second opening m may also be circular, comb-shaped or polygonal, or open and open. The number can vary depending on the design needs. The kidney film 1 〇0 can further include protection ijs 0 UG covering the source 8, the secret D and the oxide semiconductor, wherein the protective layer 110 has a contact window open, contact =, road exit bungee D. In addition, the thin film transistor may further be S3, and the electrode 112 1 electrode 112 is electrically used to turn over the opening H through the contact window opening H. The thin film transistor 100 and the halogen electrode 112 can constitute a quinone structure piXEL which does not have image data. The above-mentioned thin film electrode has a simple structure and a low manufacturing cost. [First Embodiment] [Manufacturing method of thin film electric crystal boat] 201241929

117013ITW 36985twf.doc/I The manufacturing process of the thin film transistor of the present embodiment is similar to the manufacturing process of the thin film transistor of the first embodiment, that is, after forming the source and the drain, and after forming the protective layer, In the following, only the steps of forming the source and the drain and forming the protective layer to describe the manufacturing process of the thin film transistor of the present embodiment will not be repeated. 3A to 3B are top plan views showing a part of a manufacturing process of a thin film transistor according to a second embodiment of the present invention. 4A to 4B are schematic cross-sectional views showing a part of the manufacturing process of the thin film transistor according to the line A-A of Figs. 3A to 3B. Referring to FIG. 3A and FIG. 4A, a source s and a drain D electrically insulated from each other are formed on both sides of the etch barrier layer 108, and the source s and the drain D are exposed on portions of both sides of the etch barrier layer 108. The oxide semiconductor layer 106. The difference from the first embodiment is that the source s and the drain D of the present embodiment cover only the oxide semiconductor layer 106' located on both sides of the etch barrier layer 〇8 to expose the oxide semiconductor layer ι Both ends of 6. Next, referring to FIG. 3B and FIG. 4B, the protective layer 11 is formed to cover the source S and the gate D, and the oxide semiconductor exposed at the source and the drain D simultaneously in the process of forming the protective layer 11? The layer 1G6 is formed as a two-ohmic contact layer 106a, wherein the ohmic contact layer is electrically connected to the gate electrode S. The position where the ohmic contact layers 1〇6a and 1〇6b are formed in the present embodiment is the same as that described in the fourth embodiment, and will not be repeated here. 15

201241929 117013ITW 369 85twf.doc/I

[Thin Film Transistor] Referring to FIG. 4B, the thin film transistor i〇〇a is similar to the thin film transistor 100 of the first embodiment, except that the source S, the drain D and the ohmic contact layers 106a, 106b of the present embodiment The formed position is slightly different from the source s, the gate D and the ohmic contact layers 1〇6a, 1〇6b of the first embodiment. The source S and the drain D of the present embodiment cover only the oxide semiconductor layer 106 located on both sides of the etching stopper layer 1〇8, and expose both ends of the oxide semiconductor layer 1〇6. The ohmic contact layers 106a, 106b are respectively located at both ends of the oxide semiconductor layer 106. 2 is a schematic cross-sectional view showing a structure of a thin film transistor having a second embodiment of the present invention. Referring to FIG. 4C, the film transistor 100A and the second electrode 112 constitute a charge and discharge of the pixel structure layer 4 of the pixel structure layer 4 for displaying image data, and may be performed by a thin film transistor having an oxide semiconductor layer (for example, 1GZ0). control. The thin film transistor of the present invention and the method for fabricating the same have at least a layer of dew (10) two layers of carbonaceous semiconductor conductor layers on the two sides of the barrier layer: the oxides exposed by the source and the dipole are semi-simple: Formed as a two-ohmic contact layer, and the laterally-growth-to-source extension and source-to-pole contact layer can be ensured to have good electrical characteristics with the source by good electrical contact with the drain. The thin film transistor may have the above disclosure as defined above to define any one of ordinary skill in the art without departing from the art.

201241929 117013ITW 36985twf.doc/I In the spirit and scope of the present invention, the scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. 1H are top views of a thin film transistor manufacturing process according to a first embodiment of the present invention. 2A to 2H are schematic cross-sectional views showing a manufacturing process of a thin film transistor according to the line A-A' of Figs. 1A to 1H. 3A to 3B are top plan views showing a part of the manufacturing process of the thin film transistor of the second embodiment of the present invention. 4A to 4B are schematic cross-sectional views showing a part of the manufacturing process of the thin film transistor according to the line A-A' of Figs. 3A to 3B. Fig. 4C is a schematic cross-sectional view showing a halogen structure of a thin film transistor having a second embodiment of the present invention. [Main component symbol description] 100, 100A: thin film transistor 102: substrate 104: gate insulating layer 106: oxide semiconductor layer 106a, 106b: ohmic contact layer 108: etching stopper 110: protective layer 112: pixel electrode 17

36985twf.docA 201241929

χ ί I yj 1 ^&gt;x x W D : bungee DL : data line G : gate H, HI, H2 : opening PIXEL, PIXEL A S : source SL : scan line

Claims (1)

201241929 117013ITW 36985twf.doc/I VII. Patent application scope: 1. The manufacturing method of the thin film transistor forms a gate on a substrate; Xuanzao. The insulating substrate is formed on the substrate. a gate is formed on the layer, and an oxide semiconductor is formed on the oxide semiconductor layer on both sides of the peak barrier layer; the germanium layer is etched; and the gate electrode, the Laiji and the Weiji彳^ Electrically insulating the portion of the oxide semiconductor layer on the source side. The two formation-protective layers located in the etch stop layer cover the source and simultaneously cause the source and the immersion; The protective layer is electrically connected to the drain. The contact layer is respectively associated with the source method, wherein the source has a -first-heart: an opening of the electrical-positive body, the first gate π is a pseudo-existing _ opening, and the drain has a second, .\ ^ The second openings are respectively located on the oxide semiconductor layers of the two opening-openings of the etching resistance and the portions of the second opening exposed to both sides.彳 彳 的 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. The thin-crystal method described in the section, the towel, the _ pole and the portion of the oxide semiconductor layer on both sides of the Wei. In the method of manufacturing the thin film transistor according to the first aspect of the invention, the method of forming the two ohmic contact layers includes: forming the protective layer simultaneously or before forming the protective layer, For 36985 twf.doc/I 201241929 &amp; Λ I Λ ^ Λ Λ The oxide semiconductor layer is subjected to a hydrogen doping. The method for manufacturing a thin film transistor according to the above, wherein the =-doped region formed in the layer ==;;:: ΐϊ 杂 包括 includes lateral doping, and the first patent range is the first The manufacture of the thin film transistor described in the above paragraph is further included in the protective layer to form a contact window opening, and the exposure is: the manufacture of a thin film transistor according to item 6 of the patent scope of the invention. Including forming a halogen element electrode on the secret plate, electrically connected to the drain through the window opening. According to 蜩, 8. For the method of manufacturing the thin-film transistor described in the second paragraph, the method of forming the nano-protective layer includes: assisting the chemical phase deposition method. 9. The method for producing a silicon oxide according to claim 8, wherein the gas used in the plasma-assisted chemical vapor deposition method is selected from the group consisting of tetrahydrogen tetroxide (SiH4) and nitrous oxide. (〇〇), 氦(He), hydrogen hydride (NH3), hydrogen (H2), nitrogen (N2), and combinations thereof. 10. The method for producing a thin film transistor according to claim 1, wherein the material of the oxide semiconductor layer is selected from the group consisting of: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), and indium oxide. Gallium (K50), tin oxide (Zn〇), cadmium oxide, cerium oxide (2Cd0.Ge〇2), nickel cobalt oxide (Nic〇2〇4), and combinations thereof. 11. The method of manufacturing a thin film transistor according to claim 1, wherein the forming the gate on the substrate further comprises: at 201241929 117013ITW 36985twf.doc/I inverse 2: Tian' line 'And the scan line is electrically connected to the gate. The method of manufacturing the thin film transistor according to the first item includes: while the source is opposite to the drain, the source Μι(10)' is electrically connected to the 13.-type thin film transistor, including: a gate a gate insulating layer covering the gate; the upper conductor layer 'disposed on the upper insulating layer of the germanium oxide semiconductor layer includes a two-ohmic contact layer; the last name resist layer is disposed on the oxide On the semiconductor layer; and the waste electrode and the ; and the poles are insulated from each other and disposed in the silver engraving resisting the gamma portion. The source and the drain are exposed to the two layers of the resistive layer. The surface of the germanium contacts the layer, and the layers are electrically connected to the source and the drain. In the film transistor of claim 13, wherein the film has a second opening, the first opening and the second opening are respectively Located on both sides of the side barrier, the second opening and the second opening expose the ohmic contact layers of the portion of the (4) layer of the new layer. The thin film transistor according to claim 14, wherein the opening and the shape of the second opening comprise a square shape, a circular shape or a comb shape. 2: The film transistor described in claim 13 of the &amp; The λ source and the ridge cover the oxide semiconductor layer of the portion of the etch barrier layer 21 36985 twf.doc/I 201241929. 17. The thin-layered protective layer as described in claim 13 covering the source, the secret, and the etch stop layer exposed by the drain; the dioxo: semiconductor layer, the towel The guarantee has a knife-free (four) oxide immersion. (4) having a contact (four) port, exposing the 18. The film of the invention, as described in the scope of the patent application, the opening of the window, and the electrical connection == 19', such as the thin film transistor according to claim 13 of the patent application scope, wherein the oxidation The material of the semiconductor layer is selected from the group consisting of indium gallium oxide in IGZO, indium zinc oxide (IZO), gallium arsenide (IG〇), tin oxide (Zn〇), cadmium oxide, and antimony oxide (2Cd0.Ge02). ), nickel oxide cobalt (NiC〇2〇4) and combinations thereof. twenty two