201240174 六、發明說明： 【發明所屬之技術領域】 本發明大體上係關於相變化記憶體元件，且特別係關 於形成採用碲化鍺銻（germanium antim〇ny teUuride)之 相變化記憶體元件的方法。 【先前技術】 相變化記憶體（PCM)係一種用於電腦應用的非揮發性 記憶體。在PCM中，硫族材料（通常為鍺銻碲合金（gst)) 的行為係藉由在材料的結晶相與無定形相間變化而改 變。熱阻器或任何其它適合元件經操作以加熱使硫族材 料產生相變化。結晶相與無定形相有不同的電阻率可 用來代表儲存資料用的二元碼。為減少誘發二相間變化 所需的功率，因此使用少量的GST。特別地，少量的 係限制在很小的溝槽、孔洞（通孔）或類似結構内。 然而，在製造用於電腦應用的PCM時，係使用化學氣 相沉積（CVD)或原子層沉積（ALD)所得之高度共形沉積 的GST來填充結構，以將GST限制在結構内。在—些製 造此PCM的方法中，即使採行1〇〇%共形之製程仍會 形成接縫（當GST臈與側壁接合時所產生的界面接縫 處通常不會有過密聚集的GST，故經循環（高、低溫交替 促使材料於無定形相與結晶相間變化）後，該接縫處會在 GST中變成孔隙。孔隙往往會造成採用PCM之元件的早 201240174 發性可靠度失效’可靠度失效通常係耐久性短或資料保 持力低的表徵。 在其匕方法中，pCM晶胞係利用交又間隔物製造。在 採用交又間隔物的至少一方法中，將氮化鈕（TaN)沉積於 杯狀、纟°構内，接著填入低溫氧化物（LTO)。接著使用化學 機械研磨（CMP)製程以暴露出TaN的上緣。將低溫氮化 物（LTN)/儿積在部分上緣上，上緣為與鈦鎢（丁丨貿)層 且TiW位於頂部而構成上電極。gst間隔物隨後沉積在 堆疊之LTO與TiW和LTN旁做為相變化材料，且以LT〇 來塗覆杯狀結構。沉積鋁/TaN内連線，且該鋁/TaN内連 線經由杯狀結構底部接觸Tiw而增設下電極。在此方法 中，GST係以複雜的遮蔽程序圖案化，且gST沿著垂直 邊緣接觸上電極，故其難以按比例縮放因而大幅增加 方法的成本。 在其匕形成PCM元件的方法中，係以壁面代替通常將 GST限帝J其内的溝槽結構。冑用壁面容許相變化材料 (GST或其它硫族材料）利用流程而沉積至鄰接壁面的平 —表面上。然而’在此方法中，相變化材料不像採用溝 槽之PCM元件般經適當限制。故此簡元件的性能和 縮放性比相變化材料沉積於溝槽之pcM元件差。 是以需要形成PCM元件結構的方法，其可適當限制相 變化材料’又不會併入有損元件完整性的接縫。 【發明内容】 201240174 本發明係關於相變化記憶體元件和其製造方法。 在-態樣令，本發明係關於相變化記憶體元件，立包 含基板、置於基板之第一和第二表面上的材料、位二第 -表面之材料内的上電極、位於第二表面之材料内的至 少-下電極、以及位於基板中且連接上電極與下電極的 至少一平板結構。基板之第—和第二表面上的材料為低 溫氧化物和低溫氣化物的至少其一。平板結構係實質無 縫又實質無孔的相變化材料結構。 在另一態樣中，本發明係關於形成相變化記憶體元件 的方法。在此方法中，提供具第一表面和相對之第二表 面的基板。溝槽形成於第—表面，且—或多個下電極位 於第二表面且連接溝槽。相變化材料沉積於溝槽内。介 電保護層與填充層/亦沉積於溝槽内’ i電極m沉積於第 一表面，並透過相變化材料所形成之内連線維持與下電 極間的連接。 在又一態樣中，本發明亦關於形.成相變化記憶體元件 的方法。在此方法中，提供具頂層和底層之基板，且溝 槽形成於頂層中。至少一下電極形成於底層中。相變化 材料沉積於溝槽内且連接至少一下電極。介電保護層沉 積於相變化材料上，且填充層沉積於介電保護層上。接 著’上電極沉積在頂層上且連接相變化材料。上電極與 下電極間透過相變化材料所形成之内連線維持電氣連 接。 本發明之其它態樣、特徵和實施例在參閱實施方式說 201240174 明和後附申請專利範圍後，將變得更清楚易懂。 【實施方式】 以下顯示本發明之方法所形成的PCM元件。pcM元 件包含由相變化材料所連接的上、下電極。介電材料用 於隔離上、下電極及隔離相變化材料。 參照第1圖，在形成PCM元件的第一步驟中，溝槽 1〇形成於基板12中。如圖所示，基板12包含彼此接合 設置之頂層14和底層16〇頂層14包含二氧化矽（si〇小或 其它LTO)、氮化梦（SiN)(或其它⑽）、< 前述材料之組 合物做為介電質，以提供絕緣性質。底層16包含相同或 類似材料，且底層16的組成可不同於頂I 14的組成。 然而，基板12不限於包含頂層14和底層16，基板亦可 為包含一或多層Si〇2和SiN的單一構件。 下電極20位於基板12之底$ 16巾，如此在位置μ 處’溝槽H)之相對壁面22的下緣將連接下電極2〇的表 面。每-個下電極20的寬度為f，且彼此相隔寬度f。 每一個下電極20的長度（即下電極中垂直於寬度的維度） 為任何預期長度。故在PCM元件中，下電極2〇朝三個 維度延伸而具有任何預期構造。底層16亦配置以包括任 何適合形貌，以容納下電極2〇設置於内。雖然下電極 2〇係綠示具有有角構造，但本發明不限於此，下電極也 可呈圓柱形。製造下電極2〇的材料包括，但不限制為， 201240174 氮化鈦銘（TiAIN)、氮化鈦鎢（TiNW)、前述材料之組合物 等。 為形成溝槽10，將微影遮罩放置在頂層14上，且使 用蝕刻製程（如使用濕式蝕刻化學）來形成溝槽。溝槽1〇 的寬度為2f。溝槽的長度（即溝槽尺寸中垂直寬度的維度） 亦為2 f。 現參照帛2圖，在形成pCM元件的第二步驟中，相變 化材料沉積在基板12之頂層14和至少部分界定溝槽1() 之壁面與底表面上。利用把相變化材料分配成均勻厚度 且盡可能共形的技術來沉積相變化材# 30。此技術包 括，但不限制為，CVD、數位CVD、脈衝式⑽、金屬 氧化物CVD和ALD。此技術的變化例亦^在本文所述方 法的保護範圍内。相變化材料3〇以下稱為GST 30’然 所逃方法不限於此，也可使用其它相變化材料。例如， 相變化材料30可為銼、你赵 Α 鍺鍺銻、碲化鍺、碲化銻、或其任 何組σ物。在沉絲^ 時，鍺（Ge)與銻（Sb)和碲（Te) 的比例（原子可為約2 : 2 . Η 等。在 、·，、 . 1 : 5、約 30: 15 ·· 周早。/，ςκ為2·2.5的實施例中，Ge為約20至25 、。 為約20至25原子％，T炎 %。在比例為4.,.原'子Te為約50至60原子 子0/，Sb A 」的實施例中’ Ge為約40至45原 子sb為約5至1〇 .^ 0 、千 / Te 為約 50 至 55 原子0/〇。 在比例為30 : 15 : 5 早〇/，Sh太从 實施例中’ Ge為約27至33原 子/〇’ Sb為約15 現灸昭h 原子％’Te為約50至60原子％。 現少，，、、第3圖，士1田…丄 疋向電衆餘刻製程（間隔物蝕刻製 201240174 程），選擇性移除頂層14之頂表面的GST3(^接著利用 一樣較向電㈣刻製程，移除溝槽1〇底部的GST30。 在定向電㈣刻製財，移除橫向膜（在此例巾為GST )隨著成移除溝槽1〇底表面之GST 3〇及選擇性移 除頂層14的頂表面之GST3G後，GST留在溝槽側壁上， 而形成實質無縫且實質不含孔隙的GST材料平板。由於 平板係以沉積製程沉積，故其尺寸（如冑 不受採用之料沉積製程支配1而，方法和元件不受 此限GST 30也可選擇性鋪設於側壁而不鋪設於溝槽底 表面’如此可免除移除溝槽底表面之GST的步驟。在定 向電毁餘刻製程不完全移除頂層Μ之GST 3G的實施例 中，可利用CMP製程移除頂層的殘留咖。 在第4圖所示之第四步驟中，將材料實質共形沉積於 頂層14之頂表面以及GST覆蓋之側壁和溝槽ι〇之底表 面上，以形成介電保制34。用於形成介電保護層Μ 的材料為SiN。然而，材料不限於㈣，任何其它不與 GST反應的材料也可使用。形成介電保護層34的_係 利用任何適合之沉積技術，在低於約45〇〇c之溫度下， 實質共形沉積在頂層1 4和側壁上。 又在第四步驟中，包含桃及，或_的填充層刊沉 積在介電保護層34上。填充層36係利用高沉積速率之 CVD(或類似的適當技術）沉積，以於頂層14之頂表面形 成實質均勻且共形沉積之Si〇2及/或SiN層。填充層％ 可為頂層14的延續，例如填充層可包含和介電保護層 201240174 34 —樣的材料。 現參照第5圖，施行CMP製程來處理沉積於介電保護 層34上的填充層36。藉此可移除頂表面的介電保護層 34與填充層36之Si〇2及/或SiN材料和gst，而留下填 滿介電材料的溝槽及GST3G的上緣，露出該聊3〇的 上緣以接收上電極。 現參照第6圖，形成上電極之電極材料4〇沉積於頂層 14上’使電極材料直接連接GST 3〇、㈣層34之材料 和填充層36之材料。電極材料係利用物理氣相沉積（pvD) 技術沉積，但所述方法不限於此，其也可採用其它技術。 另外，儘管所示電極材料為TiN，然其它材料也可使用。 現參照第7圖，電極材料經圖案化而形成上電極4〇， 其為橫向延伸跨越GST 30的細長元件。可利用任何適合 技術進行電極材料的圖案化，例如蝕刻。若採行蝕刻技 術圖案化，則將在下钱刻電極材料、介電材料和3〇 至下電極20的水平面，以移除從上電極4〇邊緣底下橫 向延伸的GST材料，並由平板來界定GST 30,該平板提 供下電極20至上電極40的連接（内連線）。 在另一步驟中，利用任何適合技術（如CVD、ALD等） 來共形沉積介電材料，以密封上電極4〇與下電極2〇間 任何露出之GST 30和介電填充層。 本文所述方法可加以縮放、控制，且適合與形成經修 飾的PCM元件相關的大量生產技術（HVM)合併使用。 相較於先前技術元件’所述方法和技術產生的元件有 10 201240174 數個優點。第一，因為在GST沉積於其上的表面之間無 間隙填充，故不會形成接縫。由於孔隙通常係於接縫處 隨時間擴展而成’且由於無接縫形成’因此無擴展成孔 隙之虞。因此’在不會形成孔隙的情況之下，損害利用 本文所述的方法所形成的PCM元件完整性的機會也因 此減少。 第二，GST主動區的尺寸係由GST膜厚與用於定義 GST尺寸以助於接觸電極的光微影技術妥善定義。此 外’ GST主動區係自行對準所形成之Pcm元件中的上電 。 第二’相較於光微影技術係以較小尺寸實行的其它孔 洞/溝槽填充結構，藉由將溝槽尺寸製作成具有2f之維 度，可更谷易、更有效率且更具成本效益地實行用於定 義GST主動區尺寸的光微影技術。 第四，由於GST主動區厚度能控制成如預期般薄，加 上此區寬度可製作成和上電極寬度一樣，故pCM元件和 其形成方法可輕易縮放。縮放性亦因不需填充間隙而有 所改善。因此，除上電極的圖案化外，縮放並無限制。 相較於先前技術中所述之採用交又間隔物的pcM晶 胞製造方法，本發明之PCM元件製造方法採用不同的製 程流程和製造順序’從而製造不同的對應pCM元件結 構。在先前技術所述之晶胞製造方法中，相變化材料（如 GST)係靠著（已形成之）堆疊LT〇與㈣上電極來沉積， 故GST係沿著垂直邊緣接觸上電極。反之，在本發明之 11 201240174 製造方法中’相變化記憶體材料（如GST)係於上電極形 成前適當沉積，因此相變化材料係沿著水平面接觸上電 極，其更易縮放，且製造方式更簡單、更便宜。 雖然本發明已以實施例詳述如上，然而，在此技術領 域中具有通常知識者將能理解’在不脫離本發明之精神 和範圍内，可產生各種更動並以均等物取代其元件。此 外，在不脫離本發明之基本範圍内，當可潤飾本發明之 教示’以適應特殊情況或材料。因此，本發明不限於上 述特定實施例，而是包括落入後附申請專利範圍之範_ 中的所有實施例。 【圖式簡單說明】 第1圖為形成於基板頂表面之溝槽和位於基板底表面 之一個下電極的示意圖。 第2圖為第i圖基板的示意圖，其具有沉積於溝槽内 與基板頂表面上的相變化材料。 第3圖為基板的示意圖，其中溝槽内與基板頂表面上 的部分相變化材料經移除。 冑為第3圖基板的示意圖’其中介電保護層和填 層沉積於溝槽内與基板頂表面上。 :5圖為第4圖基板的示意圖，其中部分介電保護層 、層經移除而露出頂表面上的相變化材料。 第6圖為上電極的示意圖’其沉積於基板頂表面上》 12 201240174 第7圖為基板的透視示意圖，其具有透過相變化材料 所形成之内連線而電氣連接的上、下電極。 【主要元件符號說明】 10 溝槽 12 基板 14 頂層 16 底層 20 下電極 22 壁面 26 位置 30 相變化材料 34 保護層 36 填充層 40 上電極 f 寬度 13201240174 VI. OBJECTS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to phase change memory elements, and more particularly to methods of forming phase change memory elements using germanium antim〇ny te Uuride . [Prior Art] Phase change memory (PCM) is a non-volatile memory used in computer applications. In PCM, the behavior of a chalcogenide material (usually a niobium alloy (gst)) is altered by a change between the crystalline phase and the amorphous phase of the material. A thermal resistor or any other suitable component is operated to heat to cause a phase change in the chalcogenide material. The resistivity of the crystalline phase and the amorphous phase can be used to represent the binary code used to store the data. To reduce the power required to induce changes between the two phases, a small amount of GST is used. In particular, a small amount is limited to very small grooves, holes (through holes) or the like. However, in the fabrication of PCM for computer applications, the highly conformal deposited GST obtained by chemical vapor deposition (CVD) or atomic layer deposition (ALD) is used to fill the structure to confine GST within the structure. In some methods of manufacturing the PCM, even a process in which a 1% conformal process is applied still forms a seam (the GST is not excessively concentrated at the interface joint when the GST臈 is joined to the sidewall, Therefore, after the cycle (high and low temperature alternately cause the material to change between the amorphous phase and the crystalline phase), the joint will become pores in the GST. The pores often cause early 201240174 reliability failure of the components using PCM 'reliable The degree of failure is usually characterized by short durability or low data retention. In its method, the pCM cell system is fabricated using a spacer and a spacer. In at least one method using a spacer and a spacer, a nitride button (TaN) is used. Deposited in a cup-shaped, 纟° structure, followed by a low temperature oxide (LTO). A chemical mechanical polishing (CMP) process is then used to expose the upper edge of TaN. The low temperature nitride (LTN) is accumulated on the portion. On the rim, the upper edge is the Titanium Tungsten (Tibet) layer and the TiW is at the top to form the upper electrode. The gst spacer is then deposited on the stacked LTO and TiW and LTN as a phase change material, and coated with LT〇. Covered cup structure. Deposited in aluminum/TaN a wire, and the aluminum/TaN interconnect wire is connected to the Tiw via the bottom of the cup structure to add a lower electrode. In this method, the GST is patterned by a complicated masking process, and the gST contacts the upper electrode along the vertical edge, so it is difficult Scaling thus greatly increases the cost of the method. In the method of forming the PCM element in the crucible, the wall structure is replaced by a wall surface which is usually GST-limited. The wall-preferred phase change material (GST or other chalcogenide) Material) is deposited onto the flat-surface of the adjacent wall using a flow. However, in this method, the phase change material is not appropriately limited as with the PCM element using the groove. Therefore, the performance and scalability of the simple element are comparable to the phase change material. The pcM component deposited on the trench is inferior. It is a method of forming a structure of the PCM element, which can appropriately limit the phase change material and does not incorporate a seam which is detrimental to the integrity of the component. [Description of the Invention] 201240174 Phase change memory element and method of fabricating the same. In the aspect of the invention, the invention relates to a phase change memory element, comprising a substrate, disposed on the first and second surfaces of the substrate a material, an upper electrode in the material of the second surface-surface, at least a lower electrode in the material of the second surface, and at least one flat structure in the substrate and connecting the upper electrode and the lower electrode. The material on the second surface is at least one of a low temperature oxide and a low temperature vapor. The flat structure is a substantially seamless and substantially nonporous phase change material structure. In another aspect, the present invention relates to the formation of phase change memory. A method of a body member. In this method, a substrate having a first surface and an opposite second surface is provided. The trench is formed on the first surface, and - or the plurality of lower electrodes are located on the second surface and connected to the trench. A material is deposited in the trench. A dielectric protective layer and a filling layer/also deposited in the trench are deposited on the first surface, and the interconnect formed by the phase change material maintains a connection with the lower electrode. In yet another aspect, the invention is also directed to a method of forming a phase change memory component. In this method, a substrate having a top layer and a bottom layer is provided, and a groove is formed in the top layer. At least the lower electrode is formed in the bottom layer. The phase change material is deposited in the trench and is connected to at least the lower electrode. A dielectric protective layer is deposited on the phase change material and a fill layer is deposited on the dielectric protective layer. The upper electrode is then deposited on the top layer and the phase change material is attached. The interconnect between the upper electrode and the lower electrode that is formed by the phase change material maintains electrical connection. Other aspects, features and embodiments of the present invention will become more apparent from the description of the appended claims. [Embodiment] A PCM element formed by the method of the present invention is shown below. The pcM component includes upper and lower electrodes connected by phase change materials. Dielectric materials are used to isolate the upper and lower electrodes and the isolated phase change material. Referring to Fig. 1, in a first step of forming a PCM element, a trench 1 is formed in the substrate 12. As shown, the substrate 12 includes a top layer 14 and a bottom layer 16 that are joined to each other. The top layer 14 comprises cerium oxide (si 〇 small or other LTO), nitriding (SiN) (or other (10)), < The composition acts as a dielectric to provide insulating properties. The bottom layer 16 contains the same or similar materials, and the composition of the bottom layer 16 can be different from the composition of the top I 14. However, the substrate 12 is not limited to including the top layer 14 and the bottom layer 16, and the substrate may be a single member comprising one or more layers of Si 〇 2 and SiN. The lower electrode 20 is located at the bottom of the substrate 12 by $16, such that the lower edge of the opposite wall 22 at the position μ at the 'groove H' will join the surface of the lower electrode 2''. Each of the lower electrodes 20 has a width f and is spaced apart from each other by a width f. The length of each of the lower electrodes 20 (i.e., the dimension perpendicular to the width in the lower electrode) is any desired length. Therefore, in the PCM element, the lower electrode 2 延伸 extends in three dimensions to have any desired configuration. The bottom layer 16 is also configured to include any suitable topography to accommodate the lower electrode 2〇 disposed therein. Although the lower electrode 2 has an angular structure, the present invention is not limited thereto, and the lower electrode may also have a cylindrical shape. The material for manufacturing the lower electrode 2 turns includes, but is not limited to, 201240174 Titanium nitride, TiNW, a combination of the foregoing materials, and the like. To form the trenches 10, a lithographic mask is placed over the top layer 14 and an etch process (e.g., using wet etch chemistry) is used to form the trenches. The width of the trench 1〇 is 2f. The length of the trench (i.e., the dimension of the vertical width in the trench size) is also 2 f. Referring now to Figure 2, in a second step of forming a pCM component, a phase change material is deposited on the top layer 14 of the substrate 12 and at least partially define the wall and bottom surfaces of the trench 1(). Phase change material #30 is deposited by a technique that distributes the phase change material to a uniform thickness and is as conformal as possible. Such techniques include, but are not limited to, CVD, digital CVD, pulsed (10), metal oxide CVD, and ALD. Variations of this technique are also within the scope of the methods described herein. The phase change material 3 is hereinafter referred to as GST 30'. The method of escape is not limited thereto, and other phase change materials may be used. For example, the phase change material 30 can be 锉, 赵, 碲, 碲, 碲, or any group of σ. In the case of sinking, the ratio of bismuth (Ge) to strontium (Sb) and strontium (Te) (atoms can be about 2:2. Η, etc. at, ·, , . 1 : 5, about 30: 15 ·· In the example of the early morning, /, ςκ is 2.2.5, Ge is about 20 to 25, about 20 to 25 atom%, and T is %. In the ratio of 4., the original 'Te is about 50 to In the embodiment of 60 atomic 0/, Sb A ′, 'Ge is about 40 to 45 atoms sb is about 5 to 1 〇. ^ 0 , and thousands / Te is about 50 to 55 atoms 0 / 〇. In a ratio of 30: 15 : 5 early 〇 /, Sh too from the example 'Ge is about 27 to 33 atoms / 〇' Sb is about 15 moxibustion h h atomic % 'Te is about 50 to 60 atomic %. Now less,,,, Figure 3, Shi 1 Tian... 丄疋 电 电 ( ( 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 间隔 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性GST30 at the bottom of the trench 1 。. In the directional electric (four) engraving, remove the transverse film (GST in this case) along with the GST 3〇 of the bottom surface of the trench 1 and selectively remove the top layer 14 After the GST3G on the top surface, the GST remains on the sidewalls of the trench, forming a substantially seamless A plate containing GST material that is substantially free of pores. Since the plate is deposited by a deposition process, its dimensions (such as ruthenium are not governed by the deposition process used, and the methods and components are not limited to GST 30 and can be selectively applied to the sidewalls. Instead of laying on the bottom surface of the trench, the step of removing the GST of the bottom surface of the trench is eliminated. In the embodiment where the directional electro-destructive process does not completely remove the GST 3G of the top layer, the CMP process can be removed. The top layer of the residual coffee. In the fourth step shown in Figure 4, the material is substantially conformally deposited on the top surface of the top layer 14 and the bottom surface of the GST cover and the bottom surface of the trench to form a dielectric protection. 34. The material used to form the dielectric protective layer Μ is SiN. However, the material is not limited to (4), and any other material that does not react with GST may be used. The formation of the dielectric protective layer 34 utilizes any suitable deposition technique, Substantially conformally deposited on the top layer 14 and sidewalls at a temperature below about 45 C. Also in a fourth step, a fill layer comprising peach and/or is deposited on the dielectric cap layer 34. Filler layer 36 utilizes high deposition rates CVD (or a similar suitable technique) is deposited to form a substantially uniform and conformally deposited Si 2 and/or SiN layer on the top surface of the top layer 14. The fill layer % can be a continuation of the top layer 14, for example, the fill layer can comprise Dielectric protective layer 201240174 34 - like material. Referring now to Figure 5, a CMP process is performed to process the fill layer 36 deposited on the dielectric cap layer 34. The dielectric protective layer 34 and padding of the top surface can be removed thereby. The Si〇2 and/or SiN material of layer 36 and gst leave a trench filled with dielectric material and the upper edge of GST3G, exposing the upper edge of the chatter to receive the upper electrode. Referring now to Figure 6, the electrode material 4 形成 forming the upper electrode is deposited on the top layer 14 to directly connect the electrode material to the material of the GST 3 〇, (4) layer 34 and the material of the filling layer 36. The electrode material is deposited using physical vapor deposition (pvD) techniques, but the method is not limited thereto, and other techniques may be employed. In addition, although the electrode material shown is TiN, other materials may be used. Referring now to Figure 7, the electrode material is patterned to form an upper electrode 4'', which is an elongated element that extends laterally across the GST 30. Patterning of the electrode material, such as etching, can be performed using any suitable technique. If the etching technique is patterned, the electrode material, the dielectric material and the horizontal surface of the lower electrode 20 will be etched to remove the GST material extending laterally from the edge of the upper electrode 4 and defined by the flat plate. GST 30, the plate provides a connection (interconnect) of the lower electrode 20 to the upper electrode 40. In another step, the dielectric material is conformally deposited using any suitable technique (e.g., CVD, ALD, etc.) to seal any exposed GST 30 and dielectric fill layer between the upper electrode 4 and the lower electrode 2. The methods described herein can be scaled, controlled, and suitable for use in conjunction with mass production techniques (HVM) associated with forming modified PCM components. There are several advantages of 10 201240174 compared to the elements produced by the methods and techniques described in the prior art. First, since there is no gap filling between the surfaces on which the GST is deposited, seams are not formed. Since the pores are usually expanded at the joints over time 'and because of the jointless formation', there is no expansion into the pores. Thus, the chances of impairing the integrity of the PCM components formed using the methods described herein are also reduced without the formation of voids. Second, the size of the GST active region is properly defined by the GST film thickness and the photolithography technique used to define the GST size to facilitate contact with the electrodes. In addition, the GST active region self-aligns the power-up in the formed Pcm component. The second's other hole/trench fill structure, which is implemented in a smaller size than the photolithography technique, can be more versatile, more efficient, and more cost-effectively by making the trench size a 2f dimension. The photolithography technology used to define the size of the GST active zone is advantageously implemented. Fourth, since the thickness of the GST active region can be controlled to be as thin as expected, and the width of the region can be made to be the same as the width of the upper electrode, the pCM component and its formation method can be easily scaled. Scalability is also improved by not filling the gap. Therefore, there is no limit to the scaling other than the patterning of the upper electrode. The PCM component manufacturing method of the present invention employs different process flows and manufacturing sequences to produce different corresponding pCM component structures than the prior art pcM cell fabrication method using spacers. In the cell fabrication method described in the prior art, a phase change material (e.g., GST) is deposited against the (formed) stacked LT and (iv) upper electrodes, so that the GST contacts the upper electrode along the vertical edges. On the contrary, in the manufacturing method of the invention 11, 201240174, the phase change memory material (such as GST) is appropriately deposited before the formation of the upper electrode, so that the phase change material contacts the upper electrode along the horizontal plane, which is easier to scale and is more manufactured. Simple and cheaper. Although the present invention has been described in detail above with reference to the embodiments of the present invention, it will be understood by those skilled in the art that the various changes may be made and the elements may be substituted in the equivalents without departing from the spirit and scope of the invention. Further, the teachings of the present invention may be modified to suit particular circumstances or materials without departing from the scope of the invention. Therefore, the present invention is not limited to the specific embodiments described above, but includes all embodiments falling within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a trench formed on the top surface of a substrate and a lower electrode on the bottom surface of the substrate. Figure 2 is a schematic illustration of the i-th substrate having phase change material deposited in the trenches and on the top surface of the substrate. Figure 3 is a schematic illustration of a substrate in which portions of the phase change material on the top surface of the substrate are removed.胄 is a schematic view of the substrate of Figure 3, wherein a dielectric protective layer and a fill layer are deposited in the trench and on the top surface of the substrate. 5 is a schematic view of the substrate of FIG. 4, in which a portion of the dielectric protective layer and layer are removed to expose the phase change material on the top surface. Figure 6 is a schematic view of the upper electrode 'deposited on the top surface of the substrate>> 12 201240174 Figure 7 is a perspective schematic view of the substrate with upper and lower electrodes electrically connected through interconnects formed by phase change materials. [Main component symbol description] 10 Trench 12 Substrate 14 Top layer 16 Bottom layer 20 Lower electrode 22 Wall 26 Position 30 Phase change material 34 Protective layer 36 Filler layer 40 Upper electrode f Width 13