TW201240067A - Semiconductor structure and manufacturing method and operating method for the same - Google Patents

Abstract

A semiconductor structure and a manufacturing method and an operating method for the same are provided. The semiconductor structure comprises a first well region, a second well region, a first doped region, a second doped region, an anode, and a cathode. The second well region is adjacent to the first well region. The first doped region is on the second well region. The second doped region is on the first well region. The anode is coupled to the first doped region and the second well region. The cathode is coupled to the first well region and the second doped region. The first well region and the first doped region have a first conductivity type. The second well region and the second doped region have a second conductivity type opposite to the first conductivity type.

Description

201240067

Iw jzrA VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor structure, a method of fabricating the same, and a method of fabricating the same, and more particularly to a semiconductor structure having parallel NPN B JT and PNP B JT and a method of fabricating the same And method of operation. [Prior Art] Electrostatic discharge (ESD) is a phenomenon of electrostatic charge transfer between different objects and electrostatic charge accumulation. The time of ESD is very short, only within a few nanoseconds. Very high currents are generated in ESD events, and the current value is usually ampere. g. Once the current generated by the coffee flows through the semiconductor body circuit, the semiconductor integrated circuit is usually damaged. Therefore, when a positive voltage (HV) electrostatic charge is generated in the semiconductor integrated circuit, which protection between the power supply lines must provide a discharge path to avoid the semiconductor integrated circuit. However, the D protection device requires an additional large design area and amount = Cheng. Therefore, the cost increases. Please refer to the i-th diagram. For example, a flow f (SCR) towel PW bipolar (four) crystal _ and 靡, electric connection. In addition, the L-protection device with a low maintenance voltage is prone to latch-up during the operation of the tenth. [Summary of the Invention] Zone, the first first well zone, the first doping zone is located on the second well zone, the second doped zone is implanted 3 201240067

IW7432FA is on the first well area. Anode_ to the first _-well region and the second doped region. The first well region has a second conductivity type opposite to the first conductivity:: doping has a second conductivity type. „first well region. coupling the cathode to the first well region and the second doping; I: the second region and the first doped region have a first conductivity type. The second well region has a second conductivity region The second conductivity type is opposite to the second type. The operation method of the semiconductor structure is provided. The method includes the following steps for the semiconductor structure. The semiconductor structure includes a first well region, a second well region, a doped region and a second doping region. a second well region adjacent to the first well region. The first doped region is located on the second well region. The second doped region is located on the first well region. The first well region and the first doped region have a first a conductive type. The second well region and the second doped region have a second conductivity type. The second conductivity type is opposite to the first conductivity type. Opening is formed by the second well region, the first well region and the second doping region a first bipolar junction transistor having a first type of type (Bing). Opening a second BJT having a second component type formed by the first doped region, the second well region, and the first well region. One component type is opposite to the second component type. The first bJT is electrically connected in parallel with the first B JT system. Embodiments 201240067 lw /^^zr/\ Fig. 2 is a top view of a semiconductor structure according to an embodiment. Fig. 3 is a cross-sectional view of the semiconductor structure of Fig. 2 taken along line AB. Fig. 4 is a view Figure 5 is a cross-sectional view of the semiconductor structure of Figure 4 taken along line CD. Figure 6 is a diagram showing an equivalent circuit of a semiconductor structure in accordance with some embodiments. The IV graph of the semiconductor structure of an embodiment is shown. Fig. 8 is a graph showing the IV structure of a semiconductor structure of a comparative example. Referring to Fig. 3, the semiconductor structure includes a base layer 2. The base layer 2 may be a block such as a crucible. Or formed by doping or epitaxial growth. The buried layer 4 is formed on the base layer 2. The buried layer 4 may be formed by doping or epitaxial growth. The buried layer 4 may be a deep well or a stacked structure having a plurality of layers. In some embodiments, the buried layer 4 is omitted. The first well region 6 is formed on the buried layer 4. The second well region 8 is formed on the buried layer 4. The first well region 6 and the second well region 8 are adjacent to each other. In some embodiments, for example, the first well region 6 and the first The well 8 is formed by doping a substrate exposed by a mask layer (not shown) formed on the substrate. After the doping step, the mask layer is removed. The insulating member 18 is formed in the first well region. 6 and the second well region 8. The insulating member 18 is not limited to the area yttrium oxide (LOCOS) as shown in Fig. 3. In some embodiments, the insulating member 18 may also be shallow trench isolation (STI). The element 18 may comprise an oxide such as oxidized oxide. The first doped region 14 is formed on the second well region 8. The second doped region 12 is formed on the first well region 6. The third doped region 10 is formed in the first A well region 6 is formed. The fourth doping region 16 is formed on the second well region 8. In some embodiments, for example, the first doping region 14, the second doping region 12, and the third #5 201240067 ·

The TW7432PA hetero region 10 and the fourth doped region 16 are formed by a doped substrate, such as a first well region 6 and a second well region 8 exposed by a mask layer (not shown) formed on the substrate. After the doping step, the mask layer is removed. In one embodiment, the first doped region 14 is adjacent to a portion of the fourth doped region 16, as shown in FIG. Referring to FIG. 3, in some embodiments, the base layer 2, the first well region 6, the third doped region 10, and the first doped region 14 have a first conductivity type. Further, the buried layer 4, the second well region 8, the second doped region 12, and the fourth doped region have a second conductivity type opposite to the first conductivity type. For example, the first conductivity type is P type and the second conductivity type is N type. The doping concentration of the first well region 6 may be higher than the doping concentration of the substrate layer 2. The doping concentration of the third doping region 10 and the first doping region 14 may be higher than the doping concentration of the first well region 6, respectively. The doping concentration of the buried layer 4, the second doped region 12, and the fourth doped region 16 may be higher than the doping concentration of the second well region 8, respectively. Referring to FIG. 3, in an embodiment, the anode 20 is coupled to the first doped region 14, and is also coupled to the fourth doped region 16, the second well region 8, and the buried layer 4. In addition, the cathode 22 is coupled to the second doped region 12 and is also coupled to the third doped region 10 and the first well region 6. Referring to FIG. 3, in an embodiment, the second well region 8, the first well region 6, and the second doped region 12 form a first bipolar junction transistor (BJT) 24 having a first component type. The first doped region 14, the second well region 8 and the first well region 6 form second BJTs 26 and 28 having a second component type. The first component type is opposite to the second component type. The buried layer 4, the first well region 6 and the second doped region 12 form a third BJT 30 having a first component type. For example, the first component type is NPN type, and the second component type is 6 201240067

IW = metal oxide + conductor transistor (MOS) (such as NM〇s and pM〇s) or opposite type (N-type and p-type) field effect transistors in other real-films . The second well zone 8, the first well zone 6 and the second doping 22 are the collectors of the first BJT 24, the base and the shot S n 28 L (four) - the well zone 8 and the first well zone 6 They are the second ΒΓΓ 26 and the sex (four). ▲ base and collector. The first break 24 and the second pie 26 are electrically connected to each other. The second BJT 28 is also electrically connected in parallel. Buried two techniques "One Well Area 6 and Second Miscellaneous Area 12 are the collector, base and emitter of the third BJT 30, respectively. The semiconductor structure shown in Fig. 3 and the semiconductor structure shown in Fig. 3 are not formed in the two second dummy regions I. The production of 彳H 106. The gate 132 includes a dielectric layer 134 and an electrode layer suppressor layer 136 formed on the dielectric layer 134. The electrode layer 136 can be formed by a single or double poly ♦ process. Further, the electrode layer handle is connected to the cathode 122. The semiconductor structure can be used as an ESD t-set. NpN BjT and pNP bjt are integrated into the -ESD device. Therefore, the layout area of the metal wires and the esd device can be reduced. The hiding area of the semiconductor structure in the embodiment is less than that of a typical ESD device. The semiconductor structure does not have a field plate effect and is therefore insensitive to the route. The semiconductor structure II can be fabricated by a standard bcd process. Therefore, no additional mask or process is required. The semiconductor structure of an embodiment can be applied to any suitable process or operating voltage (hv) or low voltage (LV) device, such as a typical DC circuit operation. In the embodiment, the first BJT with the electrical parallel connection and the second BJT ^ 7 201240067

The equivalent circuit of the TW7432PA semiconductor structure is shown in Figure 6. In one method of operation, the first BJT and the second BJT are turned on in a stage by stage manner for use as a high voltage ESD protection structure. For example, the PNP BJT is turned on after the NPN BJT is triggered and turned on. As shown in Figure 7, 'In Operation' triggers the NPNBJT to be turned on. The snapback is determined by the opening of the PNP BJT. The opening resistance of the ESD device (R〇n;

The slope of the graph is obtained after the snapback decision. The NpN BJT and the ΡΝΡ ΒΓΓ are simultaneously discharged with a high ESD current. The Ron system of the semiconductor structure of the embodiment shown in FIG. 7 is smaller than the R〇i^ of the comparative example having the general NPN BJT as shown in FIG. 8, and the cell pitch of the semiconductor structure of the embodiment is compared with the comparative example. (cell pitch) reduced by 53.24%. Maintaining the electrical breakdown and the second crash trigger current increased by 21.14% and 60.12%, respectively. In other embodiments, the device can be turned on by an additional bias applied to the gate or base. In the embodiment, the breakdown voltage of the semiconductor structure is approximately HV. The trigger voltage is lower than the breakdown voltage of the HV device. The sustain voltage is high = Thus, for example, the semiconductor structure of the embodiment can more easily avoid latch-up than a conventional controlled rectifier (SCR). While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and it is to be understood that those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the patent application. . BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing an equivalent circuit of a general semiconductor structure. 8 201240067 /Η〇ΔΓ/\ Road Figure 2 illustrates a top view of a semiconductor structure in accordance with an embodiment. A cross-sectional view of the semiconductor structure shown in Fig. 2 along the αβ line. 4 is not according to the fifth embodiment of the semiconductor structure of the embodiment. FIG. 6 is a cross-sectional view of the semiconductor structure along the CD line. FIG. 6 is a diagram showing the effect of the semiconductor structure according to some embodiments. The I_V curve of the semiconductor structure of the embodiment is shown in FIG. 8 - the π curve of the semiconductor structure of the comparative example [the main component symbol description] 2: the base layer 4: the buried layer 6, 106 · the first well region 8: the second Well region 10: third doped region 12, 112 • second doped region 14: first doped region 16: fourth doped region 18. Insulation element 20' 132: anode 22 '^2: cathode 24: First Bipolar Junction Transistor (BJT) 26 ' 28 : Second BJT 3〇: Third BJT 134 ··Dielectric Layer

S 9 201240067

TW7432PA 136: Electrode layer

Claims (1)

201240067 1 w /^3zr/\ VII. Patent application scope: 1. A semiconductor structure comprising: a first well region; a second well region adjacent to the first well region; a first doped region located at a second doped region, located in the first well region; an anode coupled to the first doped region and the third well region; and a cathode ' _ to the first well region And the second doped region, wherein the first well region and the first doped region have a first conductivity type, and the second well region and the second doped region have a second conductivity type, The conductivity type is opposite to the first conductivity type. The semiconductor structure of claim i, wherein the second well region, the first well region and the second doped region form a first bipolar junction transistor, the first The first doped region, the second well region and the first well region form a second BJT' the second turn; τ has a second component type, the second component type Contrary to the brother of a component type. 3. The semiconductor structure of claim 2, wherein the first component type is an NPN type, and the second component type is a pNp type. 4. The semiconductor structure of claim 2, wherein the first B JT is electrically connected in parallel with the second b JT system. 5. The semiconductor structure of claim 2, wherein the second well region is a collector of the first BJT, the first well region being a base of the first BJT, the second doping The emitter of the first bjt, the first doped region is the emitter of the second BJT, and the second well region breaks the base of the second BJT of 201240067 TW7432PA, the first well region is the first The semiconductor structure of the first aspect of the invention, wherein the first conductivity type is a P type, and the second conductivity type is an n type. 7. A method of fabricating a semiconductor structure, comprising: forming mutually adjacent first-well regions and second well regions; forming a first doped region on the second well region; forming a second doped region On the first well region; coupling the anode to the first doping region and the second well region and coupling the cathode to the first well region and the second doping region, wherein the first The well region and the first doped region have a -first conductivity, the second well region and the second doped region have a second conductivity type, and the first conductivity group is opposite to the first conductivity type. 8. A method of operating a semiconductor structure, comprising: providing a semiconductor structure, comprising: a first well region; a second well region adjacent to the first well region; a first doped region located at the second a well region; and a second doped region on the first well region, wherein the „-doped region has a first conductivity type, the second region and the ^ doped region have a second conductivity Type, the second conductivity type is opposite to the [conducting and transmitting Si: 妍 'the first - grasping has - the - element type change" and is the second well region, the first well region and the second doping Forming a second BJT, the second BJT having a 12 201240067 1 W tHDZ.rt\ the second component type being opposite to the first component type, and the second BJT being the first doped region The second well region is formed with the first well region, wherein the first BJT is electrically connected in parallel with the second BJT system. 9. The method for operating a semiconductor structure according to claim 8 of the patent application scope includes : coupling an anode to the first doping region and the second well region; and coupling a cathode to the first well region and the first 10. The method of operating a semiconductor structure according to claim 8, wherein the second BJT is turned on after the first BJT is turned on.