TW201249116A - Radio frequency integrated circuit - Google Patents

Abstract

Embodiments of the invention are concerned with configurable RFICs. In an embodiment there is provided a configurable radio-frequency integrated circuit (RFIC) comprising one or more configurable low noise amplifier circuits, each of said one or more configurable low noise amplifier circuits being configurable between: an internal input impedance matching topology in which the respective low noise amplifier circuit comprises one or more internal input impedance matching components adapted to match the input impedance of the respective low noise amplifier to a given input, said one or more internal input impedance matching components being located internally to the respective low noise amplifier circuit; and a topology different from said internal input impedance matching topology.

Description

201249116 VI. Description of the invention: [Technical field of invention] The present invention relates to a radio frequency integrated circuit (RFICV is particularly, but not limited to, a configurable RFIC. [Prior Art] A radio frequency (RF) platform is a high volume product, which includes Several integrated circuits (ICs) for audio, power management, RF transceivers, etc. 1C can provide mass-produced products with the best economical price, due to the fixed cost of the mask. This leads to a reduction in unit cost as the number of manufactured 1C increases. Infinite Transfer (OTA) performance defines the capabilities of the RF platform. OTA represents an important sales factor and can be an important selection criterion for potential customers' and the unit cost is also ^ Τ A performance is a function of antenna performance and rf 1C and baseband 1C capability. Typically, the size of the antenna is inversely proportional to the rf frequency', ie the antenna becomes larger as the wavelength increases. In the user equipment (UE) The size of the antenna is limited by the small form factor of the product, which results in an antenna performance that is not optimized. Therefore, the platform performance can be below 1 GHz. Lower degradation, resulting in reduced up/down key performance. Currently the most advanced RF 1C is designed to operate in several different frequency bands 'eg Global System for Mobile Communications (GSM) 850, 900, 1800 and/or 1900, Broadband Code Division Multiple Access (WCDMA), High Speed Packet Access (HSPA) and/or Long Term Evolution (LTE) bands 1, 2, 3, etc. Typically, RF filters (or links using Frequency Division Duplex (FDD)) In the case of a duplex filter, it is placed between the antenna and the RF IC to filter out unwanted RF signals. Since it is not 201249116 5 = key/downlink configuration, there are several frequency bands of choppers with Insertion loss (IL). IL 胄 'The receiver will be less sensitive (higher θ number). For example, Wcdma and Bands 2 and 3 have narrow duplex frequency gaps (highest transmission frequency and The difference in frequency between the lowest reception frequencies results in a higher IL. Due to the receiver sensitivity in the above bands, the range of wireless links is relatively short. As a result, network design becomes more challenging and more expensive' For example, more base stations are needed. 曰 Therefore, from the network operation From the point of view, good reference sensitivity, related quality factors. In the near future, the need for more sophisticated front-end module (FEM) s history juice 'expected low noise amplifier (LNA) in RF receiver The IL at the level will increase due to carrier aggregation (CA) between the bands. Furthermore, some existing bands will extend to cover a wider bandwidth and may have a narrower duplex distance. (eg band 2 + G block, winding: ι91〇 ~ 1915 MHz, downlink: 1990~1995 MHz). In this case, additional leakage is expected due to duplexer and switching loss, and due to Additional filtering is required for challenging duplex and coexisting scenarios. More generally, cost optimization is required, including with regard to filter modules and materials. The LNA is often the first amplification stage in the RF receiver. The minimum noise index of the receiver is set according to Friis' equation LNA. The low LNA noise index is a key parameter that determines the reference sensitivity of the entire transceiver or RF platform. The LNA is also a key part of determining the input impedance of an RFIC. Sufficient input matching performance is required because if the input of LN A is not properly matched to a particular input impedance, the RF filter performance in front of the LNA will be degraded. Since the RF filter in front of the LNA typically has a fixed frequency range of 201249116, the RFIC input will also match the specific frequency. Depending on the LNA structure, it may be necessary to utilize matching components outside the wafer to set the wheel alignment to the desired level. Depending on the number of RFIC inputs, the total number of external matching components can become high and is therefore an expensive and bulky solution. RFIC performance is a key factor in determining the performance of an RF platform. In RFic, the LNA defines the smallest possible noise index, which partially defines the reference sensitivity. RFIC's sensitivity performance and input matching configurability are fixed' and this leads to platform optimization not being optimized due to several levels of customers (eg network operators, original equipment manufacturers (〇EM)) And other mobile device products, each of which can have different requirements for the same chipset. Since the individual ic costs are reduced as the number of units increases, it is not economically sensible to design optimized ICs for different customers and/or products. It can be seen from the above that there are many different design factors to consider when designing R F, and it may be difficult to take into account some or all of these factors. It is therefore necessary to enhance RFic design by providing design adaptability, including ways to improve consideration of diverse design factors. SUMMARY OF THE INVENTION Provided in accordance with a first embodiment is a configurable radio frequency integrated circuit (RFIC) comprising one or more configurable low noise amplifier circuits, - or more configurable Each of the low noise amplifier circuits can be configured between: , an internal input impedance matching topology, wherein each of the low noise amplifiers 201249116 includes - or more internal input impedance matching components, It is adapted to match the input impedance of an individual low noise amplifier to a given input and one or more internal input impedance matching components are tied within an individual low noise amplifier circuit; and different from internal input impedance matching Topological topology. In some embodiments, the individual low noise amplifier circuits in the different topologies do not include at least one of the one or more internal input impedance matching components. In some embodiments, individual low noise amplifier circuits in different topologies do not include any of one or more internal input impedance matching components. In an embodiment, different topologies include partially externally matched or fully externally matched topologies, requiring - or more material components (ie, components external to the configurable RFIC) for input impedance matching . The external matching components are placed outside the RF 1C on a printed wiring board (PWB) or the like. The configurable RFIC can be configured according to the customer's needs. Cost efficiency and high quality and reliability can be provided by configuring one or more LNAs of the RFIC to be internal input impedance matching topologies. Improved sensitivity can be provided by configuring one or more L N A of rf 1C to require different topologies of external input impedance matching components. Embodiments therefore provide trading capabilities for cost and performance with a single RFIC a and § ten. Since a wide variety of products with different requirements can be covered by the same RFIC, this leads to more optimized engineering and marketing solutions. In some embodiments, at least one of the one or more configurable low noise amplifier circuits includes a switching arrangement, the at least one configurable low noise amplifier circuit being groupable via an individual switching arrangement The state enters the internal input 201249116 into the impedance matching topology and between different topologies. Therefore, the circuit can be configured to match the internal input impedance matching topology or different topologies depending on the desired circuit performance. In some embodiments, the internal input impedance matching topology includes a resistance feedback low noise amplifier topology, and the different topologies include a low-noise amplification topology that senses degradation. In some embodiments, the internal input impedance matching topology includes a common gate low noise amplifier topology, and the different topologies include a low noise amplifier gate topology that senses degradation. In some embodiments, the different topologies include low-noise amplifier topologies that sense degradation, and the internal input impedance matching extension includes a singularity that is configurable for low noise. The input of the amplifier circuit, while the output of the impedance matching stage provides an input bias for the impedance matching stage) and the feedback stage (which is coupled to the output and voltage source of the impedance matching stage, while the feedback stage provides compensation operation for the impedance matching stage Voltage, therefore, the RFIC can support several different combinations of LNA topologies that provide internal impedance matching capabilities or require external matching components. In some embodiments, - or more of each of the configurable low noise amplifier circuits Including the common output terminal, and the individual configurable low noise amplifiers S are provided in the internal output terminal when the internal 35 input impedance matching extension # or different topology is provided. The single output terminal The use of two LNA topologies provides a configurable RFIC with a lower cost solution. In some embodiments, some but not all of the configurable RFICs are configurable low. miscellaneous The amplifier A circuit includes a common output terminal, and the individual configurable low noise amplifier circuits are provided with an output signal when the internal input impedance matching topology or different topology is provided at this common output = 201249116; In other embodiments, the right 3► one + 1 ^ ^ one or more configurable low noise amplifier circuits in the configurable RF 1C include a common output terminal, while the individual configurable low noise amplifiers The output signals of the circuit when configured as internal input impedance matching topologies or different topologies are provided at the common output terminal. In some embodiments, the configurable RFIC includes an interface arranged to place one or more At least one of the configurable low noise amplifier circuits is coupled to a radio frequency (RF) front end module. In some embodiments, the interface includes at least a first input connection arranged to place one or more configurable At least a first one of the low noise amplifier circuits is coupled to the first RF band output of the RF front end module. In some embodiments, the interface includes at least a second input connection arranged to place one or more configurable Low noise amplification At least a second of the circuits is coupled to the second rw band output of the RF front end module, wherein the second rf band is different from the first RF band. Thus, for example, in a carrier aggregation environment, the configurable RFIC is capable of placing multiple RFs The band input is coupled to a plurality of configurable 'two. In some embodiments, the configurable RFIC includes another interface arranged to connect at least one of one or more configurable low noise amplifier circuits In another embodiment, the front end module includes a main antenna RF front end module and the other RF front end module interface includes a diversity antenna RF front end module. Therefore, for example, a high speed downlink package is stored. The multiple receiver branch environments of (HSDPA) and LTE are supported on a single configurable (four). In a second embodiment, the other interface includes at least a third input connection arranged to be - or more At least a third of the low-noise amplifier circuits of the state is connected to the third (four) piggyback output of the other-RF front-end module, wherein the first-band frequency band includes the third RF frequency band; and the other interface is at least the fourth input 201249116 , arranged in a way At least a fourth one is connected to two: an output, wherein the third RF band is not the (10)/terminal module of the fourth RF band, the -RF band. In some implementations, the p'th third RF band is included, and the second RF band is banded. So, for example, in a carrier aggregation environment, configurable support for multiple (four) bands is rounded into the primary and diversity receiver branches. The == example' configurable coffee includes at least one interface arranged to connect to at least one of the more or more configurable low noise amplifier circuits. According to a second embodiment, there is provided a method of configuring a configurable rfic 'The RFIC comprises one or more configurable low noise amplifier circuits'. The method comprises one of the following: One or more control signals are applied to at least one of the one or more circuits to configure the at least one circuit as an internal input impedance matching topology, wherein the individual low noise amplifier circuits include one or more An internal input impedance matching component ' adapted to match an input impedance of an individual low noise amplifier to a given input, and one or more internal input impedance matching components are tied within an individual low noise amplifier circuit; Or applying one or more control signals of the second group to at least one of the one or more circuits to configure the at least one circuit to a different topology, wherein the individual low noise amplifier circuits are not included One or more internal input impedance matching members. According to a third embodiment, there is provided a method of manufacturing a configurable RFIC according to the first embodiment. 10 201249116 According to a fourth embodiment, there is provided an RF module comprising one more RF front end module, and the RF front end module coupled to one or more configurable RFICs according to the first embodiment Provided in accordance with a fifth embodiment, is a wafer set comprising one or more configurable RFICs according to the first embodiment. According to a sixth embodiment, there is provided a device 'which comprises - or a plurality of configurable RFICs according to the first embodiment. The device may include, for example, a mobile/cellular phone. Provided in accordance with a seventh embodiment is a configurable radio frequency integrated circuit (RFIC) that includes one or more configurable low noise amplifier circuits and one or more configurable low noise amplifiers. Each of the circuits can be configured between: an internal input impedance matching topology, wherein the individual low noise amplifier circuits include one or more internal input impedance matching components adapted to place individual low noise amplifiers The input impedance is matched to a given input, and one or more internal input impedance matching components are tied inside the individual low noise amplifier circuits; and where the external external matching topology, where the individual low noise amplifier circuits are Does not include any of one or more internal input impedance matching components. Further features and advantages will be apparent from the following description of the preferred embodiments, which are set forth by way of example only. [Embodiment] A receiver typically includes one or more 201249116 radio frequency (RF) filters positioned between an antenna and an LNA(s) that form a first amplification stage of the receiver. FIG. 1 illustrates an example of an exemplary receiver that includes an RF module 1 and an antenna 130. The RF module 100 includes an RF front end module 132 that in turn includes one or more (total of up to n) RF filters! 10-12 is used to filter the RF signal collected by the antenna 130. The RF module 1 also includes rf 1C 134, which in turn includes one or more (up to a total of m) LNAs 120-122 to amplify the filtered signals produced by the RF filters 1 10 - 112. Figure 2 illustrates an RF chipset on a PWB for use with a receiver. The receiver includes a high band (HB) antenna and a low frequency band (LB) antenna connected to the RF front end module (FEM). The RF FEM is connected to one or more power amplifier (PA) modules and RFICs. The PA module can provide more functionality beyond the magnification function. The RFIC includes a transmitter (TX, which includes one or more amplifiers) and a receiver (RX, which includes one or more LB LNAs and one or more HB LNAs). For example, HB may include frequency bands I, π, in, iv, VII, IX, XI 'PCS, DCS. LB may include, for example, frequency bands V, VI, VIII, XII, XIII, XIV; and GSM 850 and EGSM 900. Figure 3 illustrates an RF chipset on a PWB for use with a receiver. The receiver includes a HB antenna and an LB antenna connected to the primary RF FEM. The receiver also includes a diversity (DIV) antenna connected to the DIV FEM. The RF FEM is connected to one or more PAs and RFICs. The RFIC includes TX (which includes one or more amplifiers) and RX (which includes one or more LB LNAs, one or more hb LNAs, one or more DIV LNAs). The DIV antenna is an additional antenna that is included to improve the reception quality and reliability of RF receiver links, such as for HSDPA and LTE environments.

S 12 201249116 The current state-of-the-art RFIC supports several fields and adds a different frequency band. RF choppers between RFICs are typical; antennas and bandits are broken in fixed RFIC inputs that match the specific, range, and the RFT "4 a. is dedicated to inputs in different frequency ranges. Packet Access (HSDPA) and Ι^ΤΕ, need | > 'The same as the chain of the knife (DIV) to receive 3 §. The number of RF inputs supported in the mu RFIC °, this step increases, especially when

When the receiver. The DIV LNA is often the _block in the RFIC receiver. Depending on the input matching may be passive and/or active and consist of components on the internal wafer, or input matching may be achieved by an external component placed on pwB. In general, the slab on the wafer has a larger than external component: quality (four). However, since the size and cost of the use panels should be minimized, external components should be avoided if possible. For multi-band and multi-mode transceivers covering several frequency bands, the total number of external components tends to be higher. As another example, a % nested HSDPA~LTE requires a diversity receiver to increase the number of external matching components required on the application board. * Considering receiver performance' The matching network of external components often causes some passive voltage gain before the LNA, thus reducing the noise contribution of the lna input transistor and thus reducing the overall noise figure of the receiver. This generally means that an LNA topology containing external matching components can achieve a better noise index than an LNA with internal matching. In addition, the selectivity of the LNA can be improved by passive matching components. For example, the effect of a transmitter (τχ) in a frequency division duplex (FDD) system can be suppressed. In addition, improved selectivity can mitigate desensitization in multiple RF environments 13 201249116 (desensitization). Due to the limited attenuation of other RF communication systems and the third harmonic component of the local oscillator signal used for down conversion, for example, when the receiver is down from three times the desired signal frequency De-sensitization can result when converting unwanted signals. As a result, transactions with significant performance versus cost (material bills, including additional P WB / die area and external components), current consumption (battery life) 'size, etc.' were encountered. However, at the current state of the art transceivers, the LNA and RFIC topologies are fixed. The embodiments described herein relate to RFICs that have the ability to accommodate modifications, thus avoiding non-optimized and inelastic designs. This configurable RFIC provides an optimized performance and cost-effective RF platform to meet different types of needs. Embodiments include a configurable RFIC that includes one or more configurable low noise amplifier circuits. Each of the one or more configurable low noise amplifier circuits is configurable between an internal input impedance matching topology and a different topology. For internal input impedance matching topology, the low noise amplifier circuit includes one or more internal input impedance matching components adapted to match the input impedance of the individual low noise amplifiers to a given input. One or more internal input blocking matching components are located inside the individual low noise amplifier circuits. In an embodiment, the individual low noise amplifier circuits in the different topologies do not include at least one of the one or more internal input impedance matching components. In an embodiment, the individual low noise amplifier circuits at different topologies do not include any of one or more internal input impedance matching components.

S 14 201249116 for different topologies 'Because the low noise amplifier circuit does not have an internal input impedance matching topology for input impedance matching, one or more components outside the low noise amplifier circuit are required for Input resistance; charge matching. In the embodiment described below with respect to Figures 4 through 10, the different topologies refer to external input impedance matching topologies, i.e., one or more external components are required for input impedance matching topologies. The external input impedance matching topology has a better noise index, which results in better reference sensitivity at the platform level. However, the pWB area is increased due to the need for an external matching member, so the cost is relatively high. The internal input impedance matching topology, although no external matching components are required, but the LNA noise performance is as much as 1 decibel (dB) compared to the external input impedance matching topology of the external matching LNA. Depending on the RF chopper/FEM at a lower RF frequency or the IL^ of a limited antenna performance, some of the keying losses can be compensated using the configurable RFIC described above. If the customer does not need to improve the sensitivity performance in any frequency band, then the cheapest solution can be provided. In the embodiment, since the number of assembled components on the PWB can be optimized, it is possible to provide a device with high output and high reliability. Several embodiments are now hostile with respect to Figures 4 to 1 . In these embodiments, the input interface of the RFIC from the FEM6"RF band output to a configurable LNA configured to match the internal input impedance matching (i.e., using internal impedance matching) is shown as an empty triangle. The input interface of the RFIC from the (5) frequency band output to the configurable lna (ie, using external impedance matching) configured as an external input impedance matching topology is shown as a shadow (or "filling 15 201249116" )triangle.

If the LNA is configured as an internal input impedance matching topology, the input connections (or "埠" or "pins") in the RFIC interface can be directly connected to the appropriate RF band output of the fem.

If the LNA is configured as an external input impedance matching topology, the input connections in its RFIC interface will be connected to the appropriate RF band output of the FEM via one or more external matching components. Figure 4 illustrates an RF chipset on a PWB for a receiver, including a configurable RFIC according to an embodiment. The embodiment of Figure 4 shows an ultra low cost scenario with a primary FEM to configurable A single receiver (RX) branch of the RFIC. The configurable RFIC includes an interface arranged to connect one or more configurable LNAs to the primary FEM. The interface includes several input connections, each of which connects the configurable LNA input to the RF band output of the primary fem. Here, no external impedance matching components are utilized, and all LNAs in the RFiC are configured as internal input impedance matching topologies, where input matching is implemented inside each LNA circuit. Figure 5 illustrates an RF chipset on a PWB for use with a receiver, including a configurable RFIC in accordance with an embodiment. The embodiment of Figure 5 shows a low cost scenario with a primary Rx branch from the primary FEM to the configurable RFIC 'also having a mv r knife branch from the DIV FEM to the same configurable RFIC. Figure 5 embodiment The configurable RFIC includes a first interface that is arranged to connect one or more configurable LNAs to the primary FEM. The first bread includes several input connections, each of which connects the configurable LNA input to

S 16 201249116 Main fem@ "band output. Configurable RFIC also includes second

It is arranged to connect one or more configurable LNAs to the DIV FEM. The second interface includes several input connections, each of which connects the configurable LNA input to the rf band output of the DIv job. Here, no external impedance matching components are utilized, and all the LEDs in the RFIC are configured as internal input impedance matching topologies where input matching is implemented inside each of the circuits. In Figures 4 and 5, since the number of assembled components on the PWB is relatively small, the configuration can provide a high throughput and high reliability device for a particular customer. For example, this may involve products that suffer from high temperature changes that cause mechanical stress, condensed water can damage electronic components/devices and cause rot, or the solder may be destroyed much earlier than expected, thus shortening Product life. Furthermore, machine-to-machine (M2M) devices may benefit from such ultra-low-cost RF performance without the need for diversity branches, for example, as intended for LTE devices. Similar to the configurable RFIC of the embodiment of Figure 5 above, the configurable RFIC of the embodiment of Figures 6 to 10 below also includes first and second interfaces, which are arranged to group one or more The LNA inputs are connected to the RF band outputs of the primary FEM and DIV FEM, respectively. Figure 6 illustrates the rf chipset on the PWB for the receiver, which includes a configurable RFIC in accordance with an embodiment. The scenario shown in the embodiment of Figure 6 is that European network operators wish to increase the sensitivity of RF Band 1. The configurable lna of the Band 1 RF output connected to the main FEM is configured as an external input impedance matching topology, where the external input impedance is used to improve the noise performance of the main RX and thus improve the sensitivity. In addition, the leakage of the TX of the primary receiver branch can be suppressed by such external matching. However, in the diversity branch, there is no TX connected to the RF (duplex) filter. Since the main and DIV receivers operate at the same frequency, the antennas are physically different and separated from each other'. Therefore, there is limited isolation between the two antennas. , for example 10 to 15 decibels. This means that the effect of τχ is smaller in the DIV branch than in the main branch, since the TX leakage is suppressed by the amount of isolation of the antenna. This means that the external matching component is not mandatory in the DIV branch. The configurable LNA connected to the band 1 rF output of the DIV FEM is thus configured as an internal input impedance matching topology in which internal impedance matching components are used to keep the total number of components and cost as low as possible. The configurable LNA of the embodiment of Figure 6 connected to the rf band 1 output of the primary FEM is configured as an external input impedance matching topology, and is connected to the (10) ugly RF frequency 1 output configurable LNA It is configured as an internal input impedance matching topology. This means that on the PWB, one or more external matching components will be connected in the main interface of the RFIC between the main fem band 1 RF output and the appropriate configurable LNA input, while the DIV FEM band 1 RF The output is in the DIV interface of the ruler and is directly connected to the appropriate configurable LNA input. Figure 7 illustrates an RF chipset on a PWB for a receiver, its package, a configurable RFIC in accordance with an embodiment. The scenario shown in the embodiment of Figure 7 is that the US network operator wants to compensate for the insertion loss due to the RF band 2 of the band. Configurable (4) of the Band 2 RF output connected to the main FEM 18 201249116 Configured as an external input impedance matching topology, which requires an external matching component. The band 2RF output connected to DIVFEM is available. The LNA is also configured as an external input impedance matching topology, which requires an external matching component. This is said to be on the PWB, and one or more external matching components will be connected between the band 2 RF output of the primary FEM and the appropriate settable LNA input in the rfic = interface. Similarly, one or more external matching components are connected in the DIV interface of the RFIC between the DIV ugly band 2 rf output and the appropriate configurable LNA input. For this particular example, external matching components are used for both primary and diversity receivers. In the near future, RF „ 2 will extend and also cover G: block (winding frequency: 19^4915 MHZ, downlink frequency: 199〇~1995 mHz), so forming a more challenging duplexer Filtering situation. As a result, even higher insertion loss is expected, which must use the two performance configurations according to the embodiment of Figure 7. Figure 8 illustrates an RF chip set on a PWB for a receiver, including according to an embodiment The configurable RFIC. The embodiment shown in Figure 8 shows that the network operator using RF band 20 (791 MHz to 821 MHz) wants to improve the sensitivity. Here, the third harmonic of the RX band (2373) ~2463 MHz) partially overlaps the industrial, scientific, and medical (ISM) band of 2,4 GHz. Therefore, to mitigate down-conversion from the third harmonic and to minimize desensitization of the desired channel, the interference pair The signal-to-signal ratio (ISR) performance can be improved by the preferred selectivity provided by the external input impedance matching component. The configurable LNA connected to the band 20 RF output of the primary FEM is configured as an external input impedance matching topology, Which requires external matching components. 19 201249116 The configurable LNA of the Band 20 RF output connected to the DIV FEM is also configured as an external input impedance matching topology, which requires an internal matching component. This is said to be on the PWB, one or more external matching components will be in rfic The main interface of the main FEM is connected to the band 2〇RF output of the main FEM and the appropriate configurable LNA input I__' or more external matching components will be connected to the DIV FEM in the DIV interface of the RFIC Between the band 2〇rf output and the appropriate configurable LNA input. Configuration similar to the embodiment of Figure 8 or can be used to suppress 5 GHz wlan and cellular bands operating around 1·7 to 1.9 GHz: Figure 9 illustrates an RF chipset on a PWB for a receiver that includes a configurable RFIC in accordance with an embodiment. The embodiment of Figure 9 shows a carrier aggregation (CA) scenario where it is due to complex coffee and The additional leakage caused by the filter settings is partially compensated by the external matching components.

Primary FEM and DIV FEM

The functions of both RF band 3 and RF band 7' are used to process the signals from RF band 3 and RF band 7 of the main fem and DIV FEM with a configurable RFIC. The configurable lna of the band 3 connected to the main FEM is configured as an external input impedance matching topology, and an internal matching component is required in & The band 7 rf connected to the main FEM is converted to an external input impedance matching topology in which the band 3 RF connected to the DIV FEM is configured as an external input impedance matching topology, which is connected to the DIV FEM band 7 RF output. The LNA of the state is also configured to require internal matching components. The internal input impedance is matched to the configurable LNA that is required by the internal matching component. The configurable LNA is also configured where an internal matching component is required. 20 201249116 This means that on the PWB, one or more external matching components will be connected between the Band 3 RF output of the primary FEM and the appropriate configurable LNA input in the primary interface of Rfic. In addition, one or more external matching components will be connected between the Band 7 RF output of the primary FEM and the appropriate configurable LNA input in the primary interface of RF 1C. Similarly, on the PWB, one or more external matching components will be connected between the DIV FEM's Band 3 RF output and the appropriate configurable LNA input in the DIV interface of the RFIC, and one or more The external matching component will be connected between the DIV FEM's Band 7 RF output and the appropriate configurable LNA input in the RFIC's DIV interface. Figure 10 illustrates an RF chipset on a PWB for a receiver, including a configurable RFIC in accordance with an embodiment. The embodiment of Figure 10 shows the most expensive and high performance scenario where all LNAs in the RFIC are configured as external input impedance matching topologies' where input matching is achieved using external input matching components. All configurable LNAs connected to the output of the primary FEM (e.g., RF band output) are configured as external input impedance matching topologies where external matching components are required. Similarly, all configurable LNAs connected to the DIV FEM's diverse outputs (such as RF band outputs) are configured as external input impedance matching topologies, which require external matching components. This means that one or more external matching components on the PWB will be connected between the RF band output of the primary FEM and the appropriate configurable LNA input in the primary interface of the RFIC. Similarly, one or more external matching components will be connected between the DIV FEM's RF band wheel 21 201249116 and the appropriate configurable LNA input in the DIV interface of the RFIC. The configurable RFIC according to the embodiment can be adapted to the customer's desire. Sensitivity can be improved if needed at the expense of using external matching components and increasing the p WB area. Improved selectivity can be achieved to suppress TX leakage or other RF systems (such as 2.4 GHz or 5 GHz connectivity RF). Since the configurable LNA in the RFIC can be matched without external input impedance matching components, the configurable RFIC embodiment provides a cost-effective solution with high quality and reliability. Thus, embodiments provide the ability to trade between price and performance. All of the embodiments exemplified in Figures 4 through 1 can be configured with a single RFI (: implemented, depending on the preferred use of the preferences). As a result, from the lowest cost to a wide variety of wafers with high performance options Group configuration can be covered by the same IC design. Since several mobile device products of different requirements can be covered by the same RFIC, this leads to a more optimized engineering and marketing solution. In the embodiment, one or more Each of the plurality of configurable low noise amplifier circuits includes a switching arrangement. Each circuit is configurable between internal input impedance matching topologies and different topologies via individual switching arrangements. Pak may include a topology that requires one or more external components for input impedance matching. The switching arrangement may include one or more topology switching mechanisms, which may include, for example, switching transistors and/or bias switching Mechanism. The switching arrangement is described below with respect to circles 11 to 20, which switches between multiple pairs of different internal input impedance matching and external input impedance matching topologies. 116 Many different configurable LNA circuits may be employed in the configurable RFIC embodiments described herein. In some embodiments 'internal input impedance matching topologies include common gate low noise amplifier topologies' And the different topologies include a low-stack amplifier topology that senses degradation. The configurable LNA paradigm of such an embodiment is described below with respect to Figures 11 through 3. In some embodiments, the internal input impedance matching topology includes The resistors feed back the low-miss sfl amplifier topology, and the different topologies include the low-noise amplifier topology that senses degradation. The configurable LNA paradigm for this embodiment is described below with respect to Figures 14, 14. In some embodiments, the different topologies include a low noise amplifier topology that senses degradation, and the internal input impedance matching topology includes an impedance matching stage coupled to an input of the configurable low noise amplifier circuit (the impedance matching stage The output provides an input bias for the impedance matching stage and a feedback stage coupled to the output and voltage source of the impedance matching stage (the feedback stage provides compensation operation for the impedance matching stage) The topology behind Bu is called the signal reuse topology. The configurable LNA example of this embodiment is described below with respect to Figure 1! and !6 to 2〇. Each of the configured low noise amplifier circuits includes a common output terminal, and the individual configurable low noise amplifier circuits are provided when the output signals are configured as internal wheel impedance matching topologies or different topologies. This common turn-out terminal. In the case of a non-differential amplifier (such as the positive side of the configurable low noise amplifier of Figure 13), the circuit is configured as [23 201249116 Topology] The output is generated when the output terminal 26 is turned on and the output is also generated in the output ... 6n circuit "and the state is the first. The terminal 260. This single _ wheel: used in two kinds of topologies than needed Solution for multiple output terminals: The solution for cost u is used for the configurable lna itself and other components connected to it. Similarly, the output terminals of single and early gate pairs can be used in the case of differential amplifiers rather than multiple pairs of output terminals for different configurations. The configurable RFIC embodiment in which a plurality of configurable ls are described as described herein is particularly advantageous in that such a common output terminal. Several LNA structures are known which have specific advantages and disadvantages with respect to their noise performance, overall cost, and input matching capabilities. - A known LNA #朴 is an inductively degraded LNA (4). For detailed analysis, it is listed in DK Shaeffer and Τ_Η· Lee's "丨5 volt ι $ GHz CMOS low noise amplifier", / £5. Lu Weng, Volume 32, No. 5 'May 1997, pp. 745-759. An example of an inductively degraded LNA circuit is shown in Figure u. The nna 疋 differential amplifier of Figure n, in which the transistors M2_p and M3_p form the positive or "+" side of the differential amplifier, and the transistors M2_m and M3_m form the negative or "one" side of the differential amplifier. The + and one sides of the differential amplifier are arranged in a cascode configuration in which the transistors M2 p and M2_m, which are arranged in a common source configuration, form a + and one side input (or "gain") respectively. The crystal, and the transistors M3_p and M3_m form a + and - side stacked transistor (or factory current overlap), respectively. In this case, each of the transistors M2_p, M2_m, M3_p, and Μ3_m is an enhancement mode n-channel MOSFET (MOSFET) (also called "NMOS").

S 24 201249116 The differential amplifier amplifies the difference between the two input signals inp, inm applied to its input terminals 220 and 222, wherein the signal applied to the input terminal 222 is the same size as the signal applied to the input terminal 22〇 but A signal with a phase difference of 180 degrees (ie, having the opposite phase). The differential amplifier can amplify the difference between the two signals by rejecting the signal component common to the two input signals. The differential amplifier rejects the signal component common to its two input signals and the difference between the amplified two signals can be measured by the Common Mode Rejection Ratio (CMRR) metric. The gate terminal of the input transistor M2_p on the amplifier + side is connected to the bias source vbias - ldeg via a first bias resistor Rblp. The gate terminal of the input transistor M2_p is also connected to the external matching member via the decoupling capacitor acclp. The input terminal 220 is connected to the external matching member Lextp. The external matching component Lextp is located on a separate circuit or device from the LNA-containing circuitry, i.e., the matching component Lextp is "out-of-chip" (shown in phantom by a dashed circle). In this case, the matching member Lextp is an inductor. Similarly, on the side of the amplifier, the gate terminal of the input transistor M2_m is connected to the bias source vbias_ldeg via the second bias resistor Rb. The gate terminal input of the transistor M2_m is also connected to the external matching member Lextm via the decoupling capacitor acclm. The input terminal 222 is connected to the external matching member Lextm. Again, the matching member Lextm is located off-chip, and in this case an inductor. The gate terminals of the input transistors M2_p and M2-m thus form the input terminals of their individual input transistors. The source and drain terminals of the input transistor M2_p* M2_m thus form the output terminals of the input transistor. 25 201249116 Two input transistors M2 p and M2 m—de-smears. κ From ~ ~ < The source terminal of the mother is connected to a different individual terminal of the inductor Ldeg. The inductor Ldeg is a center-tap differential inductor device with mutual coupling. Inductor

Ldeg provides the induced degradation of the source terminals of the two gain transistors M2 p and ^J2 ΓηΜ, ικ4··τΛΑ - PI. The center tap terminal of the inductor Ldeg is connected to ground. The terminal of the gain transistor M2_p on the differential amplifier + side is connected to the source terminal of the stacked transistor M3_p. Similarly, the terminal of the gain transistor M2_m on the side of the differential amplifier is connected to the source terminal of the stacked transistor M3_m. The gate terminals of the stacked transistors M3-p and M3_m are connected to the circuit voltage supply Vdd (DC voltage) Note that the voltage at the gate terminal Dc can be set to a level other than vdd, resulting in the bucking of the gain transistor M2_p,m The voltage can be set to the desired level to increase the available voltage swing at the terminal of the φ-connected transistor M3-p,m. The drain terminals of the stacked transistors M3_p and M3_m are respectively connected to the output terminal 260. 262 '纟 26〇 is the output terminal of the differential amplifier + side output signal' @ 262 is the differential amplifier - the output terminal that produces the output signal 〇utm, the stacked transistor Μ]』 and the M3_m bungee terminal The voltage supply Vdd is also connected via a configurable load; in this case, the load of the " state includes the inductor 280 and the variable capacitor 270 connected in parallel. The inductor 280 is a center tap differential inductor device And wherein the knives are connected to the voltage supply Vdd. The outputs 260 and 262 of the LNA of Figure 11 are thus connected to a configurable load. The LNA topology shown is typically represented by an input transistor. 26 9 201249116 M2 The noise performance of _p and M2_m is controlled. The noise performance can be improved by optimizing the input matching network (for example, including the benefit transistor _2_ρ and M2_m and the external matching components Lextp and Lextm). The input matching network in front of the input transistor provides a passive voltage gain that can be measured as the voltage swing observed at the gate-to-source termination of the corresponding input transistor (eg, M2_p) and the voltage swing at the LNA input The ratio of the gain. Although this ratio (known in this context as the q value of the input matching network) has a high value, it is beneficial to reduce the buckling current noise of the input transistor M2_p' but it increases the input gate of the input transistor. Extreme current noise. However, the inductively degraded LNA requires several external mating components, Lextp and Lextm, and therefore tends to be more compelling. The second known LNA topology is the common gate LNA, and its detailed analysis has been Listed in Hooman Darabi and Asad A. Abidi, "4.5 mW 900 MHz CMOS Receiver for Wireless Paging", published in the Wuyi State Road Tour Office, Volume 35, Issue 8, August 2000 An example of a common gate LNA circuit is shown in Figure a. Like the inductively degraded LNA of Figure j1, the LNA of Figure 12 is a differential amplifier in which transistors —1-P and M3-p form a positive or differential amplifier The "+" side, and the transistor Ml_m* M3-m forms the negative or "" side of the differential amplifier. The common gate LNA of Figure 12 includes a common gate LNA stage (labeled cg_core in Figure 12), which includes the input. The transistor is supplied with a suitable bias voltage from a voltage source vbias-eg via a bias resistor Rb2p,m. The common gate LNA stage also includes a stacked transistor M3_p,m and an inductor 25〇p,m. The common gate LNA stage of Figure 12 also includes a capacitor cfbp,m between the gate 27 201249116 of each input transistor and the output source terminal. The external matching members Lextp and Lextm are not provided in the common gate LNA of FIG. The input transistors M1_p and M1_m are thus directly connected to the input terminals 22A, 222 via decoupling capacitors acc2p and acc2m, respectively. The external matching component is not required to match the impedances of the input terminals 22A and 222 (where the impedance to be matched is, for example, the RF filter output impedance in front of the LNA), and the common gate a of Figure 2 can instead be in the LNA. The impedances connected to the input terminals 22A and 222 are internally matched. For example, the common gate LNA shown by circle 12 has the ability to match internal input impedance because the impedance at the input transistor source is inversely proportional to the mutual conductance %. Typically, the single-ended termination impedance is 5 ohms, so a mutual conductance of approximately 20 mS is required. A large impedance to the signal ground is required to direct the signal to the source terminal of the input transistor, which can be achieved by a source of current connected to the individual source node. However, the current source is not typically used, which is due to the poor performance of the associated noise and the fact that stacking several transistors can lead to technical limitations. The preferred noise performance is achieved by using the inductor 25 〇p,m at the input source node, as shown in Figure 30. In the case of perfect impedance matching (l/gm = Rs), the power gain of the common gate low noise amplifier becomes the part of the output load to source impedance, ie Zl / Rs. This assumption is true if the input-to-source resistance of the input transistor is much larger than the load resistance at the individual terminal. Achieving high voltage gain patterns can be challenging because the voltage gain of the very low noise amplifiers in common is limited by the ratio of load/source impedance. Furthermore, the need for high output impedance also requires special attention when designing the interface. 28 201249116 > The minimum noise index for a perfectly matched common gate lna presented by the prior art is NF = 10 lg(l + r /α ) = 10 lg(5/3) = 2 2 decibels. For short channel devices, the noise parameter r can be large: one', and α can be much smaller than...the actual achievable noise index tends to be around 3 decibels or greater. This means that the noise index of the common gate LNA is slightly higher than the common source LNA system of induced degradation. In summary, the common gate LNA can provide wideband matching without external matching components. In addition, the common interpole LNA provides good linearity. Furthermore, if two independent source inductors are used, the common mode also achieves a good input match' which also results in good common mode linearity. Compared to the induced degradation of the graph, the common (four) pole LNA has poor noise performance; depending on the application, it can pay special attention to the interface design. Embodiments Regarding an LNA circuit, which can be configured between the top: topology and the second topology, H's low noise amplifier circuit includes a degraded inductor stage. : causes the low noise amplifier circuit to operate as a low noise amplifier that senses degradation; and the second topology of the low noise amplifier circuit includes a common gate low noise amplification HI 'causing low noise amplifier A|f circuit operation to become common Closed low noise amplifier. In the first-topology, & match the input impedance, the external matching component is used in conjunction with the LNA. For the second topology, the components inside the lna topology are used for input impedance matching; the second topology does not require external matching components. Input impedance matching, for example, may involve matching an RF filter output impedance connected to one or more inputs of [ΝΑ. An example of a configurable LNA circuit in accordance with the present invention is illustrated in FIG. Like the LNA of Figure 12, the example of the LNA of Figure 13 is differential amplification ,-,.. 29 201249116 'where the transistors Ml_p, M2-p, M3_p form the positive or "+" side of the differential amplifier, And the transistors Ml_m, M2_m, M3_m form the negative or "one" side of the differential amplifier. The configurable LNA circuit example of Figure 13 includes a common gate LNA stage (labeled cg_core) in accordance with the common gate LNA stage of the circuit of Figure 12. The topology of the configurable LNA of Figure 13 necessarily includes some features similar to the inductively degraded LNA of Figure 11 and the common gate LNA of Figure 12; however, there are several important differences, including the following: The configurable LNA of Figure 13 includes a handover arrangement to configure the LNA between the first topology and the second topology. The switching arrangement includes a topology switching mechanism, in this case switching transistor SW1 p,m, which is connected between the output and the input of the degraded inductor stage of the configurable LNA. In this case, the source terminal of swip,m is connected to the source terminal of the input transistor μ 1 p,m of the common gate LNA stage, and the drain terminal of SWlp,m is connected to the decoupling capacitor acc2p, n^ switching The source terminals of the transistors SWlp,m are also connected to the source terminals of the input transistors M2_p,m of the inductively degraded LNA stage. The gate terminal of the switching transistor SWlp,m is connected to the configuration control signal terminal, for example, as shown in Fig. 3 as xLdeg. The first 'is not a degraded LNA according to FIG. 11 but a degenerate inductor on each side of the differential amplifier, and is not a source of the input transistor Ml-p,m on each side of the differential amplifier according to the common gate LNa level of FIG. The pole including the inductor 'the configurable LNA of Figure 13 instead includes only the inductor 250p,m. In addition, the inductor (Ldeg) in the circle 11 includes a single center tapped inductor, while Figures 12 and 13 have two separate inductors 250p, m. These inductors 30 201249116 are shared between the first and second topologies and are usefully used when the configurable lNa system is configured for any topology. The use of such components helps to reduce cost and die area. By applying the appropriate configuration control signal to the configuration control terminal xLdeg 'switch transistor swlp, m can be turned on (by which the configurable LNA of Figure 3 is configured as the first topology) and off state (Through this configurable LNA of Figure 13 is configured as a second topology). The configurable LNA can be configured according to the intended use. Sensitivity can be improved in the first, inductively degraded configuration, if desired, but at the expense of external matching components. However, since the configurable LNA of the second, common gate configuration can be matched without the need for external input impedance matching components, a cost effective solution is provided. Second, the common gate configuration also provides better linearity than the first, inductively degraded configuration. Thus the embodiment provides the possibility of trading between price and performance. The first and second topologies that can be configured by the configurable LNA using the topology switching mechanism will now be described in more detail. When in the on state, the switching transistor provides a high resistance between its drain and source terminals, which effectively disconnects (or "opens") the drain and source terminals. The switching transistor can be placed in an on state by applying an appropriate control signal to an individual configuration control signal terminal such that the voltage (ie, voltage Vgs) between the gate terminal and the source terminal of the switching transistor is less than (or It is almost less than the threshold voltage of the switching transistor (i.e., voltage Vt), that is, the switching transistor can be described as being in the off mode. The configuration control signal for configuring the switching transistor to be turned on may include, for example, a digital "〇" signal (e.g., packet 31 201249116 including the first voltage level signal). When in the off state, the switching transistor provides a low resistance ' between the drain and the source terminals' which effectively connects (or "shorts") the drain and source terminals. The switching transistor can be placed in a closed state by applying a configuration control signal to its control signal terminal. [The voltage between the gate terminal and the source terminal of the switching transistor (ie, voltage vgs) is greater than the threshold of the switching transistor. The voltage (i.e. voltage vt), i.e. the switching transistor, can thus be described in the triode mode. An example of a configuration control signal for configuring the switching transistor to be in a closed state may include a digital "1" signal (eg, a signal including a second voltage level). In the first topology, the switching transistor S\v 1 P,m is configured to be in an open state. The switching arrangement also includes a first bias switching mechanism adapted to set the bias voltage vbias-ldeg to a relatively high or relatively low bias voltage. The low noise amplifier circuit that can be configured is configurable to the first topology by using the first bias switching mechanism to set the bias voltage vbias_ldeg to a relatively high bias voltage. Applying a relatively high bias voltage to the inductively degraded LNA stage input transistor M2_p, m biases the M2_P'm transistor to the off state. Which constitutes a relatively high bias voltage depends on the transistor technology used. Typically, a relatively high bias voltage includes a voltage in the vicinity of one-third to one-half of the supply voltage, although voltages outside this range may be employed. In an embodiment, the supply voltage is 1 25 volts and the relatively high bias voltage is 450 to 500 millivolts. The switching arrangement also includes a first bias switching mechanism adapted to set the bias voltage vbias-eg to a relatively high or relatively low bias voltage. The configurable low noise amplifier circuit is configurable to the first topology by using a second bias switching mechanism to set the bias voltage vbias_cg to a relatively low bias voltage. Apply lower

S 32 201249116 The input transistors Ml-p, m biased to the common gate LNA stage bias the Ml_p,m transistor to the on state. A relatively low bias voltage can include, for example, a zero bias voltage. By displacing the switching transistor SW1 p,m into an on state and biasing the input transistor M1_p,m of the common gate LNA stage to an on state, the source of the input transistor M2_p,m of the inductive degradation stage is sensed The terminals are connected via inductors 250p,m. The inductor 250p,m thus provides induced degradation of the source terminal of the input transistor m2p' as induced degradation Lna of Figure 11. When the switching transistor SW 1 p,m is switched to the on state, i.e., when the configurable LNA is configured as the first topology, the configurable lna thus operates as an inductively degraded LNA. Thus, when configured as a first topology, the configurable LNA does not provide internal input impedance matching, such as matching the output impedance of the preceding RF filter connected to input terminals 22A and 222. As a result, the input impedance of the configurable LNA of Figure 13 can be matched to the previous RF filter, for example, by connecting an appropriate external impedance matching component. The external matching member may, for example, include external matching members Lextp and Lextm connected between the decoupling capacitor acclp'm and the input terminals 220 and 222, respectively. While the first topology of the configurable LNA of Figure 13 thus provides at least some of the benefits of the inductively degraded LNA of Figure u, including relatively low noise indices, external matching components are required to provide input impedance matching. In the second topology, the switching transistor swip, m is configured to be in a closed state. The configurable low noise amplifier circuit is configurable in the second topology of 33 201249116 by using a first bias switching mechanism to set the bias voltage vbias deg to a relatively low bias voltage. Applying a relatively low bias voltage to the inductively degraded input transistor M2_p, m biases the M2-p, m transistor to the on state. The configurable low noise amplifier circuit is configurable to the first topology by using a second bias switching mechanism to set the bias voltage vbias_cg to a comparative bias. Applying a relatively high bias voltage to the input gate crystal M1_p'm of the common gate lnA stage biases the Mi_p,m transistor to the off state. By configuring the switching transistor SWlp,m to be in a closed state and biasing the input transistor Ml_p,m of the common gate LNA stage to the off state, the source of the input transistor M1_p,m of the common gate LNA stage The pole terminal is connected via an inductor 250p,m, which is connected to ground. The inductor 25 〇 p, m connected to the source terminal of the input transistor M1_P,m is high impedance k at the operating frequency and operates as a DC current path for the second topology to ground. The inductors 250p,m remain in the circuit in both the first topology and the second topology, rendering the embodiment an expensive (in terms of area) integrated inductor area for two different (four). The same integrated inductor is used as a degenerate inductor in the inductive degradation topology and as a DC feed inductor in a common gate LNA topology. The use of a single inductor for two topologies avoids one topology requiring an expensive on-wafer component and the other topology requires another expensive on-wafer component. The configurable LNA of Figure 13 thus provides an LNA that can be configured according to the intended use or design requirements. If a more sensitive LNA is required and a better noise index is available, the LNA can be configured to The cost of an extension is that external matching components, such as Lextp and Lextm, are required to provide impedance matching for the input of the configurable 34 201249116 LNA. Alternatively, the lna can be configured as a second topology to provide a better linear and more cost effective solution. A further known LNA topology is a resistor feedback (or "shunt resistor" LNA, whose detailed analysis is listed in C F. LU〇 and si. [ than for the 3. 1 to 10.6 GHz UWB receiver. Broadband Noise Cancellation CM〇s lna"' MM 思靡雹路谤, Book 42, No. 2, February ,, 329-339. Examples of resistance feedback LNA circuits are shown in Figure 4. Like the inductively degraded LNA of Figure ii, the LNA of Figure 14 is a differential amplifier in which transistors 200 and 210 form the positive or "+" side of the differential amplifier, and transistors 202 and 212 form a differential amplifier. The negative or "_" side. There are several differences between the topology of the resistor-backed LNA in Figure 14 and the topology of the inductively degraded lNA in Figure n, which include the following: First, the inductor Ldeg (which provides the graph n The inductive degradation of the source transistor M2-p, the source terminal of the inductively degraded lNA does not appear in the resistor feedback LNA of Figure 14. The source terminal of the input transistors 200 and 202 of the resistor feedback LNA of Figure 14 is directly Connected to ground. The first 'output terminal 260 (ie, the output terminal of the differential amplifier + side) is fed back The resistor 300 is connected to the input terminal 22 (i.e., the input of the differential amplifier + side). Similarly, the output terminal 262 (i.e., the output terminal of the differential amplifier side) is connected via the feedback resistor 3〇2. The input terminal 222 (i.e., the input terminal on the side of the differential amplifier). The feedback resistors 3A and 3〇2 respectively provide resistance feedback to the + and - sides of the differential amplifier. Third 'these LNA topologies The important difference is the input matching frequency 35 201249116 configurability. In the resistance feedback topology, the best input matching frequency follows the output swing of the output. When the gain in the resistance feedback output is adjusted by applying to the output When the resonator is loaded and set to the desired frequency, the input matching is observed at the same frequency. This can be understood by calculating the input impedance value of the resistance feedback topology, which is almost by &)〆, (l+Gm ZL) is defined as "the feedback resistance value, & is the load impedance, and Gm is the mutual conductance of the input device. This is in contrast to the input matching of the inductive degradation through the topology, which is generally more fixed at a particular frequency. Thereafter, the external matching members Lextp and Lextm are not provided in the resistor feedback LNA of Fig. 。 The input transistors 20 "σ 2〇2 are thus directly connected to the input terminals 220 and 222 via decoupling capacitors 240 and 242, respectively. The external matching member is adapted to match the impedances of the input terminals 22 and 222 (wherein the impedance to be matched is, for example, the output impedance of the RF filter in front of the LNA), and the resistance feedback lna of FIG. 4 can be internally matched in the LNA. The impedance is connected to input terminals 220 and 222. Since the resistor feedback LNA of FIG. 14 does not have external matching components Lextp and Lextm to provide passive voltage gain before capacitors 240 and 242 'as described above for the induced degradation LNA of FIG. ', the input transistors 200 and 202 are not mitigated. Noise effect. In addition, the resistor feedback LNA of Figure 14 has an additional source of noise due to the feedback loop between the output terminals 260 and 262 and the input terminals 220 and 222. At the same time, the input reference noise from the configurable load and feedback loops increases as the resistance of the feedback resistors 300 and 302 decreases. In general, the noise performance of the resistor feedback LNA is compared to the graph.

The inductively degraded LNA of S 36 201249116 11 is poor. However, since the resistor feedback LNA of FIG. 4 does not require the external matching member Lextp and [the inductor Ldeg for the induction degradation does not need to be added, the overall cost of the resistance feedback LNA of Η μ is compared with the induction of FIG. Degraded LNA is lower. Embodiments relate to an LNA circuit configurable between a first topology and a second topology: the first topology of the low noise amplifier circuit includes a degraded inductor, causing the low noise amplifier circuit to operate as a low-inductance degradation The second topology of the low noise amplifier circuit includes a feedback resistor, causing the low noise amplifier circuit to operate as a resistor feedback low noise amplifier. In the first topology 'to match the input impedance', the external matching member is used in conjunction with the LNA. In the second topology, the internal components of the LNA topology are used for input impedance matching; the second topology + external matching components. The ~impedance matching example can refer to an rf chopper output impedance that is matched to one or more inputs connected to the LNA. An example of a configurable LNA circuit in accordance with the present invention is illustrated in FIG. LNA of 5 1 and 14 'The LNA example of Figure 15 is a differential amplifier. The neutral day and the body 200 and 210 form the positive or "+" side of the differential amplifier, and the transistor 2〇2# 212 forms a differential amplifier. Negative or "-" side. Η $ The topology of the configurable LNA of Figure 15 necessarily contains some features similar to the low noise amplifier of Figure 11 induced degradation and the resistance of Figure 14 resistance feedback lna, however there are several important differences, including the following:

The configurable LNA of Figure 15 contains the switching arrangement to configure the LNA between the flute | person topology and the second topology. In an embodiment, the switching arrangement package a many topological switching mechanisms. 37 201249116 Second, similar to the resistor feedback LNA of Figure 14, the settable LNA of Figure 15 includes a feedback resistor 3〇〇 on the differential amplifier + side. However, the feedback resistor 3 on the differential amplifier + side is not directly connected to the input terminal 220, and the feedback resistor 300 is instead connected to the topology switching mechanism, in this case switching the transistor 400, which in turn is connected to the input. Terminal 22〇. One of the drain terminal and the source terminal of the switching transistor 400 is coupled to the feedback resistor 300' and the other terminal is coupled to the input terminal 22A. The gate terminal of the switching transistor is connected to the configuration control signal terminal 42A. The topology switching mechanism 400 is thus connected (via decoupling capacitor 24A) between the gate of the input transistor 2A and the feedback resistor 300. The third 'similar to the resistance feedback LNA of Fig. 14, the configurable LN A of Fig. 15 includes the feedback resistor 3〇2 on the side of the differential amplifier. However, the feedback resistor 3〇2 on one side of the differential amplifier is not directly connected to the input terminal 222, and the feedback resistor 3〇2 is instead connected to the topology switching mechanism, in this case switching the transistor 402, which in turn Connected to the input terminal 222. One of the drain terminal and the source terminal of the switching transistor 402 is coupled to the feedback resistor 302' and the other terminal is coupled to the input terminal 222. The gate terminal of the switching transistor 4〇2 is connected to the configuration control signal terminal 423. The topology switching mechanism 402 is thus connected (via decoupling capacitor 242) between the gate of the input transistor 2〇2 and the feedback resistor 302. The fourth 'similar to the inductively degraded LNA of Figure 11, the inductor 250 appears in the configurable LNA of Figure 15. A fifth 'topology switching mechanism (in this case, switching transistor 4 1 〇) is connected between the source terminals of the input transistors 200 and 202. Switching transistor 4 i 〇

One of the drain terminal and the source terminal of S 38 201249116 is connected to the source terminal of the input transistor 200, and the other terminal is connected to the source terminal of the input transistor 202. The gate terminal of the switching transistor 410 is connected to the configuration control signal terminal 42 5 . The sixth 'decoupling capacitors 430 and 432 provide DC decoupling from the supply voltage to increase the switching performance of the switching transistors 400 and 402, respectively. By applying appropriate configuration control signals to the configuration control terminals 42 i, 423, 425, the switching transistors 400, 402, 410 can be turned on (by which the configurable LNA of Figure 15 is configured as the first Switch between the topology and the off state (by which the configurable LNA of Figure 15 is configured as a second topology). The first and second topologies that can be configured by the configurable LNA using the topology switching mechanism will now be described in more detail. The first topologies 'switching transistors 400, 402, 4' are configured to be turned on. By configuring switching transistors 400 and 402 to the on state, feedback resistors 300 and 302 are effectively disconnected from the input signals applied to input terminals 22 and 222, respectively. As a result, there is no feedback loop between the output terminals 26A and 262 and the input terminals % 2 2 0 and 2 2 2, respectively. By configuring the switching transistor 410 to be in an on state, the source terminals of the input transistors 200 and 202 are operatively coupled only via the inductor 250 (whose center tap is connected to ground). Inductor 250 thus provides induced degradation of the source terminals of input transistors 2A and 202, such as the induced degradation lna of Figure u. When the switching transistors 400, 402, 4 10 are switched to the on state, that is, when the configurable LNA is configured as the first topology, the configurable LNA thus operates as an inductively degraded LNA. 39 201249116 Therefore 'when configured as a TOP-topology, the configurable LNA does not provide internal f-input impedance matching, for example matching the output impedance of the RF filter at the input terminals connected to input terminals 220 and 222, As a result, the input impedance of the configurable LNA of _1 5 should be such as by connecting external impedance matching components (e.g., external matching components 230 and 232) between the decoupling capacitor 242 and the input terminals 220, 222, respectively. The induction of n degenerates lna, while matching the RF filter in the front. Although the first topology of the configurable LNA of Figure 15 thus provides the benefit of the inductively degraded LNA of Figure u, i.e., a relatively low noise index, an external matching component is required to provide input impedance matching. The second topology 'switching transistors _, 402, 410 are configured to be in a closed state. By switching the switching transistors 4A, 4〇2 to the off state feedback resistors 3GG, 3G2, they are operatively connected to the input terminals 22() and 222, respectively. ,. The feedback loops are present between the output terminals 260 and 262 and the input terminals 220 and 222 (and thus the input terminals of the input transistors 200 and 202 via the depletion capacitors 24A and 242, respectively). When the standby switching transistors 400, 402, 410 are configured to be in a closed state, that is, when the configurable LNA is configured as a second topology, the configurable LNA thus operates as a resistance feedback lNA. Thus, when the field is configured to a second topology, the configurable lNA provides internal input impedance matching, such as matching the output impedance of the preceding RF filter connected to input terminals 22A and 222. As a result, when the configurable LNA is configured for the second configuration, no external matching components are required, such as the external matching components shown in the figure " Inductive Degraded LNA [to print and [to add. 40 5 201249116 When the configurable LNA of Figure 15 is configured as a second topology, the switching transistor 410 is configured to be in a closed state; this provides additional benefits, as will now be described. The switching transistor 41 is effectively connected by configuring the switching transistor 41A to be in the off state 'the source terminals of the input transistors 200 and 202 (i.e., the switching transistor 41 between the source terminals of the input transistors 200 and 202). The connection formed by 〇 is connected in parallel to the inductor 250, which is connected to the source terminals of the input transistors 2〇〇 and 2〇2. As in the inductively degraded LNA of Fig. 11, the inductor 250 is a differential inductor having mutual coupling The mutual coupling of the differential inductor devices causes the inductor to perform different operations on the common mode signal applied to the differential amplifier. Compared to the differential mode signal applied to the differential amplifier, the inductor is applied to the differential amplifier applied to the differential amplifier. The common mode signal is a signal component having the same size and phase as the individual input signals applied to input terminals 220 and 222. In contrast, the differential mode signal has the same individual input signals as applied to input terminals 220 and 222. Signal components of size and opposite phase. For differential mode signals applied to input terminals 220 and 222, when the configurable LNA is configured as a second topology, The connection formed by the switching transistor 41A between the source terminals of the input transistors 200 and 202 forms a virtual ground for the differential signal. However, 'with respect to the common mode % number applied to the input terminals 220 and 222, When the configurable LNA is configured as a second topology, the inductor 25 〇 remains active 'while at the source terminal and ground of the input transistors 2 〇〇 and 202 (the 41 201249116 is connected to the inductor 250 The inductance provided between the center taps is equivalent to: (1 - k) / 2 * x Ln (i) where k 疋 inductor 250 has a mutual face factor ' and Ln is a nominal inductance based on the electrical length of the inductor 250 Thus, when the configurable LNA is configured as a second topology, the inductor 250 forms an impedance with respect to the inductance provided by the common mode signal (according to equation (i) above), which is used to attenuate the supply from the ground voltage. Interference and other noise. Therefore, when the configurable LNA is configured as a second topology, the power supply's noise rejection performance is improved, such as by a higher power supply rejection ratio (PSRR) metric. Demonstration by law. When configurable [ΝΑ乃Configuration When the second extension Park, degeneration inductor inductor 250 provided therefore adapted to provide power supply noise rejection filter impedance LNA topology degradation by induction from "borrow" (b〇rrowing) inductor

The Ldeg' configurable LNA enables this PSRR improvement to occur in the resistor feedback LNA topology. The "borrowing" inductor Ldeg also ensures that the components on the wafer from the first topology of the configurable LNA (in terms of die area) are two configurations for the configurable LNA. In addition, when the configurable LNA is configured as a second topology, the inductor 250 forms a source for wheeling the transistors 200 and 202 with respect to the inductance provided by the common mode signal (according to equation (1) above). Degraded inductor of the terminal. As with the inductively degraded LNA described above with respect to Figure 11, such degraded inductors are used to improve the rejection performance of the common mode when the configurable lna is configured as a second topology' as exemplified by the higher CMRR metrics. When the stackable LNA is configured as a second topology, the degraded inductance provided by the inductor 25 is thus adapted to provide a common mode with respect to the signal components common to the input signals applied to the input terminal 42 and 42 201249116 222 The signal rejects the impedance. By "borrowing" the inductor Ldeg from the inductively degraded LNA of Figure 11, the configurable LNA enables such CMRR improvement to occur in the resistance feedback lNA topology. The "borrowing" inductor Ldeg also ensures that the components on the wafer from the configurable [on the first topology of the expensive (in terms of wafer area) are for the configuration of the configurable LnA. The configurable LNA in Figure 15 therefore provides an LNA that can be configured according to the intended use or design requirements. If a more sensitive Lna with a better noise index is needed, the LNA can be configured as a first topology at the expense of requiring one or more external matching components, such as Lextp and Lextm, to provide for grouping. The impedance of the input of the lNA of the state is matched. Alternatively, the LNA can be configured into a second topology to provide a more cost effective solution. In addition, when the configurable LNA is configured as a second topology, the use of inductor 250 provides an improved LNA's PSRR* CMRR over the resistance feedback LNA of Figure 14. This results in the reuse of inductor components on expensive wafers that can consume configurable significant wafer area. Embodiments are directed to providing an input impedance matching capability without the need to use an external input impedance matching component LNA topology. This topology is referred to herein as the "signal reuse" topology, the reasons of which will be explained below with reference to Figures 16-18. The signal re-use LNA has a wideband match for the differential mode signal and the common mode signal. Therefore, the common mode signal also maintains a good differential 43 201249116 Linear. Another gain stage connected in parallel to the input impedance matching stage increases the LN a gain. The amplified signal at the output of the input impedance matching stage is then used to reduce the noise contribution of the subsequent transistor. In addition, the signal can be biased using the LNA without the need for a large value AC coupling capacitor input at the LNA. The noise index is higher than the inductively degraded LNA because of the lack of passive voltage gain before the signal is re-used with the LNA input stage. Furthermore, there is an additional source of noise in addition to the gain transistor. However, since the signal re-use LNA requires neither external components nor additional source inductors on the wafer for input impedance matching, the overall cost is much lower compared to the inductively degraded LNA. The signal then uses topology to provide a cost-effective solution. The example of a particular embodiment of the present disclosure achieves a high gain, thus reducing the noise contribution of the level of interest behind the LNA. This can be seen when applying the Friis equation: the noise factor of the subsequent components is divided by the power gain of the previous LNA. The example of a particular embodiment of the differential [ΝΑ] provides good input impedance matching over the wide bandwidth of the differential mode signal and the common mode signal, which in turn results in good common mode linearity. The LNA according to some embodiments has compensated for effects such as temperature, process, corners, aging, etc., and there is no limit when selecting an interface to the mixer and analog baseband components. In some embodiments, LNa no longer requires a direct current (DC) coupling capacitor for input to the transistor device; this results in the use of a smaller die area when compared to prior art LNAs. Fig. 16 is a diagram showing one or more stages of the side of the differential amplifier of [να] according to the embodiment. The particular feature of the differential amplifier is omitted, such as coupling the other side of the differential amplifier to ground, preferably.

S 44 201249116 Conceptual aspects of the exemplary embodiment. The stage shown in Fig. 16 has a signal inp applied to the input terminal 220. The input terminal is fitted to the impedance matching stage 4 1 〇. The role of the impedance matching stage 41 0 is to match the input impedance seen at the input terminal 2 2 '. For example, one or more components of the impedance matching stage 410 may have a combined impedance that matches the upstream of the LNA Any impedance of the receiver processing stage (eg front-end module, rf filter, duplex filter, etc.). Input terminal 220 is further electrically coupled to gain stage 42A, i.e., impedance matching stage 4 1 0 and gain stage 420 are coupled in parallel to input terminal 220. The gain stage 420 with the impedance matching stage 4 10 increases the gain of the LNA. As with the relative dimensions of the stages of Figure 16, the gain of the gain stage 420 is greater than any gain provided by the impedance matching stage 4 10 . The gain stage 4 2 is integrated with the output terminal 26 that produces the output signal outp. The output of impedance matching stage 4 10 (node a) is coupled to feedback stage 43A. The output of the impedance matching stage 410 also contributes to the output 〇utp of the system, which in this example is via the second gain, signal processing or signal re-use stage 44〇. In other embodiments, impedance matching stage 410 can be coupled to output terminal 26 without signal reuse stage 440, such as via other components that maintain high impedance at node A, causing LN A to still have proper impedance matching. The outputs of the signal re-use stage 440 and the gain stage 420 of the circle 1 & are combined to produce an output signal outp. This can be achieved by coupling the output of the secondary to node B, so that the two output current signals are constructively combined. In some embodiments, the gain stage 420 and the signal reuse stage 44A share the same DC current path, thus optimizing the current consumption of the LNA. 45 201249116 By coupling the output of the impedance matching stage 410 to the output terminal 26 (e.g., via the signal reuse stage 440), it can be said that the result of the impedance matching stage 41 is "re-used", that is, subsequently used to generate the amplifier. The output, in this example, is via a further gain stage. For example, impedance matching functionality of impedance matching stage 4 10 may be provided without electrically coupling impedance matching stage 41〇 to output terminal 260, such as without any coupling between node a and node B. In a particular embodiment, the signal processed by the impedance matching stage 41 (and in some cases amplified) is used to reduce the noise contribution provided by one or more transistors implementing the LNA, ie, The contribution of noise factors. For example, the amplification provided by the impedance matching stage 4 1 0 reduces the noise contribution of the subsequent stages of ln A (such as, in particular, current buffer or load stage). In a particular embodiment, a current buffer stage (not shown) may be provided prior to output, i.e., between node B and output terminal 260. This buffer stage buffers the current signals from gain stage 42〇 and signal reuse stage 440. In various embodiments, the conceptual features of Figure 16 are typically replicated on the second side of the differential amplifier for inputting the signal inm. The feedback stage 430 is used in some embodiments 'impedance matching stage 410. The example 'return stage 430' of Figure 16 includes a feedback amplifier, however other functionally similar feedback arrangements with or without gain can be used for other implementations. The output of impedance matching stage 410 (which may include current and voltage at point a) is coupled to the inverting input 434 of the feedback amplifier. An embodiment of the feedback amplifier (labeled X1 in the figure) is shown in more detail in FIG. The non-inverting input 432 of the amplifier is coupled to a voltage source 435 that provides a configurable bias voltage vbias. Bias vbias can be internal or external

S 46 201249116 Generated bias voltage (from an integrated LNA point of view). For example, it can be generated using resistors and a fixed current. It can also use a current or voltage reference that is proportional to absolute temperature (PTAT) to accommodate temperature changes. The output 436 of the feedback stage 430 is coupled to a bias voltage 415 for the impedance matching stage 4 1 〇 ', i.e., the voltage is used to set the operating point of the impedance matching stage 4 1 。. Therefore, the feedback provided by the feedback stage 430 during use and over time sets the (DC) voltage at node A to the applied bias voltage vbias. For example, this can achieve a steady state operation. In a particular embodiment, the voltage at node A defines the input bias for impedance matching stage 410 and gain stage 420 (see description of Figure 18 below). This has the advantage of avoiding the use of any AC coupling capacitors and bias resistors to bias the input voltages of stages 410 and 420, thus reducing the cost and size of the integrated LNA. The feedback stage 430 compensates for temperature and corner variations in one or more of the transistor devices that make up the LNA, such as a transistor that implements an impedance matching stage. By varying the bias voltage 41 5 of at least the impedance matching stage 4 1 0, the LNA can compensate for corner effects and aging. This is important in mass-produced circuits (ie, mass-produced LNAs) where the circuit must be robust to compensate for mass production processes. The changes inherent in it. The feedback stage 430 is also capable of configuring the LNA for optimal performance to improve productivity, such as by compensating for at least one of variations in performance, temperature, aging, and the like. An alternating current (AC) coupling capacitor or bias resistor that does not require a large value at the input to the LNA can be provided by using the feedback stage 'which can provide an input bias for impedance matching stage 4 1 0 and gain stage 420'. Since large-value AC-coupling capacitors are typically large in size, this further avoids the need for large grain areas. In addition, the lack of bias 47 t··, 201249116 piezoresistance n leads to the performance of the noise factor in the case of blocking. Figure 17 shows an implementation of the feedback stage 430, which is exemplified as suitable for the LNA of Figure 18 below. This implementation uses feedback amplifier XI to provide feedback functionality in a common mode. The non-inverting input 432 of amplifier X1 is coupled to a voltage source such as source 435 of Figure 16, which provides a configurable bias voltage vbias. The output 436 of the feedback stage 43 0 is coupled to the bias voltage 415 for the (p-channel MOSFET, abbreviated as pM〇s system) transistor to implement the impedance matching stage 41 (μρ hall bias p_- The vbias and common mode feedback inputs Cm-fb can be coupled to the equivalent of Figure 18, as described below. The common mode feedback circuit X1 compensates for the temperature of one or more of the transistor devices (e.g., NMOS transistors) that make up the 1NA. And corner variations. By changing the PMOS bias M pm 〇 s_vbias, the NM0S / PM 〇s ratio can be kept constant under different effects of temperature, aging and process. As mentioned above, this provides a more robust solution. Specific circuit implementations of embodiments of the present disclosure will now be described with reference to Figure 18. It should be noted that the LNA may also vary while maintaining the same functional effects, for example, a resistor or may be replaced by two series resistors. , or the components may be rearranged while still maintaining an equivalent circuit. Therefore, the specific circuit implementation of Figure i 8 should not be considered limiting. The LNA circuit of Figure 18 has two sides 6〇5 and 61〇, which together form Differential amplifier The differential side 605 is arranged to process the input efl number inp provided at the terminal 22, and the differential side 10 is arranged to process the input signal inm provided at the terminal 222. The differential side 605 produces an output signal at the output terminal 260. 〇utP, and the differential side 610 produces an output signal (10) plus at the output terminal 262.

S 48 201249116 The topology of Figure 18 is symmetrical 'that is, the configuration of the first differential amplifier side 6〇5 is replicated on the second differential amplifier side 6丨〇. The first differential amplifier side 6〇5 may be on the non-inverting, “+” or positive side of the LNA, and the second differential amplifier side 610 may be in relation to the LNA inversion, “―” or negative side (or vice versa) Also). Although the following description will only discuss the first differential amplifier side 6〇5 in detail, the functionality is equally applicable to the corresponding second differential amplifier side 6丨〇. In a particular embodiment, the functionality of the first differential amplifier side can be additionally selected to be implemented without the second differential amplifier side to provide a single-ended amplifier. The impedance matching stage of Figure 18 (e.g., stage 4 10 of Figure 16) is implemented by transistors M 1_P and M3 - p and feedback resistor Rfb. In this example, the transistor M1 - p is an NMOS transistor, and the transistor M3_p is a PMOS transistor. The transistors M1_p and M3_p form a feedback portion of the LNA. The gate terminal of the transistor M1_P is coupled to the input terminal 220. The source terminal of transistor Μ1 _p is coupled to ground. The drain terminal of the transistor Μl_p is consumed via the node a to the drain terminal of the transistor M3_p. The source terminal of transistor M3_p is consuming the voltage supply Vdd. The gate terminal of transistor M3_p is coupled to input terminal 220 via Ac-light capacitor accl-p and is also coupled to pmos_vbias (pM〇S bias provided by feedback amplifier XI) via resistor Rpv. The AC coupling capacitor accl_p enables the AC signal to pass from the input terminal 220 to the gate of the transistor M3_p but blocks any dc components, thus isolating the DC bias seen at the gate of the transistor M3_p and in the transistor M1-P The DC bias seen by the gate. This enables the DC bias seen at the gate of transistor M3_p to be set by pmos_vbias. For this example, applying a pM〇S bias pmos_vbias to the gate of PMOS transistor M3_p applies a bias of 49 201249116 to impedance matching stage 410, as described above with respect to FIG. The function of the resistor Rpv is to separate the two differential amplifier sides 6〇5 and 61〇 (i.e., P and m). Without this resistor on each side of the differential amplifier, the PM0S gate on each side of the differential amplifier is shorted via the M3-P and gate connections. In the example of Figure 18, pm〇s_vbias is coupled to the output pmos-vbias of amplifier XI, as shown in Figure 17. The same pm 〇 s - is also applied to the other differential side, ie the two pm 〇 S-Vbias nodes are coupled to the pmos_vbias output of the feedback amplifier XI. In order to provide their AC coupling function, the AC coupling capacitor accl_p only has to have a small capacitance, for example less than IpF. This minimizes parasitic capacitance at critical nodes of the circuit and minimizes the cost and die area required for circuit capacitors. The mutual conductance and feedback resistors Rfb of the devices M1_p and M3_p match the input impedance of the LNA of Figure 18 to the desired source impedance. For example, for a particular implementation, the input impedance can be a 100 ohm differential, a single end of 5 ohms. Node A can be viewed as the output of the impedance matching stage implemented by transistors M1_p and M3-p and feedback resistor Rfb. Node A also meets the common mode feedback input cm-fb of amplifier X1 via resistor Rem, as shown in Figure 17, "any voltage signal at node A is sensed using resistor Rem without disturbing the presence of node A. Any AC signal. This provides a voltage input signal cm_fb for the feedback amplifier ,ι, as shown in FIG. The bias voltage Vbias is applied to the amplifier 如上ι as described above. The feedback amplifier χι' implementing the common mode feedback stage 43 0 functions to modify the pM〇s bias signal pmos_vbias (which biases the PMOS transistor M3-!) (for example, by setting the voltage at the gate of the transistor) Setting the operation of the transistor 50 201249116 point)) 'The voltage at the node cm_fb is equal to the bias voltage vbias when used. Since the voltage at node A defines the input bias for μ l_p and the input bias for gain transistor M2_p (described below), the input bias for impedance matching stage 4 10 and gain stage 420 is This example is based on vbias. The gain stage of Fig. 18' is implemented by the gain transistor M2_p of the differential amplifier side 605 and the gain transistor M2_m of the differential amplifier side 61 。. In Figure 18. These transistors are NM〇s transistors. The gate terminal of the gain transistor M2_p is coupled to the input terminal 220. Therefore, the gate terminal is subjected to the (DC) bias voltage set at the point a and the feedback resistor Rfb, i.e., the same bias voltage setting for the transistor Μ l_p. The source terminal of the gain transistor M2_p is coupled to ground. The drain terminal of the gain transistor M2_p is coupled to node B. By using the voltage at node a to provide input biases for transistors M1_p and M2-P, which in this example implement impedance matching stage 4 and gain stage 420, respectively, bias resistors can be avoided. And/or an AC coupling capacitor to bias Ml_p and M2_p (i.e., provide input bias for the gates of M1_p and M2_p). This not only reduces the cost and size of the integrated LNA' but also avoids the LNA noise factors discussed above. In Figure 1, the signal reuse level is implemented by the transistor M4-p. The source terminals of transistors M4-P are also coupled to node B. The gate terminal of transistor M4_p is coupled to voltage supply vdd via resistor Rm4. The bias voltage for the transistor M4-p in other embodiments may be replaced by an AC bias, such as a partial Vdd (such as 〇.75xVdd). Typically, the gate bias is selected (in this case, Vdd), causing the transistor M4-p to operate as a linear amplifier. The gate terminal of transistor M4_p is further coupled to node A via an AC-contracted capacitor stomach like 2 p 51 201249116. Again, the capacitor acc2_p has to be small, such as < 1 pF, to isolate the DC bias applied to the gate terminal of the transistor M4_p and the DC voltage of node A, but to allow the AC signal component to pass through The transistor M4-p is amplified. In this way, the signal reuse level implemented by M4_p, acc2_p, and Rm4 buffers the voltage at point a to become the current signal input to point B. As can be seen from Figure 1 $, only a minimum of two Ac-coupling capacitors are required on each side of the differential amplifier, which reduces cost and required die area. As with the impedance matching function provided by its arrangement, the impedance matching stage further amplifies the input signal inp, i.e. acts as a fixed transconductance (gm) amplifier' to generate an amplified (AC) signal at node A. This amplified signal is "re-used" at the first gain stage. In Fig. 18, the amplified signal at node a is applied to the gate terminal of transistor M4-p, which further amplifies the signal to produce a further amplified signal at node b which has the characteristics of high current and low noise. For other comparative examples, node A does not need to be coupled to the further portion of differential side 605, i.e., it may not be necessary to couple the gate terminals of node A and transistor M4_p to achieve an impedance matching function. However, certain embodiments use the signal at node A to provide better LNA performance when considering the first use of a partial impedance matching function. Alternatively, another embodiment can be used to couple another form of unbuffered or amplifying the transistor such that the signal at A is reused in b. In Figure 18, the current splicing or current buffering stage is implemented by transistor m5-p. In Fig. 18', the transistor M5_p is an NMOS transistor. The source terminal of transistor M5 p is electrically coupled to node B. The gate of the transistor M5-p is electrically closed 52 201249116 in conjunction with node c. The gate terminal of the transistor M5_P is coupled to a voltage source vdd (also the gate terminal of the transistor M5_m, which forms part of the second differential side 610). For sufficient performance, the gate bias of transistor M5_m should follow the gate bias of transistor M4_m. For example, if the bias voltage for the transistor M4-p is replaced by an AC bias (eg, 〇75*Vdd), the bias voltage for the transistor M5-m should also be biased by an AC (such as 〇 Replaced by 75*vdd). The fulcrum C is at least consumed by the output terminal 260 and the adjustable LC resonators 270, 280. The adjustable LC resonator implements a configurable load that is at least electrically coupled to the dipole terminal of the transistor M5_p,m. In an embodiment, the adjustable LC resonator includes a variable capacitor connected in parallel to the center tap differential inductor, and the center tap differential inductor is electrically coupled to the voltage supply Vdd. Note that the gate terminal DC voltage for the transistor M5_p,m can be set to a level other than Vdd' such that the gate voltage of the gain transistor Μ2_ρ can be set to the desired level to increase the drain of the transistor Μ5_ρ The available voltage swing of the terminal. If the gate terminal DC voltage for the transistor M5_p,m is to be changed' then it is recommended to also change the gate terminal DC voltage for the transistor M4_p in order to maintain sufficient performance characteristics. In some implementations, a current directing junction X2 can be provided between the drain terminal of each transistor M5_p,m and the adjustable LC resonator/each output. Current steering stacking can be used to add gain control between M5_p and output terminal 260, or to provide further current buffering (if needed). In Figure 1, the transistors M5_p and M2_p are thus arranged in a stacked configuration, where M2_p provides a common source amplifier and M5_p provides a common gate amplifier. M2_p further shares a common DC current with M4_p and M5_p 53 201249116 path. The transistor M2_p has the largest mutual conductance (and the highest drain current) of the NMOS transistor. The signal current through transistors M4_p and M2_p is constructively added at point B to increase the current gain. Node b thus outputs a low-pitched high-signal current from the gain stage to the splicing or buffering stage and then feeds into the current that passes through the Μ5_ρ-stacked transistor, which in turn is an adjustable LC resonator 270, 280. At least the resistors Rcm, Rpv' and Rm4 have large values, i.e., values in the order of 10 k ohms. The exact values of the resistors and capacitors described herein can be selected based on implementation specifications using standard design specifications. By reusing the signal that is generated as part of the impedance matching stage, the current consumption of the LNA can be reduced. The particular embodiments described herein provide the advantage of achieving good noise performance (i.e., having low noise factors) without the need for external matching components. The current consumption of a particular embodiment is also low, for example, when the LNA is fed back compared to known resistances. Embodiments may include a fully integrated differential amplifier on a single wafer. At least one of the correct gain, linearity, noise, and input impedance matching can be achieved by properly biasing the gain and impedance matching stages (especially those that implement those stages), although the difference is in process and temperature effects. Supplying at least one of a voltage change and an aging condition. Particular embodiments are able to properly set the mutual conductance of the MOSFET device to mitigate the above variations. In one embodiment, this is accomplished by biasing the transistors Mi and m2 with a fixed mutual conduction circuit and a common mode feedback stage using resistor feedback and DC bias point settings. The use of at least resistive feedback further avoids the need to use additional DC bias resistors to bias the voltage seen by transistors M丨 and M2 to 5 54 201249116. The embodiments described herein minimize the number of bias resistors and A c coupling capacitors, minimizing cost and die area (i.e., the area occupied by the integrated wafer on the substrate). This allows a particular embodiment to attract many LNAs that need to be implemented for different frequency bands. The particular LNA embodiment presented herein provides common pattern matching and good common mode linearity. They further provide wideband input impedance matching', that is, impedance matching across a wide range of RF signal frequencies. Such wide frequency matching occurs without the need for a specific frequency calibration. For example, the topology of Figure 18 matches the frequency range up to 3 GHz. This is due to the fact that there is no frequency selection component in the topology and that any inductor is lacking as a source load (as found in the inductively degraded LNA). For example, compared to known resistance feedback LNAs, this results in better attenuation against remote signal blockers (eg, transmitter, wireless network, and Bluet00thTM signal wideband matching to further avoid degradation of duplex filter performance; This degradation can occur if impedance matching does not occur in the frequency range handled by the duplex filter. It also avoids desensitization of the product between the receiver front end and the module. Figure 18 Signals using LNA topology again Some are similar to the topology of the inductively degraded LNA of Figure jj; however, there are several differences: First, the signal of Figure 18 re-uses the LNA without the presence of an inductor [deg, which provides the gain transistor M2_p of Figure 11 inductively degraded LNA Inductive degradation of the source terminal of m, the signal of the circle 18 is further connected to the ground of the input terminal M2_p of the gain stage of the LNA, and the source terminal of the m is directly connected to the ground. Second, the output terminal 260 (ie, the differential amplifier) The output terminal on the + side is connected to the input 55 via the input impedance matching, feedback and signal re-use level. 201249116 Terminal 220 (ie the input of the differential amplifier + side). The sides are also similarly connected. The second 'external matching components Lextp and Lextm are not provided for the signal reuse LNA of Fig. 18. The input transistors M2_p,m are thus directly adapted to the input terminals 220 and 222, respectively. The components are adapted to match the impedance to which the input terminals 22A and 222 are connected (wherein the impedance to be matched is, for example, the output impedance of the RF filter in front of the LNA), and the signal of Figure 8 is reused [ν a instead can be internal to the LNA To match the impedances connected to inputs 220 and 222. Because the signal of Figure 18 uses LNA without external matching components Lextp and Lextm to provide passive voltage gain in front of transistors M1-pm, M2_p, m (as described above) The inductive degradation of the LNA is described, so the noise effect of the gain transistor M2_p,m is not alleviated. In addition, the signal of Figure 18 uses the LNA to have additional between the LNA's output terminals 260 and 262 and the input terminals 220 and 222. The source of the noise. Generally, §, the signal performance of the signal of Figure 18 is worse than that of the inductively degraded LNA of Figure 11. However, since the signal of Figure 18 is no longer needed to use the LNA The external matching components Lextp and Lextm also do not require the inductor Ldeg for sensing degradation, so the overall cost of the signal reuse of Figure 18 is lower compared to the induced degradation Lna of Figure . Some embodiments relate to LNA circuits. Configurable between the first topology and the second topology: the first topology of the low noise amplifier circuit includes a degraded inductor, causing the low noise amplifier circuit to operate as a low noise amplification of the induced degradation 1 §; The second topology is referred to herein as the signal reuse topology. 56 201249116 The §fl re-use topology includes an impedance matching stage (which is coupled to the input of a configurable low noise amplifier circuit) and a feedback stage (which is coupled) Output and voltage source for impedance matching stage). The output of the impedance matching stage provides an input bias for the impedance matching stage. The feedback stage provides a compensated operating voltage for the impedance matching stage. In the first topology, one or more external input impedance matching members are used in conjunction with the LNA to match the input impedance. For the second topology, the input impedance matching is performed using components inside the LNA topology; the second topology does not require external matching components. Input impedance matching may, for example, involve matching the output impedance of an RF filter connected to one or more inputs of the LNA. An example of a configurable LNA circuit in accordance with an embodiment is illustrated in FIG. Like the LNAs of Figures 11 and 18, the configurable LNA paradigm of Figure 19 is a differential amplifier; other embodiments are equally applicable to non-differential amplifiers. The topology of the configurable LNA of Figure 19 necessarily includes some features of the low noise amplifier similar to the inductive degradation of Figure 11 and the signal of Figure 18 using LN a; however, there are several important differences, including As follows: First, the configurable [ΝΑ contains the switching arrangement to configure lnA between the first, inductively degraded topology and the second, signal reuse topology. The switching arrangement includes a number of topology switching mechanisms. Second, similar to the signal of Fig. 18, the LNA of the configurable state of Fig. 9 includes an input impedance matching stage 4, a feedback stage 43A, and a signal reusing stage 440. However, the input impedance matching stage 4丄〇 on the differential amplifier + side is not directly connected to the input terminal 220, but the input impedance matching stage 41〇 is connected to the topology switching mechanism (in this case, the switching transistor SW2p), which It is coupled to the input terminal 220 in turn. Specifically, the drain of the switching transistor SW2p 57 201249116 is connected to the feedback resistor Rfb and the AC coupling capacitor accl_p, and the source terminal is connected to the input terminal 220. The gate terminal of the switching transistor SW2p is connected to the configuration control signal terminal xLdeg2. The topology switching mechanism sw2p is thus connected between the gate of the transistor Μ1_p and the feedback resistor Rfb and the ac coupling capacitor accl_p. The side of the differential amplifier is similarly connected, wherein the topology switching mechanism SW2m is connected to the gate of the transistor M1_m. Second, the topology switching mechanism (in this case, switching transistor S w 1) is connected between the source terminals of the gain transistors M2_p and M2_m. One of the drain terminal and the source terminal of the switching transistor swi is connected to the source terminal of M2_p, and the other terminal is connected to the source terminal of M2_m. The gate terminal of the switching transistor swi is connected to the configuration control signal terminal xLdegi. Fourth, the gate terminal of the gain transistor M2_p on the differential amplifier + side is not directly connected to the bias source vbias 'topology switching mechanism via the first bias resistor Rbp (in this case, switching transistor 8 W3p) Instead, it is connected between the first bias resistor Rbp and the bias source vbias. Specifically, the drain terminal of the switching transistor S W3p is connected to Rbp, and the source terminal is connected to vbias. Similarly, on the differential amplifier side, the topology switching mechanism (in this case, switching transistor SW3m) is connected between the second bias resistor Rbm and the bias source vbias. By applying appropriate configuration control signals to the configuration control terminals xLdegl, xLdeg 2, Ldeg 3, the switching transistors SW1, SW2p, m can be switched to the on state, and SW3p, m can be switched to the off state, whereby Figure 19 The configurable LNA is configured as a first, inductively degraded topology. Conversely, 'by applying the appropriate configuration control signal to the configuration control terminal 58 201249116 xLdegl ' xLdeg 2, Ldeg 3, switching transistors SW1, SW2p, m can be switched to the off state, and SW3p, m can be switched on The state, whereby the configurable LNA of Figure 19 is configured as a second, signal-reuse topology. A configurable low noise amplifier can be configured between the first and second topologies using a switching arrangement. The switching arrangement includes a number of topology switching mechanisms, and embodiments include switching transistors. In the first inductively degraded topology, the switching transistors SW1 and SW2p,m are configured to be in an on state, and the switching transistors SW3p,m are configured to be in a closed state. By arranging the switching transistor S W 2 p to the on state, this prevents current from flowing through the transistors M1 - p, m. This means that the impedance matching stage 4 1 0 on each side of the differential amplifier is effectively disconnected from the input signals inp, inm applied to the individual input terminals 220 and 222. The switching transistor SW3_p,m is configured to be in a closed state by applying an appropriate control signal Ldeg3 to directly apply a bias voltage vbias to the gate of the gain transistor Μ 2 _ p,in. The configurable low noise amplifier circuit can be grouped by coupling the output of the differential amplifier + and the feedback amplifier XI of the feedback stage 430 on one side to the positive supply voltage Vdd to turn on the M3-p,m transistor. In the first topology. In the embodiment, since the feedback amplifier X1 is not used in the first topology, the common mode feedback amplifier χι on the differential amplifier + and one side is disabled by connecting its enable input to the appropriate control signal. The configurable low noise amplifier circuit can be configured on the first topology by turning on the signal and then using the M4_P, m transistor. This can be done by applying the appropriate 59

The control signal of 201249116 (for example, compared to the lower control signal when the configurable low noise amplifier circuit is configured as a second) is reached by the gate of the M4-p, m transistor. This configuration mode is shown in Figure 20. The transistors Ml_p, m, M3_p, m, M4_p, m are open and therefore do not affect circuit operation (these components are shown in circle 20 as gray instead of black). In addition, the common mode feedback of the feedback amplifier χi is disabled, and the bias resistors and Rem connected to XI, together with the resistor Rfb, have no effect on the operation of the configurable low noise amplifier. Since the input impedance matching stage of this configuration (not shown in Figure 9 and Figure 2 is not XMATCH) is disabled, the external matching components Lextp and Lextm are used to achieve input impedance matching. By configuring the switching transistor SW1 to be in the on state, the source terminals of the input transistors M2_p,m are operatively connected only via the inductor Ldeg, the center tap of which is connected to ground. The inductor Ldeg thus provides inductive degradation of the source terminal of the input transistor M2p,m, as in the induced degradation LNA of Figure i. When the switching transistors SW1 and SW2p, m are configured to be in an open state, and the switching transistor SW3p,m is configured to be in a closed state, that is, when the configurable LNA is configured as the first topology, The configured LNA thus operates as an inductively degraded LNA » Therefore, when configured as a first topology, the configurable LNA does not provide internal input impedance matching, for example matching to the front of the input terminals 22 and 222 The output impedance of the RF filter. As a result, the input impedance of the LNA of the group of bears in Figure 2 should be connected by an external impedance matching component (for example

S 60 201249116 external matching components Lextp and Lextm) are matched, for example, to the previous RF filter, as shown by the inductively degraded LNA of FIG.

Although the first topology of the configurable LNA of Figure 19 thus provides the benefit of the inductively degraded LNA of Figure iJ, i.e., a relatively low noise index, external matching components are required to provide input impedance matching. In the second, the signal is further used to switch the transistors SW1 and SW2p, m is configured to be in a closed state, and the switching transistor SW3p, m is configured to be in an on state. In this mode of operation, the input impedance matching, the level 41〇 and the feedback 'and 430 (Fig. 19; f is shown as XMatch) and the signal are connected, so that the circuit operation is the same as that shown in Fig. 18. The signal re-use LNAe does not use any external light-weight components (such as Lex (four) to achieve input impedance matching (via XMATCH) » in the embodiment 'by the differential amplifier + and - side of the feedback stage 43 〇 feedback amplifier X1 output The solution is lighter than the positive supply voltage 乂(5), causing the M3_P,m transistor to be turned off, so that the configurable low noise amplifier circuit can be configured in the second topology. In addition, the common mode feedback on the 'differential amplifier + and the side' The amplification ΜΙ# is enabled by applying the appropriate control signal to its enable input. The configurable low noise amplifier circuit can be configured to the second topology by turning off the signal and then using the M4-P, m transistor. This can be done by applying the appropriate = signal (for example, a higher control signal than when the configurable low noise amplifier circuit is a diode) to the M4-P, m transistor. The gate is reached. When configured as the first reactance match, for example, the second In the topology, the output impedance of the aforementioned rf 61 201249116 filter, which is configurable to the input terminal LNA to provide internal input resistances 220 and 222. As a result, no external matching components are required, such as the inductively degraded LNA of Figure 11. The external matching components Lextp and Lexpm are shown. When the configurable LNA of Figure 19 is configured as a second topology, the switching transistor SW1 is configured to be in a closed state; this provides additional benefits, as will now be described By configuring the switching transistor SW1 to be in the off state, the source terminals of the gain transistors M2_p,m are operatively connected (ie, shorted). Switching between the source terminals of the gain transistors M2_p,m The connection formed by the crystal sw 1 is connected in parallel to the inductor Ldeg, which is connected to the source terminal of the gain transistor M2_p,m. As in the inductively degraded LNA of Fig. 11, the inductor Ldeg is a differential inductor device having mutual coupling The mutual coupling of the differential inductor devices causes the inductor to perform different operations on the common mode signal applied to the differential amplifier, as compared to the differential mode signal applied to the differential amplifier. The common mode signal of the differential amplifier is a signal component having the same size and the same phase as the individual input signals inp, inm applied to the input terminals 220 and 222. In contrast, the differential mode signal has and is applied to the input terminal 220. The signal components of the same size and opposite phase are input to the individual input signals of 222. When the configurable LNA is configured as the second topology, the input mode is applied to the differential mode signals applied to the input terminals 220 and 222. The connection formed by the switching transistor SW1 between the source terminals of the crystal M2_p,m forms a virtual ground for the differential signal. However, when the configurable LNA is configured as a second topology, the common mode signal applied to the input terminals 220 and 222 is applied to the source terminal of the gain transistor M2_p,m. The inductance provided between the ground and the ground (which is connected to the center tap of the inductor Ldeg) is equal to: (1 - k) / 2 * Ln (2) where k is the mutual coupling coefficient of the inductor Ldeg and Ln is based on the inductor The nominal inductance of the electrical length of Ldeg.

Therefore, when the sconfigurable LNA is configured as a second topology, the inductance provided by the inductor Ldeg (according to equation (2) above) is used to attenuate interference and other noise from the ground voltage supply. impedance. Therefore, the noise rejection performance of the power supply is improved, for example, when the configurable lna is configured as the second topology by the higher power supply rejection ratio (pSR when the configurable configuration is configured as the first In the second topology, the degenerate inductance provided by the inductor is therefore suitable for providing the power supply noise rejection impedance. By degrading the LNA topology from the inductive degraded inductor Ldeg, configurable

When configured as a second topology, the F performance is demonstrated, for example, by the configurable lna group CMRR metric. Degradation provided by inductor Ldeg when configurable 63 63 201249116 The inductor is therefore adapted to provide a common mode signal rejection impedance for the signal components common to the input signals applied to input terminals 22 and 222. By "borrowing" the inductor Ldeg from the inductively degraded LNA of Figure 11, the formable LNA can improve the signal to reuse the cmrr of the LNA topology. The "borrowing" inductor Ldeg also ensures that the expensive (in terms of wafer area) components from the first topology of the configurable LNA can be used for both configurations of the configurable LNA. The configurable LNA of Figure 19 thus provides an LNA that can be configured to suit the intended use or design requirements. If a more sensitive LNA with a better noise index is needed, the LNA can be configured as a first topology at the expense of requiring external matching components, such as Lextp and Lextm, to provide input for the configurable LNA. Impedance match. Alternatively, the LNA can be configured to be a second solution to provide a more cost effective solution. In addition, when the configurable LNA is configured as a second topology, the sensor Ldeg is used to provide an improved PSRR and CMRR that is superior to the signal of Figure 18 and then the LNA. This results in reuse of components on expensive wafers that can consume a significant amount of wafer area (i.e., inductor Ldeg) of the configurable LNA. The above embodiments are to be understood as illustrative examples of the invention. The present invention contemplates further embodiments. In the embodiment of Figure 9, the inter-band CA (in this case between RF bands 3 and 7) is implemented using a single RFIC. Alternative implementation

S 64 201249116 Example, the design can be extended to include two separate RFICs, one for processing signals from the main FEM, and the other RFIC for processing signals from the DIV FEM; or an RFIC for processing from the rf band 3 while in the main and DIV FEM signals, while another RFIC is used to process signals from the 叩 band 7 while in the main and DIV FEM. Alternatively, the inter-band CA can be achieved using a single RFIC and only a single (primary) FEM, rather than using both the primary FEM and DIV FEM. The configurable RFIC of an embodiment may be configured by its manufacturer or configured by a third party to install one or more configurable RFICs, for example, in its device module; this may involve A method of configuring a configurable RFIC of one or more configurable low noise amplifier circuits. The configuration method can include one of: applying one or more control signals of the first group to at least one of the one or more circuits to configure the at least one circuit as an internal input impedance matching topology, Wherein the individual low noise amplifier circuits include one or more internal input impedance matching components adapted to match the input impedance of the individual low noise amplifiers to a given input, and one or more internal input impedance matching components Typing within an individual low noise amplifier circuit; or applying one or more control signals of the second group to at least one of the one or more circuits to configure the at least one circuit to a different topology Wherein the individual low noise amplifier circuits do not include one or more internal input impedance matching components. A set of control signals can be applied, for example, to one or more switching transistors and/or bias switching mechanisms.

A configurable RFIC can be included in an RF module that includes one or more RF 65 201249116 ferrites located in the RF front-end module in front of the RF1C. The RFIC can include input and output pins and/or leads to connect externally mating components between the dirty configurable (10) and RF ferrites. The job may alternatively be selected to include one or more rf filters connected to one or more configurable LNAs. The configurable R F丨C of an embodiment can be incorporated into many different devices. Such a device may alternatively include a user device' such as a mobile station, a personal digital assistant, or a cellular telephone. The H state #RFICfL may be included in the receiver of such a user device. In addition, such a device may include a data device device to be attached to a user device, such as a universal serial bus (USB) modem. Further, such a device may also include a communication module, such as a machine-to-machine (M2M) module, which may be inserted into another device, such as a laptop or other communicative device (e.g., a vending machine). Moreover, such a device may alternatively include a wafer set that may include radio frequency and baseband components. It is to be understood that any feature described with respect to any embodiment can be used alone or in combination with other described features, or can be used in combination with one or more features of any other embodiment, or in any combination with other embodiments. To use. Further, the equivalents and modifications, which are not described above, may be employed without departing from the scope of the embodiments, which are defined in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates an example of a receiver according to the prior art, which includes an RF module and an antenna. Figure 2 illustrates the use of an rf chipset on a PWB in accordance with the prior art.

S 66 201249116 at the receiver. Figure 3 is an illustration of an rf chipset on pwB for use in a receiver in accordance with the prior art. Figure 4 illustrates an RF chipset on a pWB for a receiver, including a configurable RFIC, in accordance with an embodiment. Figure 5 illustrates an rf chipset on pwB for a receiver, including a configurable RFIC, in accordance with an embodiment. Figure 6 illustrates an rf chipset on a pWB for a receiver, including a configurable RFIC, in accordance with an embodiment. Figure 7 illustrates an RF chipset on a PWB for a receiver, including a configurable RFIC, in accordance with an embodiment. Figure 8 illustrates an RF chipset on pwB for a receiver' which includes a configurable RFIC, in accordance with an embodiment. Figure 9 illustrates an RF chipset on a PWB for a receiver, including a configurable RFIC, in accordance with an embodiment. Figure 10 illustrates an RF chipset on a PWB for a receiver, including a configurable RFIC, in accordance with an embodiment. FIG. 11 is a circuit diagram of an inductively degraded LNA in accordance with an embodiment. Figure 12 is a circuit diagram of a common gate LNA in accordance with an embodiment. Figure 13 is a circuit diagram of a configurable LNA in accordance with an embodiment. 14 is a circuit diagram of a resistance feedback LNA in accordance with an embodiment. Figure 15 is a circuit diagram of a configurable LNA in accordance with an embodiment. Figure 16 is a block diagram of a signal reuse low noise amplifier in accordance with an embodiment. 67 201249116 FIG. 1 7 illustrates a common mode feedback amplifier in accordance with an embodiment. Figure 18 is a circuit diagram of a signal reuse low noise amplifier in accordance with an embodiment. 19 is a circuit diagram of a configurable low noise amplifier in accordance with an embodiment. 20 is a circuit diagram of a configurable low noise amplifier configured to sense a degraded topology, in accordance with an embodiment. [Main component symbol description] 100 RF (RF) module 110' 112 RF filter 120 ' 122 Low noise amplifier (LNA) 130 Antenna 132 RF front-end module (FEM) 134 RF integrated circuit (RFIC) 200 > 202 ' 210 ' 212 transistor 220 > 222 input terminal 240 ' 242 decoupling capacitor 250, 250m ' 250ρ inductor 260 > 262 output terminal 270 variable capacitor 280 inductor 300 ' 302 feedback resistor 400 , 402 switching Crystal 68 201249116 410 415 420 421 , 423 , 425 430 432 434 435 436 440

605, 610 A

Acc 1 m, acc1p acc2m, acc2p B

B1, B2, B3, B7, B20 C cfbm, cfbp cg_core cm_fb

DIV

HB inm, inp LB switching transistor, impedance matching stage bias gain stage configuration control signal terminal decoupling capacitor, feedback stage decoupling capacitor, non-inverting input inverting input voltage source output signal and then using differential side node capacitor Capacitor node band 1 , 2 , 3 , 7 , 20 node capacitor common gate LNA level common mode feedback input diversity south band input signal low band 69 201249116

Ldeg inductor Ldeg 3 configuration control signal terminal Lextm, Lextp external matching component M 1 _m, M 1 _p transistor M2_m ' M2_p transistor M3_m ' M3_p transistor M4_m, M4_p transistor M5_m ' M5_p transistor outm, outp output signal PA power amplifier pmos_vbias PMOS bias Rbm, Rbp bias resistor Rb1m, Rb1p bias resistor Rb2m ' Rb2p bias resistor Rem resistor Rfb feedback resistor Rm4 resistor Rpv resistor RX receiver SW1, swim, SWlp switching Transistor SW2m > SW2p Switching transistor SW3m, SW3p Switching transistor TX Transmitter vbias ' vbias_cg , vbias_ldeg Hemiplegia Source

70 S 201249116

Vdd XI X2_m, X2_p xLdeg ' xLdeg1 XMATCH circuit voltage supply feedback amplifier current steering splicing xLdeg2 configuration control signal terminal input impedance matching stage 71

Claims (1)

201249116 VII. Patent application scope: 1' configurable radio frequency integrated circuit (RFIC) including one or more configurable low noise amplifier circuits, one or more configurable low miscellaneous Each of the aR amplifier circuits can be configured between: an internal input impedance matching topology, wherein the individual low noise amplifier circuits include one or more internal input impedance matching components adapted to separate individual low noise The input impedance of the amplifier is matched to a given input, the one or more internal input impedance matching components being tied within an individual low noise amplifier circuit; and a topology different from the internal input impedance matching topology. 2. The configurable RFic of claim 1 wherein the individual low noise amplifier circuits of the different topologies do not include at least one of the one or more internal wheeled impedance matching components. _ 3 'A configurable RFIC according to claim 1 of the claims, wherein the individual low noise amplifier circuits in the different topologies do not include any one of the one or more internal input impedance matching components . 4. The configurable RFlc according to item i of the claimed patent scope, wherein at least one of the one or more configurable low noise amplifier circuits comprises a switching female platoon 'the at least one configurable low miscellaneous The amplifier circuit can be configured between the internal input impedance matching topology and the different topology via individual switching arrangements. 17 立 5. According to the configurable RFI of the scope of patent application i (where the input impedance matching topology comprises a resistance feedback low noise amplifier topology, and the different topology includes low noise of induced degradation Amplifier topology S 72 201249116 6. According to the configurable RFIC of the scope of patent application i, the internal input impedance matching topology comprises a common gate low noise amplifier topology, and the different topologies include induction Degraded low noise amplifier topology. 7. Configurable RFIC according to claim 1 of the patent application, wherein the different topology comprises a low noise amplifier topology that senses degradation, and the internal input impedance matches the topology The method includes: an impedance matching stage coupled to an input of a configurable low noise amplifier circuit while an output of the impedance matching stage provides an input bias for the impedance matching stage; and a feedback stage coupled to the output of the impedance matching stage And a voltage source, and the feedback stage provides a compensated operating voltage for the impedance matching stage. 8. The configurable RFIC according to claim 1 of the patent application, wherein the one or more Each of the configurable low noise amplifier circuits includes a common output; knowing, while the individually configurable low noise amplifier circuit is configured to match the top input impedance matching topology or the different topology The output signal is provided at the common output terminal. 9. The configurable RFIC of the scope of claim 1 includes a face, arranged to place the one or more configurable low noise amplifier circuits One is connected to a radio frequency (RF) front-end module. The configurable RFIC according to claim 9 of the patent scope, wherein the " face includes at least a first input connection arranged to bring the one or At least a first of the lower noise amplifier circuits can be connected to the first RF band output of the front end module. • Configurable RFIC according to claim 10 of the patent scope, 73 201249116 The " face includes at least a second input connection arranged to connect at least a second one of the one or more: configured low noise amplifier circuits to the previous _ RF band output, wherein the second The RF band is different from the first RF frequency band. The configurable rfic according to item 9 of the patent scope of the patent, comprising an interface f that is arranged to connect at least one of the one or more configurable low noise amplifier circuits Another - RF front-end module. According to the configurable RFIC of claim 12, where the "" front-end module includes the main antenna RF front-end module, and the other-, RF front-end module interface includes the diversity antenna RF front-end Module 。 Configurable RFIC according to item 12 of the patent scope of the application, wherein the other interface comprises: at least a third input connection arranged to place the one or more groupable low miscellaneous At least a third one of the amplifier circuits is coupled to the other RF front end, 'the _RF band output', wherein the _ rf band includes the third RF band; and the 输入 four input connection 'is arranged to Or less than $ 中 in the configurable low noise amplifier circuit. _ Medium to / Fourth is connected to the fourth RF band rim of the other RF front-end module, i# Beckham Wherein the s-th third RF band is different from the four RF bands. $15. According to the scope of the patent application, the first RF band includes the third including the fourth RF band. 16. The configurable RFIC according to claim 14 of the scope of the patent application, wherein the RF band 'and the configurable RFIC of the second rf band 1 includes at least one interface of 201249116 arranged to bring the one or more At least one of the plurality of configurable low noise amplifier circuits is coupled to the at least one antenna. 1 7. Configurable RF 1C according to claim 1 of the scope of the patent application, wherein the different topology comprises a completely externally matched topology, wherein the individual low noise amplifier circuits do not comprise the one or more internal Enter any of the impedance matching components. 1 8. A method of configuring a configurable RFIC comprising one or more configurable low noise amplifier circuits, the method comprising one of: one or more of the first group Control signals are applied to at least one of the one or more circuits to configure the at least one circuit as an internal input impedance matching topology, wherein the individual low noise amplifier circuits include one or more internal input impedance matching components Suitable for matching the input impedance of an individual low noise amplifier to a given input' and the one or more internal input impedance matching components are tied to the interior of the individual low noise amplifier circuit; or Applying one or more control signals to at least one of the one or more circuits to configure the at least one circuit to a different topology, wherein the individual low noise amplifier circuits do not include the one or more An internal input impedance matching component. 1 9_ A method of manufacturing a configurable rfic according to the scope of the patent application. 20. An rf module comprising one or more RF front end modules. The RF front end module is lightly coupled to one or more configurable RFICs according to the scope of the patent application. 2 Xia.----------------------------------------------------------------------------------------------------------------------------------------------- 22. A device comprising one or more configurable RFICs according to the scope of the claims. 23. A configurable radio frequency integrated circuit (RFIC) comprising one or more configurable low noise amplifier circuits, each of the one or more configurable low noise amplifier circuits The system can be configured between: an internal input impedance matching topology, wherein the individual low noise amplifier circuits include one or more internal input impedance matching components adapted to match the input impedance of the individual low noise amplifiers to For a given input, the one or more internal input impedance matching components are tied within an individual low noise amplifier circuit; and a fully externally matched topology where the individual low noise amplifier circuits do not include the one or more One of the internal input impedance matching components. Eight, the pattern: (such as the next page) S 76