201248852 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種金屬閘極結構及其製作方法，尤_ 一種採用後閘極(gate last)製程之金屬閘極結構及其製作方 法0 【先前技術】 隨著半導體元件尺寸持續微縮，傳統方法中利用降低門 極介電層，例如降低二氧化矽層厚度，以達到最佳化目 方法，係面臨到因電子的穿隨效應（tunneling effect)而導故 電流過大的物理限制。為了有效延展邏輯元件的世代演迤舄 high-K材料因具有可有效降低物理極限厚度並且在相同 等效氧化厚度（equivalent oxide thickness，EOT)下，有欸降 低漏電流並達成等效電容以控制通道開關等優點，而被用r 取代傳統—氧化⑦層或氮氧化⑪層作為閘極介電層。' 另外’傳統的閘極材料多晶矽則面臨硼穿透(boron penetration)效應’導致元件效能降低等問題；且多晶矽 更遭遇難以避免的空乏效應(如咖論沿⑽)，使得等欵的門 極；1電層厚度增加1極電容值下降，進而導致it件驅動# 力的衰退等困境。針對此問題，半導體業界更提出以新的^ 和材料例如利用具有功函數(w〇rk functi〇n)金屬層的金屬 3 201248852 閘極來取代傳統的多晶石夕閘極，用以作為匹配high-K閘極 介電層的控制電極。 然而，high-K材料非常容易受到後續製程的影響。舉例 來說，在後續製程暴露出來的high-K閘極介電層極易因氧 化而導致介電常數降低(degrade)或不穩定（uncertainty)，進而 影響閘極結構的可靠度(reliability);而暴露出來的high-K閘 極介電層甚至可能在後續製程中耗損，進而影響半導體元件 的電性表現。因此，採用high-K閘極介電層之閘極結構仍 然需要可避免high-K材料發生氧化反應的保護結構，以確 保high-K閘極介電層與金屬閘極結構的可靠度。 【發明内容】 因此，本發明之一目的係在於提供一種high_K閘極介電 層之保護結構，以及具有該保護結構之金屬閘極結構及其製 作方法。 根據本發明所提供之中請專利範圍，係提供—種金属問201248852 VI. Description of the Invention: [Technical Field] The present invention relates to a metal gate structure and a method of fabricating the same, and more particularly to a metal gate structure using a gate last process and a method of fabricating the same [Prior Art] As the size of semiconductor components continues to shrink, the conventional method utilizes a lower gate dielectric layer, such as reducing the thickness of the yttria layer, in order to achieve an optimized method, which is subject to electron wear and tear (tunneling) Effect) The physical limit of the current is too large. In order to effectively extend the generation of logic components, high-K materials have an effective reduction in physical limit thickness and, under the same equivalent oxide thickness (EOT), reduce leakage current and achieve equivalent capacitance to control The advantages of the channel switch, etc., are replaced by r----- 7 layers of oxide or 11 layers of oxynitride as the gate dielectric layer. 'In addition, the traditional gate material polysilicon is faced with boron penetration effect, which leads to problems such as reduced component efficiency; and polycrystalline germanium suffers from unavoidable depletion effects (such as the theory of coffee (10)), making the gate of the helium 1 The thickness of the electric layer is increased by 1 pole, and the value of the capacitor is decreased. In response to this problem, the semiconductor industry has proposed to replace the traditional polycrystalline slab gate with a new ^ and material, for example, using a metal 3 201248852 gate with a work function (w〇rk functi〇n) metal layer. The control electrode of the high-K gate dielectric layer. However, high-K materials are very susceptible to subsequent processes. For example, the high-K gate dielectric layer exposed in subsequent processes is highly susceptible to degradation or instability due to oxidation, which in turn affects the reliability of the gate structure; The exposed high-K gate dielectric layer may even be depleted in subsequent processes, thereby affecting the electrical performance of the semiconductor component. Therefore, the gate structure using the high-K gate dielectric layer still needs a protection structure that avoids the oxidation reaction of the high-K material to ensure the reliability of the high-K gate dielectric layer and the metal gate structure. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a protection structure for a high_K gate dielectric layer, a metal gate structure having the same, and a method of fabricating the same. According to the scope of the patent provided in the present invention, a metal is provided
，設置於該 簡稱為SlCN)封層（seal layer)。且 形之功函數金屬層，設置於該 201248852 high-K閘極介電層上。 根據本發明所提供之申請專利範圍，另提供一種金屬閘 極結構之製作方法，該製作方法首先提供一基底，該基底上 形成有一虛置閘極，且該虛置閘極包含有至少一犧牲層❺接 下來進行一原子層沈積（atomjc layer dep0siti〇n，以下簡稱為 ALD)方法，於該基底及該虛置閘極上形成一 SiCN封層且 該ALD方法更包含通入碳氫化合物（hydr〇carb〇n，CxHj氣 體。待形成該SiCN封層之後，係移除該虛置閘極之該犧牲 層，以於該基底上形成—閘極溝渠，最後於該閘極溝渠内形 成一金屬閘極。 根據本發明所提供之金屬閘極結構及其製作方法，係利 用一 ALD方法，於該金屬閘極與該high_K閘極介電層之側 壁形成一具有較低濕餘刻率（wet etching rate)的SiCN封展 由於SiCN封層的濕蝕刻率較低，因此可於後續蝕刻或清洗 製私中有效地保濩high-K閘極介電層，避免high_K閘極介 電層氧化，進而避免因氧化導致的效能降低問題。因此，本 發明所提供之金屬閘極結構之製作方法，係可提供一具有， 好可靠率之金屬閘極結構。 & 【實施方式】 請參閱第1圖至第6圖，第i圖至第6圖係為本發明所 5 201248852 提供之金屬閘極結構之製作方法之一第一較佳實施例之示 意圖’且本較佳實施例係採用後閘極(gatelast)製程。如第1 圖所示’首先提供一基底100，如一矽基底、含矽基底、或 矽覆絕緣（silicon-on-insulator，SOI)基底等，且基底100内 係形成有複數個用以提供電性隔離的淺溝絕緣(shaU〇w trench isolation，STI) 102。接下來，係於基底1〇〇上形成一 虛置閘極110 ’而虛置閘極11 〇則包含一介質層（interfaciai layer) 112、一閘極介電層 114、一底部阻障（bottom barrier) 層116、一犧牲層118、以及一圖案化硬遮罩（圖未示），該 等膜層係由下而上依序堆疊於基底1〇〇上。底部阻障層116 可包含氮化鈦（titanium nitride，TiN)，但不限於此，而犧牲 層118則可包含多晶矽材料。值得注意的是，本較佳實施例 係與先閘極介電層（high-K first)製程整合，因此閘極介電層 114係包含high-K材料，其可以是一金屬氧化物層，例如一 稀土金屬氧化物層。High-K閘極介電層114係可選自氧化铪 (hafnium oxide ’ Hf02)、矽酸铪氧化合物(hafniurn silicon oxide ’ HfSi04)、矽酸铪 Ι氧化合物（hafnium silicon oxynitride，HfSiON)、氧化鋁（aluminum oxide，Al2〇3)、氧 化鑭（lanthanum oxide，La203)、氧化钽(tantalum oxide， Ta2〇5)、乳化紀（yttrium oxide，Y2O3)、氧化錯(zirconium oxide ’ Zr02)、鈦酸錄（strontiumtitanate oxide，SrTi03)、矽酸 锆氧化合物（zirconium silicon oxide，ZrSi04)、鍅酸铪 (hafnium zirconium oxide ’ HfZr04)、勰鉍鈕氧化物(strontium s 6 201248852 bismuth tantalate，SrBi2Ta2〇9, SBT)、錯鈦酸錯(lead zirconate titanate， PbZrxTikO〕，PZT)與鈦酸鎖錄(barium strontium titanate，BaxSi^TiOh BST)所組成之群組。 請繼續參閱第1圖。接下來，係進行一 ALD方法120， 於基底100及虛置閘極110上形成一 SiCN封層122，SiCN 封層122具有一厚度，且該厚度係小於40埃（angstrom)。熟 習該項技藝之人士應知，ALD方法120乃利用製程氣體與材 料表面進行化學吸附反應，而於該材料表面上形成所欲獲得 的膜層。而在本較佳實施例中，ALD方法120包含一通入前 趨物（precursor)之步驟，且該前趨物包含二矽乙烷(disilane， DIS)、二氣石夕甲院（dichlorosilane，DCS)、六氣石夕乙焼 (hexa-chloride-disilane，HCD)或石夕烧（silane)，但不限於此。 更重要的是，本較佳實施例所提供之ALD方法120更包含 了通入碳氫化物(hydrocarbon，CxHy)氣體之步驟，且該碳氫 化合物包含乙烯(ethylene，C2H4)，但不限於此。另外值得注 意的是，本較佳實施例所提供之ALD方法120係以不採用 電漿為佳。 根據本較佳實施例，係利用碳氫化合物，例如乙稀中所 含有的碳作為SiCN封層122中碳原子的來源，因此可於基 底100與虛置閘極110上形成SiCN封層122。更重要的是， 根據本較佳實施例所提供的ALD方法120所形成的SiCN封 201248852 層122為一具有較低濕蝕刻率的緻密膜層，且其濕蝕刻率濕 名虫刻率係小於5。請參閱表格一 ’表格一為根據本較佳實施 例提供之ALD方法120所形成之SiCN封層122與利用其他 方法形成之膜層之濕蝕刻率比較： 表格一 膜層 SiCN SiN 形成 方法 ALD CVD PEALD 前趨 物 DCS BTBAS CHCD DIS HCD DCS 製程 溫度 630〇C 550〇C 580〇C 700°C 580〇C 450〇C 500°C 550〇C DHF 濕蚀 刻率 0.91 6.31 6.06 9.74 28.69 33.54 15.60 7.94 磷酸 濕1虫 刻率 4.72 27.81 45.00 94.57 249.00 170.99 112.90 73.88 折射 係數 (RI) 2.01 1.9 2.05 1.96 2.01 1.89 1.92 1.95 單位：埃/分鐘 201248852 表格一比較了利用本較佳實施例所提供的ALD方法120 所形成的SiCN封層122、利用化學氣相沈積（chemical vapor deposition，CVD)方法形成的SiCN或SiN膜層、以及利用 電漿輔助原子層沈積(plasma enhanced ALD，PEALD)方法形 成的SiN膜層的濕触刻率。另外，表格一更比較了於CVD 方法中通入不同前趨物（如二（特丁基氨基）矽烷 (bis(tertiary-butylamino)silane，BTBAS)、碳源六氯乙石夕燒 (carbon-sourced hexachloride disilane，CHCD)、二石夕乙烧(DIS) 與六氣乙石夕烧(hexachloride disilane，HCD)作為前趨物所產 生的膜層，以及於PEALD製程中通入DCS但利用不同溫度 所產生的膜層之濕蝕刻率。由表格一可知，根據本較佳實施 例所提供的ALD方法120所形成的SiCN封層122，不論是 在利用峨酸或稀釋氫氟酸(diluted hydrofluoric acid，DHF)的濕触 刻製程中，其濕蝕刻率皆低於5，與習知技術中利用CVD製 程或PEALD製程以及其他前趨物所形成的SiCN膜層或SiN 膜層相比，其濕蝕刻率更是如表格一所示遠低於該等膜層。 請參閱第2圖與第3圖。在完成SiCN封層122之製作後， 係如第2圖所示於虛置閘極110兩側之基底100内分別形成 一輕摻雜汲極(lightly-doped drain，LDD) 130。隨後係如第3 圖所示，於基底100與虛置閘極110上形成一絕緣層132， 絕緣層132較佳為氧化矽層，但不限於此。 201248852 請參閱第4圖。接下來，係回蝕刻絕緣層132與SiCN封 層122，而於虛置閘極110之周圍形成一側壁子134。如第4 圖所示，側壁子134係包含絕緣層132與具有L字形狀的 SiCN封層122所建構。而在完成側壁子134之製作後，係 於側壁子134兩側之基底100内分別形成一源極/汲極136 , 並完成半導體元件150之製作。值得注意的是，在回敍刻絕 緣層132與SiCN封層122時，由於SiCN封層122的濕钮 刻率極低，因此可確保在形成側壁子134時，被siCN封層 122保護的high-K閘極介電層114完全不受到回触刻製程的 影響。 更重要的是，在半導體製程中常結合選擇性應力系統 (selective strain scheme，SSS)等製程，例如利用選擇性磊晶 成長（selective epitaxial growth，SEG)方法來製作源極/汲極 136。SSS製程係於側壁子134兩側之基底1〇〇内先分別形 成一凹槽（圖未示），並經過適當的濕式凹槽清洗製程後， 利用SEG方法於凹槽内分別形成適用於p型半導體元件的 包含有錯化石夕（SiGe)之蠢晶層，或適用於η型半導體元件的 包含有碳化矽（SiC)之磊晶層，用以作為源極/汲極ι36β而本 較佳實施例所提供的SiCN封層122因具有較低濕蝕刻率的 優點，可確保high-K閘極介電層114在製作凹槽或濕式凹槽 清洗製程中皆受到SiCN封層122之保護而不致被影響。 201248852 另外，熟習該項技藝之人士應知，在完成源極/及極13 ό 之製作後，習知技術常於源極/汲極136表面形成一用以降低 接觸界面電阻之金屬矽化物（silicide)(圖未示）。而金屬石夕化 物之製作首先係於基底上形成一金屬層，隨後進行一熱處 理，使金屬層與源極/汲極136内的矽反應，而生成過渡 (transitional)金屬矽化物。隨後’利用一濕蝕刻製裎移除未 反應的金屬，並再度利用一熱處理將過渡金屬矽化物轉化成 為金屬矽化物。而本較佳實施例所提供的SiCN封層122因 具有較低濕蝕刻率的優點，可確保high-κ閘極介電層114 在用以移除未反應金屬的濕蝕刻製程中受到siCN封層122 之保護而不致被影響。 請參閱第5圖。接下來’係於基底ι〇〇與虛置閘極n〇 上依序形成一接觸洞蚀刻停止層（c〇ntact etch stop layer，以 下間稱為 CESL) 140 與一内層介電（inter_iayer dieiectric，以 下簡稱為ILD)層142。待完成CESL 140與ILD層142之製 作後，係進行一平坦化製程移除部分的ILD層142、CESL 140 與圖案化硬遮罩，而暴露出虛置閘極110的犧牲層118。隨 後，係進行一蝕刻製程移除犧牲層118，而形成一閘極溝渠 144。此時’底部阻障層116係可作為一蝕刻停止層，用以 保護high-K閘極介電層114。如前所述，由於本較佳實施例 係採用先閘極介電層製程整合，因此high-K閘極介電層114 201248852 並未與犧牲層118 —同移除。 請參閱第6圖。隨後係於閘極溝渠144内的high-K閘極 介電層114上依序形成一功函數金屬層160、一頂部阻障層 162與一填充金屬層164。此外，在底部阻障層116與功函 數金屬層160之間亦可依製程或產品需要更設置一#刻停止 層。功函數金屬層160係依半導體元件150之導電形式可選 用合適的材料，舉例來說，當半導體元件150為η型半導體 元件時’功函數金屬層160可包含功函數為3.9電子伏特（eV) 〜4.3 eV的金屬材料；而當半導體元件150為p型半導體元 件時，功函數金屬層160可包含功函數為4.8 eV〜5.2 eV的 金屬材料。由於功函數金屬層160之材料選擇係為該領域中 所熟知者，故於此係不加以贅述。頂部阻障層162可包含 TiN，但不限於此。填充金屬層164則可選擇具有優良填充 能力與較低阻值的金屬或金屬氧化物，例如銘（aluminum， A1)、紹化鈦（titanium aluminide，TiAl)或氧化紹鈦（titanium aluminum oxide，TiAlO)，但不限於此。 請繼續參閱第6圖。最後，進行一平坦化製程，例如一 CMP製程，用以移除多餘的填充金屬層164、頂部阻障層ι62 與功函數金屬層160,而完成金屬閘極ll〇a之製作。且如第 6圖所示，本較佳實施例中high-K閘極介電層114之剖面結 構係具有--字形狀，設置於high-K閘極介電層114上的金 201248852 屬問極110a之功函數金屬層160與頂部阻障層162之剖面 結構係具有一 U字形狀，而SiCN封層122係可視為設置於 high K閘極介電層114與金屬閘極11 〇a之側壁。此外，本 實施例亦可再選擇性去除ILD層142與CESL 140等，然後 重新形成CESL與介電層，以有效提升半導體元件的電性表 現。 根據本發明所提供之金屬閘極結構及其製作方法，係利 用ALD方法120,於金屬閘極閘極介電層112 之側壁提供一具有較低濕蝕刻率的SiCN封層122。由於 SiCN封層122的濕蝕刻率較低，因此可於後續蝕刻或清洗 製程中’例如SEG凹槽蝕刻與清洗製程、金屬矽化物所需 之用以移除未反應金屬的蝕刻製程，以及半導體製程中任何 必需的濕式清洗製程，皆得以有效地保護high-K閘極介電 層114，避免high-K閘極介電層114氧化，進而避免因氧化 導致的效能降低問題。 請參閱第7圖至第10圖，第7圖至第10圖係為本發明 所提供之金屬閘極結構之製作方法之一第二較佳實施例之 示意圖，且本較佳實施例仍採用後閘極製程。如第7圖所示， 首先提供一基底200，如一矽基底、含矽基底、或SOI基底 等，且基底200内係形成有複數個用以提供電性隔離的STI 202。接下來，係於基底200上形成一虛置閘極210,而虛置 13 201248852 閘極210則包含一閘極介電層212與一犧牲層218、以及— 圖案化硬遮罩（圖未示），該等膜層係由下而上依序增叠於 基底200上，且閘極介電層212係設置於犧牲層218與基底 200之間。另外如前所述，犧牲層218則可包含多晶石夕材料。 值得注意的是，本較佳實施例係與後閘極介電層（high-K last) 製程整合’因此閘極介電層2 1 2較佳為一傳統的二氧化;ς夕層。 請繼續參閱第7圖。接下來，係進行一 ALD方法220， 於基底200及虛置閘極210上形成一 SiCN封層222，SiCN 封層222具有一厚度，且該厚度係小於40埃。在本較佳實 施例中’ ALD方法220包含一通入前趨物之步驟，且該前趨 物包含DIS、DCS、HCD或矽烷，但不限於此。更重要的是， 本較佳實施例所提供之ALD方法220更包含了通入碳氫化 物（CxHy)氣體之步驟，且該碳氫化合物包含乙烯(c2H4)，但 不限於此。另外值得注意的是，本較佳實施例所提供之ALD 方法220係以不採用電漿為佳。 根據本較佳實施例，係利用碳氫化合物，例如乙稀中所 含有的碳作為SiCN封層222中碳原子的來源，因此可於基 底200與虛置閘極210上形成siCN封層222。更重要的是， 根據本較佳實施例所提供的ALD方法220所形成的SiCN封 層222具有較低的濕蝕刻率，且其濕蝕刻率濕蝕刻率係小於 5。此外’根據本較佳實施例提供之ALD方法220所形成之 201248852, which is referred to as "SlCN" seal layer. And a metal function layer of the shape function is disposed on the 201248852 high-K gate dielectric layer. According to the patent application scope of the present invention, a method for fabricating a metal gate structure is provided. The fabrication method first provides a substrate having a dummy gate formed thereon, and the dummy gate includes at least one sacrifice. Next, an atomic layer deposition (hereinafter referred to as ALD) method is performed, a SiCN seal layer is formed on the substrate and the dummy gate, and the ALD method further includes a hydrocarbon (hydr) 〇carb〇n, CxHj gas. After the SiCN seal layer is formed, the sacrificial layer of the dummy gate is removed to form a gate trench on the substrate, and finally a metal is formed in the gate trench The metal gate structure and the manufacturing method thereof according to the present invention are formed by using an ALD method to form a lower wet residual ratio on the sidewalls of the metal gate and the high_K gate dielectric layer (wet The etching rate of the SiCN seal is low due to the low wet etching rate of the SiCN seal layer, so that the high-K gate dielectric layer can be effectively protected in the subsequent etching or cleaning process, and the high_K gate dielectric layer is prevented from being oxidized. Enter Therefore, the problem of the performance reduction caused by oxidation is avoided. Therefore, the method for fabricating the metal gate structure provided by the present invention can provide a metal gate structure having a good reliability. & [Embodiment] Please refer to the first FIG. 6 to FIG. 6 are diagrams showing a first preferred embodiment of a method for fabricating a metal gate structure provided by the present invention 5 201248852; and the preferred embodiment adopts a rear gate A gatelast process. As shown in FIG. 1 , a substrate 100 is first provided, such as a substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate, and the substrate 100 is formed therein. A plurality of shallow trenches (STI) 102 for providing electrical isolation. Next, a dummy gate 110' is formed on the substrate 1 and the dummy gate 11 is included. An interfaciai layer 112, a gate dielectric layer 114, a bottom barrier layer 116, a sacrificial layer 118, and a patterned hard mask (not shown), the layers Stacked on the substrate 1 from bottom to top The bottom barrier layer 116 may comprise titanium nitride (TiN), but is not limited thereto, and the sacrificial layer 118 may comprise a polysilicon material. It is noted that the preferred embodiment is a gate dielectric layer. (high-K first) process integration, such that the gate dielectric layer 114 comprises a high-K material, which may be a metal oxide layer, such as a rare earth metal oxide layer. The high-K gate dielectric layer 114 can be selected from the group consisting of hafnium oxide 'Hf02, hafniurn silicon oxide 'HfSi04, hafnium silicon oxynitride (HfSiON), and oxidation. Aluminum oxide (Al2〇3), lanthanum oxide (La203), tantalum oxide (Ta2〇5), yttrium oxide (Y2O3), zirconium oxide 'Zr02), titanic acid (strontiumtitanate oxide, SrTi03), zirconium silicon oxide (ZrSi04), hafnium zirconium oxide 'HfZr04, strontium s 6 201248852 bismuth tantalate, SrBi2Ta2〇9, SBT ), a group of lead zirconate titanate (PbZrxTikO), PZT) and barium strontium titanate (BaxSi^TiOh BST). Please continue to see Figure 1. Next, an ALD method 120 is performed to form a SiCN cap layer 122 on the substrate 100 and the dummy gate 110. The SiCN cap layer 122 has a thickness and the thickness is less than 40 angstroms. Those skilled in the art will recognize that the ALD method 120 utilizes a process gas to chemically react with the surface of the material to form a desired layer on the surface of the material. In the preferred embodiment, the ALD method 120 includes a step of introducing a precursor, and the precursor comprises disilane (DIS), dichlorosilane (DCS). ), hexa-chloride-disilane (HCD) or silane, but is not limited thereto. More importantly, the ALD method 120 provided by the preferred embodiment further includes a step of introducing a hydrocarbon (CxHy) gas, and the hydrocarbon comprises ethylene (ethylene, C 2 H 4 ), but is not limited thereto. . It is also worth noting that the ALD method 120 provided by the preferred embodiment is preferably not plasma. According to the preferred embodiment, carbon contained in a hydrocarbon such as ethylene is used as a source of carbon atoms in the SiCN seal layer 122, so that the SiCN seal layer 122 can be formed on the substrate 100 and the dummy gate 110. More importantly, the SiCN seal 201248852 layer 122 formed according to the ALD method 120 provided by the preferred embodiment is a dense film layer having a lower wet etching rate, and the wet etching rate is less than the wet engraving rate. 5. Please refer to Table 1 'Table 1 for the wet etching rate of the SiCN sealing layer 122 formed by the ALD method 120 provided according to the preferred embodiment and the film layer formed by other methods: Table 1 film SiCN SiN forming method ALD CVD PEALD precursor DCS BTBAS CHCD DIS HCD DCS Process temperature 630〇C 550〇C 580〇C 700°C 580〇C 450〇C 500°C 550〇C DHF wet etching rate 0.91 6.31 6.06 9.74 28.69 33.54 15.60 7.94 Phosphoric acid wet 1 Insect rate 4.72 27.81 45.00 94.57 249.00 170.99 112.90 73.88 Refractive index (RI) 2.01 1.9 2.05 1.96 2.01 1.89 1.92 1.95 Unit: angstrom/minute 201248852 Table 1 compares the ALD method 120 provided by the preferred embodiment. SiCN cap layer 122, SiCN or SiN film layer formed by chemical vapor deposition (CVD) method, and wet touch of SiN film layer formed by plasma enhanced ALD (PEALD) method Engraving rate. In addition, Table 1 compares the different precursors in the CVD method (such as bis(tertiary-butylamino)silane (BTBAS), carbon source, and hexachloroethane (carbon-). Sourced hexachloride disilane, CHCD), hexahydrate disulfide (DIS) and hexachloride disilane (HCD) as precursors, and DCS in PEALD process but with different temperatures The wet etch rate of the resulting film layer. As can be seen from Table 1, the SiCN cap layer 122 formed by the ALD method 120 provided in accordance with the preferred embodiment, whether using tannic acid or diluted hydrofluoric acid , wet etching process of DHF), the wet etching rate is lower than 5, which is wet compared with the SiCN film layer or SiN film layer formed by the CVD process or the PEALD process and other precursors in the prior art. The etching rate is much lower than the film layers as shown in Table 1. Please refer to Figures 2 and 3. After the fabrication of the SiCN cap layer 122 is completed, the dummy gate 110 is shown in Figure 2. Lightly doped drains are formed in the substrates 100 on both sides LDD) 130. Subsequently, as shown in FIG. 3, an insulating layer 132 is formed on the substrate 100 and the dummy gate 110, and the insulating layer 132 is preferably a hafnium oxide layer, but is not limited thereto. 201248852 Please refer to FIG. Next, the insulating layer 132 and the SiCN sealing layer 122 are etched back, and a sidewall spacer 134 is formed around the dummy gate 110. As shown in FIG. 4, the sidewall spacer 134 includes an insulating layer 132 and has an L-shape. The shape of the SiCN seal layer 122 is constructed. After the fabrication of the sidewall spacers 134, a source/drain 136 is formed in the substrate 100 on both sides of the sidewall spacers 134, and the fabrication of the semiconductor device 150 is completed. When the insulating layer 132 and the SiCN sealing layer 122 are etched back, since the wet buttoning ratio of the SiCN sealing layer 122 is extremely low, the high-K protected by the siCN sealing layer 122 when the sidewall spacers 134 are formed can be ensured. The gate dielectric layer 114 is completely unaffected by the touchback engraving process. More importantly, in the semiconductor process, a selective strain scheme (SSS) process, such as selective epitaxial growth (selective epitaxial growth) is often used. Growth, SEG) method to make the source / The pole 136. The SSS process is formed in the substrate 1 两侧 on both sides of the side wall 134 to form a groove (not shown), and after a suitable wet groove cleaning process, the SEG method is used in the groove respectively. Forming a staggered layer containing a distorted SiGe (pGe) suitable for a p-type semiconductor element, or an epitaxial layer containing tantalum carbide (SiC) suitable for an n-type semiconductor element, as a source/drain ι 36β The SiCN sealing layer 122 provided by the preferred embodiment has the advantage of lower wet etching rate, and ensures that the high-K gate dielectric layer 114 is protected by the SiCN seal during the process of making the groove or the wet groove cleaning process. The protection of layer 122 is not affected. 201248852 In addition, those skilled in the art should be aware that after the fabrication of the source/pole 13 完成 is completed, conventional techniques often form a metal telluride on the surface of the source/drain 136 to reduce the contact interface resistance ( Silicide) (not shown). The metallization is first formed by forming a metal layer on the substrate, followed by a heat treatment to react the metal layer with the germanium in the source/drain 136 to form a transition metal halide. Subsequently, the unreacted metal is removed by a wet etching process, and the transition metal halide is again converted into a metal halide by a heat treatment. The SiCN sealing layer 122 provided by the preferred embodiment has the advantage of lower wet etching rate, and ensures that the high-κ gate dielectric layer 114 is subjected to siCN sealing in a wet etching process for removing unreacted metal. The protection of layer 122 is not affected. Please refer to Figure 5. Next, a contact hole etch stop layer (hereinafter referred to as CESL) 140 and an inner layer dielectric (inter_iayer dieiectric) are sequentially formed on the substrate ι〇〇 and the dummy gate n〇. Hereinafter referred to as ILD) layer 142. After the CESL 140 and ILD layer 142 are completed, a planarization process removes portions of the ILD layer 142, the CESL 140, and the patterned hard mask to expose the sacrificial layer 118 of the dummy gate 110. Thereafter, an etching process is performed to remove the sacrificial layer 118 to form a gate trench 144. At this time, the bottom barrier layer 116 serves as an etch stop layer for protecting the high-K gate dielectric layer 114. As previously mentioned, since the preferred embodiment uses a gate dielectric layer process integration, the high-K gate dielectric layer 114 201248852 is not removed as the sacrificial layer 118. Please refer to Figure 6. A work function metal layer 160, a top barrier layer 162 and a fill metal layer 164 are sequentially formed on the high-K gate dielectric layer 114 in the gate trench 144. In addition, a stop layer may be further disposed between the bottom barrier layer 116 and the work function metal layer 160 depending on the process or product requirements. The work function metal layer 160 may be selected from a suitable material depending on the conductive form of the semiconductor device 150. For example, when the semiconductor device 150 is an n-type semiconductor device, the work function metal layer 160 may include a work function of 3.9 electron volts (eV). ~4.3 eV metal material; and when the semiconductor element 150 is a p-type semiconductor element, the work function metal layer 160 may comprise a metal material having a work function of 4.8 eV to 5.2 eV. Since the material selection of the work function metal layer 160 is well known in the art, it will not be described here. The top barrier layer 162 may include TiN, but is not limited thereto. The filling metal layer 164 may select a metal or metal oxide having excellent filling ability and lower resistance, such as aluminum (A1), titanium aluminide (TiAl) or titanium aluminum oxide (TiAlO). ), but not limited to this. Please continue to see Figure 6. Finally, a planarization process, such as a CMP process, is performed to remove the excess fill metal layer 164, the top barrier layer ι62, and the work function metal layer 160 to complete the fabrication of the metal gate 〇a. As shown in FIG. 6, the cross-sectional structure of the high-K gate dielectric layer 114 in the preferred embodiment has a ---word shape, and the gold 201248852 is disposed on the high-K gate dielectric layer 114. The cross-sectional structure of the work function metal layer 160 and the top barrier layer 162 of the pole 110a has a U-shape, and the SiCN seal layer 122 can be regarded as being disposed between the high K gate dielectric layer 114 and the metal gate 11 〇a. Side wall. In addition, the present embodiment can selectively remove the ILD layer 142 and the CESL 140 and the like, and then reform the CESL and the dielectric layer to effectively improve the electrical performance of the semiconductor device. According to the metal gate structure provided by the present invention and the method of fabricating the same, the SiC method 120 is used to provide a SiCN seal layer 122 having a lower wet etch rate on the sidewall of the metal gate gate dielectric layer 112. Since the wet etching rate of the SiCN capping layer 122 is low, it can be used in a subsequent etching or cleaning process, such as an SEG trench etching and cleaning process, an etching process for removing unreacted metal required for metal germanium, and a semiconductor. Any necessary wet cleaning process in the process can effectively protect the high-K gate dielectric layer 114 from oxidation of the high-K gate dielectric layer 114, thereby avoiding the performance degradation caused by oxidation. Please refer to FIG. 7 to FIG. 10 . FIG. 7 to FIG. 10 are schematic diagrams showing a second preferred embodiment of a method for fabricating a metal gate structure according to the present invention, and the preferred embodiment is still used. Rear gate process. As shown in Fig. 7, a substrate 200 such as a germanium substrate, a germanium-containing substrate, or an SOI substrate is provided first, and a plurality of STIs 202 for providing electrical isolation are formed in the substrate 200. Next, a dummy gate 210 is formed on the substrate 200, and the dummy 13 201248852 gate 210 includes a gate dielectric layer 212 and a sacrificial layer 218, and a patterned hard mask (not shown) The film layers are sequentially stacked on the substrate 200 from bottom to top, and the gate dielectric layer 212 is disposed between the sacrificial layer 218 and the substrate 200. Additionally as previously described, the sacrificial layer 218 may comprise a polycrystalline material. It should be noted that the preferred embodiment is integrated with the high-K last process. Thus, the gate dielectric layer 2 1 2 is preferably a conventional oxidized layer; Please continue to see Figure 7. Next, an ALD method 220 is performed to form a SiCN cap layer 222 on the substrate 200 and the dummy gate 210. The SiCN cap layer 222 has a thickness and the thickness is less than 40 angstroms. In the preferred embodiment, the ALD method 220 includes a step of introducing a precursor, and the precursor comprises DIS, DCS, HCD or decane, but is not limited thereto. More importantly, the ALD method 220 provided by the preferred embodiment further includes the step of introducing a hydrocarbon (CxHy) gas, and the hydrocarbon comprises ethylene (c2H4), but is not limited thereto. It is also worth noting that the ALD method 220 provided by the preferred embodiment is preferably not plasma. According to the preferred embodiment, carbon contained in a hydrocarbon such as ethylene is used as a source of carbon atoms in the SiCN seal layer 222, so that the siCN seal layer 222 can be formed on the substrate 200 and the dummy gate 210. More importantly, the SiCN seal layer 222 formed in accordance with the ALD method 220 provided by the preferred embodiment has a lower wet etch rate and a wet etch rate wet etch rate of less than 5. Further, the ALD method 220 provided according to the preferred embodiment is formed by 201248852.
SiCN封層222與利用其他方法形成之膜層之濕蝕刻率比較 係同於表格一，故於此係不再贅述。由表格一可知，根據本 較佳實施例所提供的ALD方法220所形成的SiCN封層 222，不論是在利用磷酸或稀釋氫氟酸的濕蝕刻製程中，其 濕蝕刻率皆低於5，與習知技術中利用CVD方法或pEALD 方法以及其他前趨物所形成的SiCN膜層或SiN膜層相比， 其濕姓刻率係如表格一所示遠低於該等膜層。 請參閱第8圖。在完成SiCN封層222之製作後，係如第 8圖所不於虛置閘極21〇兩側之基底2〇〇内分別形成一 lDD 230 15¾後於基底2〇〇與虛置閘極21 〇上形成一絕緣層232， 且絕緣層232較佳為氧化矽層，但不限於此。請繼續參閱第 8圖。接下來，係回蝕刻絕緣層232與siCN封層222，而於 虛置閘極210之周圍形成—側壁子234。如第8圖所示，側 壁子234係包含絕緣層232與具有L字形狀的SiCN封層222 所建構。而在完成側壁子234之製作後，係於側壁子234兩 側之基底200内分別形成一源極/汲極236，並完成半導體元 件250之製乍。由於上述步驟係與第一較佳實施例相同，因 此該等步驟細節係可參閱第2圖至第4圖之相關說明，故於 此係不再贅述。The wet etching rate of the SiCN sealing layer 222 and the film layer formed by other methods are the same as those in Table 1, and therefore will not be described again. As can be seen from Table 1, the SiCN sealing layer 222 formed by the ALD method 220 provided by the preferred embodiment has a wet etching rate of less than 5 in a wet etching process using phosphoric acid or dilute hydrofluoric acid. Compared with the SiCN film layer or the SiN film layer formed by the CVD method or the pEALD method and other precursors in the prior art, the wetness rate is much lower than that of the film layers as shown in Table 1. Please refer to Figure 8. After the fabrication of the SiCN cap layer 222 is completed, a lDD 230 152⁄4 is formed in the substrate 2〇〇 on both sides of the dummy gate 21〇 as shown in FIG. 8, and then the substrate 2 and the dummy gate 21 are formed. An insulating layer 232 is formed on the crucible, and the insulating layer 232 is preferably a hafnium oxide layer, but is not limited thereto. Please continue to see Figure 8. Next, the insulating layer 232 and the siCN capping layer 222 are etched back, and the sidewall spacers 234 are formed around the dummy gate 210. As shown in Fig. 8, the side wall 234 is constructed by including an insulating layer 232 and an SiCN sealing layer 222 having an L shape. After the fabrication of the sidewalls 234 is completed, a source/drain 236 is formed in the substrate 200 on both sides of the sidewall 234, and the fabrication of the semiconductor device 250 is completed. Since the above steps are the same as those of the first preferred embodiment, the details of the steps can be referred to the related descriptions of Figs. 2 to 4, and therefore will not be described again.
請繼續參閱第8圖。接下來，係於基底200與虛置閘極 210上依序形成一 CESL240與一 ILD層242。待完成CESL 15 201248852 240與ILD層242之製作後，係進行一平坦化製程移除部分 的ILD層242、CESL 240與圖案化硬遮罩，而暴露出虛置閘 極210的犧牲層218。隨後，係進行一蝕刻製程移除犧牲層 218，而形成一閘極溝渠244。此時，閘極介電層212可作為 一蝕刻停止層，用以保護基底200。如前所述，由於本較佳 實施例係採用後閘極介電層製程整合，因此部分的閘極介電 層212係於移除犧牲層218時被消耗而移除，並於移除犧牲 層218之後暴露於閘極溝渠244之底部，且於後續製程中作 為一介質層212。另外，在本較佳實施例之一變化型中，閘 極介電層亦可於此時全部移除，並重新形成一介質層212。 請參閱第9圖。隨後係於閘極溝渠244内的介質層212 上依序形成一 high-K閘極介電層214、一底部阻障層216、 一功函數金屬層260、一頂部阻障層262與一填充金屬層 264。此外，在底部阻障層216與功函數金屬層260之間亦 可依製程或產品需要更設置一蝕刻停止層。如前所述， high-K 閘極介電層 214 係可選自 Hf02、HfSi04、HfSiON、 Al2〇3、La203、Ta205、Y203、Zr02、SrTi〇3、ZrSi〇4、HfZr〇4 所組成之群組。功函數金屬層260係依半導體元件250之導 電形式可選用合適的材料，舉例來說，當半導體元件250為 η型半導體元件時，功函數金屬層260可包含功函數為3.9 eV 〜4.3 eV的金屬材料；而當半導體元件250為p型半導體元 件時，功函數金屬層260可包含功函數為4.8 eV〜5.2 eV的 16 201248852 金屬材料。由於功函數金屬層260之材料選擇係、為域 所熟知者，故於此係不加以贅述。底部阻隆 - #屬216與頂部阻 障層262可包含TiN，但不限於此。填夯厶思θ 丹疋隹屬層264則可選 擇具有優良填充能力與較低阻值的金屬或金屬氣化物，例如 Al、TiAl或氧化铭鈦TiAlO，但不限於此。 請參閱帛10 ffi。最後，進行一平坦化製程，例如 製程’用以移除多餘的填充金屬層264、頂部阻障層262、 功函數金屬層260、底部阻障層閑極S介電層 214，而完成金屬閘極210a之製作。且如第1〇圖所示，本 較佳實施例中high-K閘極介電層214、底部阻障層216、功 函數金屬層260、與頂部阻障層262之剖面結構係具有一 u 字形狀’且high-K閘極介電層214係設置於SiCN封層222 與金屬閘極210a之間。此外，本實施例可選擇性地去除ild 層242與CESL240等，然後重新形成CESL與介電層，以 有效提升半導體元件的電性表現。如前所述，由於本較佳實 施例所提供的SiCN封層222具有較低濕蝕刻率的優點，可 故可確保high-K閘極介電層214在用以移除CESL 240與 ILD層242時受到SiCN封層222之保護而不致被影響。 根據本發明所提供之金屬閘極結構及其製作方法，係利 用ALD方法220,於金屬閘極21〇a與high-K閘極介電層212 之側壁提供一具有較低濕蝕刻率的SiCN封層222。由於 17 201248852Please continue to see Figure 8. Next, a CESL 240 and an ILD layer 242 are sequentially formed on the substrate 200 and the dummy gate 210. After the fabrication of CESL 15 201248852 240 and ILD layer 242 is completed, a flattening process removes portions of ILD layer 242, CESL 240, and patterned hard mask to expose sacrificial layer 218 of dummy gate 210. Subsequently, an etching process is performed to remove the sacrificial layer 218 to form a gate trench 244. At this time, the gate dielectric layer 212 can serve as an etch stop layer for protecting the substrate 200. As described above, since the preferred embodiment employs a post-gate dielectric layer process integration, a portion of the gate dielectric layer 212 is removed and removed when the sacrificial layer 218 is removed, and is sacrificed for removal. Layer 218 is then exposed to the bottom of gate trench 244 and acts as a dielectric layer 212 in subsequent processes. In addition, in a variation of the preferred embodiment, the gate dielectric layer can also be completely removed at this time and a dielectric layer 212 is reformed. Please refer to Figure 9. A high-K gate dielectric layer 214, a bottom barrier layer 216, a work function metal layer 260, a top barrier layer 262, and a fill are sequentially formed on the dielectric layer 212 in the gate trench 244. Metal layer 264. In addition, an etch stop layer may be further disposed between the bottom barrier layer 216 and the work function metal layer 260 depending on the process or product requirements. As described above, the high-K gate dielectric layer 214 may be selected from the group consisting of Hf02, HfSi04, HfSiON, Al2〇3, La203, Ta205, Y203, Zr02, SrTi〇3, ZrSi〇4, and HfZr〇4. Group. The work function metal layer 260 may be selected from a suitable material according to the conductive form of the semiconductor device 250. For example, when the semiconductor device 250 is an n-type semiconductor device, the work function metal layer 260 may include a work function of 3.9 eV to 4.3 eV. Metal material; and when semiconductor component 250 is a p-type semiconductor component, work function metal layer 260 may comprise 16 201248852 metal material having a work function of 4.8 eV to 5.2 eV. Since the material selection system of the work function metal layer 260 is well known to the domain, it will not be described here. The bottom barrier - #属216 and top barrier layer 262 may comprise TiN, but is not limited thereto. Filling the θ θ Tanzanite layer 264 may select a metal or metal vaporizer having excellent filling ability and lower resistance, such as Al, TiAl or oxidized titanium TiAlO, but is not limited thereto. See 帛10 ffi. Finally, a planarization process is performed, such as a process 'to remove excess fill metal layer 264, top barrier layer 262, work function metal layer 260, bottom barrier layer idle S dielectric layer 214, and complete the metal gate. Production of pole 210a. As shown in FIG. 1 , in the preferred embodiment, the high-K gate dielectric layer 214, the bottom barrier layer 216, the work function metal layer 260, and the top barrier layer 262 have a cross-sectional structure. The word shape 'and the high-K gate dielectric layer 214 is disposed between the SiCN seal layer 222 and the metal gate 210a. In addition, the present embodiment can selectively remove the ild layer 242 and the CESL 240 and the like, and then reform the CESL and the dielectric layer to effectively improve the electrical performance of the semiconductor device. As described above, since the SiCN seal layer 222 provided by the preferred embodiment has the advantage of a lower wet etch rate, it is ensured that the high-K gate dielectric layer 214 is used to remove the CESL 240 and ILD layers. At 242, it is protected by the SiCN seal layer 222 without being affected. According to the metal gate structure and the method of fabricating the same according to the present invention, an ALD method 220 is used to provide a SiCN having a lower wet etching rate on sidewalls of the metal gate 21a and the high-K gate dielectric layer 212. Sealing layer 222. Due to 17 201248852
SiCN封層222的濕蝕刻率較低，因此可於後續蝕刻或清洗 製程中，例如移除CESL 240與ILD層242所需之蝕刻製程， 以及半導體製程中任何必需的濕式清洗製程，皆得以有效地 保護high-K閘極介電層212，避免high_K閘極介電層212 氧化，進而避免因氧化導致的效能降低問題。 练上所述，根據本發明所提供之金屬閘極結構及其製作 方法，係利用一 ALD方法，於該金屬閘極與該high-K閘極 介電層之側壁形成—具有較低濕關率的緻密The SiCN encapsulation layer 222 has a low wet etch rate and can be used in subsequent etching or cleaning processes, such as etching processes required to remove the CESL 240 and ILD layers 242, as well as any necessary wet cleaning processes in the semiconductor process. The high-K gate dielectric layer 212 is effectively protected from oxidation of the high_K gate dielectric layer 212, thereby avoiding the performance degradation caused by oxidation. As described above, the metal gate structure and the method of fabricating the same according to the present invention are formed by using an ALD method on the sidewalls of the metal gate and the high-K gate dielectric layer - having a lower wet Density
SiCN封層。 ,;N封層的濕姓刻率較低，因此可於後續姓刻或清洗 製程中有效地保護high_K閘極介電層，避免high K間極介 電層氧化’進而避免因氧化導致的效能降低問題。因此，本 發明所提供之金相極結構之製作方法，係可提供—具有良 好可靠率之金屬閘極結構。 所做本發明之較佳實施例，凡依本發明申請專利範圍 =紇化/、修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 作方味圖至第6圖係為本發明所提供之金屬閘極結構之製 >之―第一較佳實施例之示意圖。 作方味'第1G_為本發明所提供之金相極結構之製 〆之第一較佳實施例之示意圖。 201248852 【主要元件符號說明】 100 ' 200 基底 102 > 202 淺溝隔離 110 、 210 虛置閘極 110a、210a 金屬閘極 112 、 212 介質層 114 、 214 高介電常數閘極介電層 116 、 216 底部阻障層 118 、 218 犧牲層 120 ' 220 原子層沈積方法 122 、 222 氮碳化矽封層 130 、 230 輕摻雜汲極 132 > 232 絕緣層 134 、 234 側壁子 136 、 236 源極/汲極 150 、 250 半導體元件 140 、 240 接觸洞蝕刻停止層 142 、 242 内層介電層 144 、 244 閘極溝渠 160 、 260 功函數金屬層 162 、 262 頂部阻障層 19 201248852 164 、 264 填充金屬層SiCN seal layer. , N seal layer has a low wet engraving rate, so it can effectively protect the high_K gate dielectric layer in the subsequent surname or cleaning process, avoiding the oxidation of the high K interlayer dielectric layer and avoiding the oxidation-induced performance. Reduce the problem. Therefore, the method for fabricating the metallographic pole structure provided by the present invention can provide a metal gate structure having good reliability. The preferred embodiments of the present invention are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS A schematic diagram to a sixth embodiment is a schematic view of a first preferred embodiment of the metal gate structure of the present invention. The first aspect of the invention is a schematic diagram of a first preferred embodiment of the metallographic pole structure provided by the present invention. 201248852 [Description of main component symbols] 100 '200 substrate 102 > 202 shallow trench isolation 110 , 210 dummy gate 110a , 210a metal gate 112 , 212 dielectric layer 114 , 214 high dielectric constant gate dielectric layer 116 , 216 bottom barrier layer 118, 218 sacrificial layer 120' 220 atomic layer deposition method 122, 222 niobium carbide sealing layer 130, 230 lightly doped gate 132 > 232 insulating layer 134, 234 sidewall 136, 236 source / Bungee 150, 250 semiconductor device 140, 240 contact hole etch stop layer 142, 242 inner dielectric layer 144, 244 gate trench 160, 260 work function metal layer 162, 262 top barrier layer 19 201248852 164, 264 fill metal layer