201248789 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路的製造方法，且特別是 有關於一種非揮發性記憶元件的製造方法。 【先前技術】 非揮發性記憶體元件可多次進行資料之存入、讀取、 抹除，且存入的資料在斷電後也不會消失，因此，已成為 個人電腦和電子設備廣泛採用的一種記憶體元件。 典型的非揮發性記憶體元件包括浮置閘(fl〇ating gate) 與控制閘(control gate)。控制閘是直接設置在浮置閘上，浮 置2與控制閘之間以介電層相隔，而浮置閘與基底之間是 以牙隧氧化層（tunneling 〇xide)相隔（亦即所謂堆疊閘極快 閃記憶體）。 目如所發展的非揮發性記憶體元件的浮置閘則位於 控制閘的兩側。控制閘是讀人溝渠的方式形成，控制問 :方的間介電層是在溝渠形成之後 ，且在控制閘形成之 月^利用沉積的方式形成，因此，隨著溝渠的高寬比逐漸 的沉積製程愈難以控制’所形成的閘介電層的不均 句度，兩’特別是其邊緣處的厚度遠小於中心的厚度，導 致邊緣處成為漏電的路徑，造紅件可靠度的問題。 【發明内容】 t發明提供〜種轉發性記憶元件的製造方法，其可 201248789 ’減少漏電，提升 以增加控侧下方之閘界電層的均句度 元件的可靠度。 在美麻！~ f供—種非揮發性記憶元㈣製造方法，包括 溝渠的堆疊結構。此堆疊結構包括第- 勺括^ -入Φ體層與第—頂蓋層依序堆疊於基底上，且 二電層位於溝渠侧壁上。接著，以至少兩種不同 的基底上形成閘介電層。之後， t導體層與第二頂蓋層。然後，移除第一 頂盍層，之後，再移除部分第一導電層。 依照本發明一實施例所述， 方法使付閘介電層的中心與邊緣 處不均勻度的定義為： 上述至少兩種不同的成膜 的不均勻度小於25%。此 不均勻度％ =(最大膜厚-最小膜厚)/(平均膜厚）χ ι〇〇% 依照本發明-實施例所述，上述形成閘介電層的步驟 包括.於溝渠底部的基底上形成襯層，再於襯層上 三介電層。 /依照本發明-實施例所述，上述用於形成概層的方法 係使得襯層的不均勻度低於第三介電層的不均句度。 依照本發明-實施例所述，上述形成#見層的方法包括 一製程方法，其可以使得襯層的不均勻度在ι〇%以下。 依照本發明一實施例所述，上述用來形成襯層之製程 方法包括熱氧化製程或原子層沉積製程。 201248789 依照本發明一實施例所述，上述熱氧化製程包括快速 熱氧化製程或臨場水汽生成(ISSG)製程。 依照本發明一實施例所述，用於形成襯層的方法的成 膜速率低於用於形成第三介電層的成膜速率。 / π，依照本發明一實施例所述，用於形成襯層的方法係使 得襯層的緻密度高於第三介電層的緻密度。 依照本發明一實施例所述，上述襯層之 介電層的厚度。 ^ ； 本發明之非揮發性記憶元件的製造方法，其可以增加 二=了方之閘界電層的均勻度，減少漏電，提升元“ 為，本發明之上述特徵和優點能更明顯易懂，下文特 舉貝施例，並配合所附圖式作詳細說明如下。 【實施方式】 圖1至7是依據本發明一實施例所繪示之— 性記^元件的製造方法的剖面示意圖。之種非_ 睛參照圖卜在基底1〇上形成介電 層14與笫—了百葚猛# ‘弟一導體 如是石夕，或者、曰基底10之材質例如是半導體，例 層，其材二介電層12是用來製作穿随介電 層的介電材料。= 夕2 ’或其他適合用，作穿隨介電 是化學氣相沉積法，之形成方法例如是熱氧化法，或 '或其他合適的方法。介電層ι2的厚度 201248789 例如是約為50至100埃。第—導 閘，其材質例如是摻雜的多晶石夕。體層14係用來製作浮置 法例如是利用化學氣相沈積法形^導體層14之形成方 行離子植入步驟以形成之。第一導未摻雜多晶矽層後，進 以是利用化學氣相沈積法形成摻層曰14之形成方法也可 摻雜。第一導體層14的厚度例^曰多6晶矽層並在臨場進行 第-頂蓋層16的材質例如是氮化:至2_埃。 的方法例如是化學IU目沈積法。第_/ f氮氧切’其形成 是約為1000至3000埃。 頂蓋層16的厚度例如 凊參照圖2，圖案化第一頂蓋 以形成溝渠18。圖案化的方法^ ^ [導體層14 ’ 之後，於A底10上形忐入Φ既和用微影與敍刻製程。 側壁以及；-頂蓋層：介\層二^ 或是多層材料層所構成之堆二。 錢切復切(⑽=㈣ί 如疋先以熱氧化法形成一層氧化石夕層後，利用 氧切層上形成氮化聲氧化魏化 乂堆疊層的厚度例如分別是約為20至80埃/ 介電層加之材質也可以是任何其他已知的介電材料。 參照圖3，移除溝渠18底部的介電層20及 八]；，層12，裸露出溝渠18底部的基底10表面， 遠下溝渠18側壁的介電層2〇。移除溝渠18底部的介電層 2〇的方法包括非等向性韻刻法，例如是乾式敍刻法。採用 非等向性敍刻法來移除溝渠18底部的介電層Μ的過程 201248789 110第上二ff層呈3上的介電層20也會被移除。至此，基 底；^成了八有溝渠18的堆疊結構4G，此堆叠社構40 層上 12、第一導體層14與第-頂蓋層16依序 ^豐於基底H)上，且包括第二介電層2q位於溝㈣的側 壁。 4，以至少兩種不同的成膜方法，於 5二上以及溝渠18之側壁形成介電層 再於基底K)上形成介電層24，㈣蓋第—頂蓋層;6後介 °襯層22與介電層24的材質可以相 22之形成方法與介電層24的形成方法不;更 22其中心與邊緣的不均勻度低於介電層 …中〜邊緣的不均勻度。不均勻度的定義如下： 不均勻度％ =(最大膜厚-最小膜厚)/(平均膜厚）X 100% 在-實施财，概層22所使用的製财法(成長或是沉 積），係可錢其不均勻度控制在職以下者。通常膜的均 勻度與成膜的速率有關’成膜的速率愈高職的均勻度愈 低。在一實施例中，襯層22所採用的形成方法的成膜 ，於=電層的成膜速率。從另一個角度來說，襯層22的緻 密度尚於介電層24的緻密度。襯層22所使用的製程方法 包括熱氧化製程或原子層沉積製程或其他合適用來成長襯 201248789 層的方法。熱氧化製程包括快速熱氧化製程(RTO)或臨場 水汽生成（in-situ steam generation，ISSG)製程。介電層 24的形成方法例如是化學氣相沉積法。在 層22之厚度小於介電層24的厚度。概層22之厚度例如是 1至200埃；介電層24的厚度例如是1〇〇至4〇〇埃。襯層 22與介電層24的厚度總和例如是1〇〇至6〇〇埃。在溝渠 18側壁的介電層24與介電層2〇是做為浮置閘與控制閘之 間的閘間介電層。在溝渠18底部的介電層24與襯層22 則是做為後續形成之控制閘與基底i 〇之間的閘介電層，其 中心與邊緣的不均勻度小於25〇/。。 ' 繼之，於基底上形成第二導體層26，第二導體層26 ，蓋介電層24並填人於溝渠18之中。第三導體層％之材 質例如是摻雜的多晶♦第二導體層26之形成方法例如是 利用化學—沈餘軸未# 入步驟以形成之。第二導^夂⑨仃離子植 化學氣相沈毅形麟^層形成方法也可以是利用 二導體層％的厚_^夕2夕層並在臨場進行摻雜。第 之後，請參照圖5，^ί_至麵埃。 第二導體層26與介電層2 = 4中第—頂蓋層16上方的 哲-.曾础战^ 24，並移除溝渠18之中一邱八沾 第二導體層26，使嵌於溝渠 =二: 26的高度低於第-頂蓋； 下从第-導體層 為100至1000埃。在」—、问度’其尚低差例如是約 1貫施例中，移除部分第二導體屛 戶ΓίΓ採用化學機械研磨法，以第3 i 層16為研磨終止層，胳楚 木]貝盖 一頂蓋層16上的第二導體層26 201248789 以及介電層24移除。之後，再利用回蝕刻製程將溝渠u 中一部分的第二導體層26移除。在另一實施例中，移^ 分的第二導體㉟26 #方法例如是可以直接利用回蚀刻 程將第-頂蓋層16上的第二導體層26移除，並繼續移^ 溝渠18中的部分第二導體層26。之後，移除第一頂蓋^ 16上的介電層24。留下來之嵌於溝渠18中的第二導^ 26係做為控制閘。 θ 接著，於溝渠18中的第二導體層26上形成第二頂蓋 層28 ^第二頂蓋層28的材質與第一頂蓋層16之^質不 同，其材質例如是氧化矽，厚度例如是約為5〇〇至&⑽ 埃。第二頂蓋層28的形成的方法例如是利用化學氣相沈積 法先沉積第二頂蓋材料層（未繪示），之後再以第一頂=層 16為移除終止層，移除第一頂蓋層16上的第二頂蓋材二 層。移除第一頂蓋層16上的第二頂蓋材料層 化學機械研磨法。 』疋 其後，請參照圖6，移除第一頂蓋層16，裸露出第一 導體，14。移除第—頂蓋層16的方法可以採祕刻製程， =是濕式蝴製程。之後，於基底1G上形成間隙壁材料 層川’覆蓋第一導體層14、介電層20、介電層24盘第二 =蓋層28。間隙壁材料層3㈣材質與第二頂蓋層28的材 不同，其材質例如是氮化矽，形成的方法例如是化學氣 相沈積法’厚度例如是約為100至600埃。 、，後。請參照圖7，非等向性蝕刻間隙壁材料層3〇， 以在介電層20的側壁上形成間隙壁3〇a，間隙壁3〇a覆蓋 201248789 部分苐一導雷恩 法。其後，㈣隙等向性飯刻的方法例如是乾式触刻 部分第-導體及第二頂蓋層28為罩幕，移除 層14的方法裸露出介電層12。移除部分第-導體 法。留下的第採用非等向性韻刻法，例如是乾式敍刻 為控制閘。介^電層14位於第二導體層％的關，做 電層Η(浮置=^與介電層2G組合制是做為第一導 層。介電ί^與第二導體層26(控制問)之間的問間介電 之間的閘介電層、襯層2 2組合後則是做為控制閘與基底1 〇 介電實關巾4雜_麟底之間的閘 ^電=^固步驟來形成，先形成均句度較高的概層，之 "用成膜速率較高的沉積方式來形成介電層。然 本=並不以此為限，控制閘與基底之間的閘介曰電層可以 而不限於2個步驟，實際在應用時， -你周整之，只要是第一個成膜步驟的膜均勻度 步驟者’而後續的成膜速率高於第一個成膜步驟 都疋本發明涵蓋之範圍。 綜上所述，本發明控制閘與基底之間的閘介電層可以 拆成Τ個步驟或更多的來形成，先在溝渠的底部形成均 勻度，向的襯層，減緩中心與邊緣處的高低差，進而可以 滅級尚寬比過高對於後續沈積製程所形成之介電層膜厚不 均的問題，之後，再利用成膜速率較高的沉積方式來形成 介電層，一方面可以提供閘介電層所需的總厚度，另一方 面可以增加製程的產出（throughput)，避免襯層的成膜速率 201248789 車又低而景〉響產出。因此，本發明之方法 本發日發㈣以實施顧露如上，然其並非用以限定 本^之ΪΓ屬技賴域巾科通常知識者，在不脫離 發^之和範肋，當可作些許之更動與潤飾，故本 ^ '、》蒦軏園當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1至7是依據本發明一實施例所繪示之一種非揮發 性記憶科的製造方法的剖面示意圖。 【主要元件符號說明】 10 :基底 12、2〇、24 :介電層 14 ' 26 :導體層 16 ' 28 :頂蓋層 18 ·溝渠 22 .铜^層 3〇 ·間隙壁材料層 3Ga :間隙壁 40 :堆疊結構 11201248789 VI. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing an integrated circuit, and more particularly to a method of manufacturing a non-volatile memory element. [Prior Art] Non-volatile memory components can store, read, and erase data multiple times, and the stored data will not disappear after power-off. Therefore, it has become widely used in personal computers and electronic devices. A memory component. Typical non-volatile memory components include a floating gate and a control gate. The control gate is directly disposed on the floating gate, and the floating layer 2 and the control gate are separated by a dielectric layer, and the floating gate and the substrate are separated by tunneling 〇xide (also called stacking) Gate flash memory). The floating gates of the non-volatile memory components developed are located on both sides of the control gate. The control gate is formed by reading the ditches. The control is: the inter-dielectric layer is formed after the trench is formed, and is formed by the deposition method during the formation of the control gate. Therefore, as the aspect ratio of the trench is gradually The more difficult the deposition process is to control the unevenness of the gate dielectric layer formed, the thickness of the two is particularly much smaller than the thickness of the center, resulting in a leakage path at the edge and a problem of reliability of the red component. SUMMARY OF THE INVENTION The invention provides a method for fabricating a type of transmissive memory element, which can reduce leakage current and increase the reliability of the uniformity element of the gate boundary layer under the control side. In the United States! ~ f for a non-volatile memory element (four) manufacturing method, including the stack structure of the trench. The stack structure comprises a first-spraying-in-the-Φ layer and a first-top layer stacked on the substrate in sequence, and the second electrical layer is located on the sidewall of the trench. Next, a gate dielectric layer is formed on at least two different substrates. Thereafter, the t-conductor layer and the second cap layer. Then, the first top layer is removed, and then a portion of the first conductive layer is removed. According to an embodiment of the invention, the method defines the unevenness at the center and the edge of the gate dielectric layer as: the inhomogeneity of the at least two different film formations is less than 25%. This unevenness % = (maximum film thickness - minimum film thickness) / (average film thickness) 〇〇 ι 〇〇 % According to the present invention - the embodiment, the step of forming the gate dielectric layer includes the substrate at the bottom of the trench A liner is formed thereon, and a third dielectric layer is formed on the liner. / In accordance with the present invention - the above-described method for forming a layer is such that the unevenness of the underlayer is lower than the unevenness of the third dielectric layer. In accordance with the present invention, the method of forming the layer is described as a process which allows the unevenness of the underlayer to be less than 〇%. According to an embodiment of the invention, the method for forming a liner includes a thermal oxidation process or an atomic layer deposition process. 201248789 In accordance with an embodiment of the invention, the thermal oxidation process includes a rapid thermal oxidation process or an on-site water vapor generation (ISSG) process. In accordance with an embodiment of the present invention, the film formation rate of the method for forming the underlayer is lower than the film formation rate for forming the third dielectric layer. / π, in accordance with an embodiment of the present invention, the method for forming the underlayer is such that the density of the underlayer is higher than the density of the third dielectric layer. According to an embodiment of the invention, the thickness of the dielectric layer of the liner layer. The method for manufacturing the non-volatile memory element of the present invention can increase the uniformity of the electric layer of the second gate, reduce the leakage, and enhance the element. Therefore, the above features and advantages of the present invention can be more clearly understood. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to FIG. 7 are schematic cross-sectional views showing a method of manufacturing a character device according to an embodiment of the present invention. The non- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The second dielectric layer 12 is used to fabricate a dielectric material that penetrates the dielectric layer. = 夕 2 ' or other suitable for use as a dielectric vapor deposition method, such as thermal oxidation, or 'Or other suitable method. The thickness of the dielectric layer ι2 201248789 is, for example, about 50 to 100 angstroms. The first guide is made of, for example, doped polycrystalline stone. The bulk layer 14 is used to make a floating method, for example. The formation of the conductor layer 14 by chemical vapor deposition After the first ion-doped polysilicon layer is formed, the formation method of forming the germanium layer 14 by chemical vapor deposition may also be performed. The thickness of the first conductor layer 14 is as follows. The ruthenium 6 ruthenium layer and the material of the first cap layer 16 are, for example, nitrided to 2 angstroms. The method is, for example, a chemical IU mesh deposition method. The _/f nitroxene is formed about The thickness of the cap layer 16 is, for example, 凊, referring to Fig. 2, the first cap is patterned to form the trench 18. The patterning method ^ ^ [conductor layer 14 ', after the bottom 10 Φ both the lithography and the lithography process. The sidewall and the - top layer: the layer / layer 2 ^ or the multilayer material layer of the stack 2. The cut and cut ((10) = (four) ί 疋 first by thermal oxidation After forming a layer of oxidized stone layer, the thickness of the stacked layer of arsenic oxidized cerium oxide formed on the oxygen etch layer is, for example, about 20 to 80 angstroms / dielectric layer plus the material may be any other known dielectric Referring to Figure 3, the dielectric layers 20 and VIII at the bottom of the trench 18 are removed; the layer 12, the substrate 10 at the bottom of the trench 18 is exposed The dielectric layer 2 of the sidewall of the trench 18 is removed. The method of removing the dielectric layer 2 at the bottom of the trench 18 includes an anisotropic rhyme method, such as a dry quotation method. The process of removing the dielectric layer 底部 at the bottom of the trench 18 is further removed. The dielectric layer 20 on the third layer of the second layer is also removed. At this point, the substrate is a stacked structure of the eight-ditch 18 The stacking mechanism 40 layer 12, the first conductor layer 14 and the first cap layer 16 are sequentially on the substrate H), and the second dielectric layer 2q is located on the sidewall of the trench (4). Two different film forming methods, forming a dielectric layer on the sidewalls of the trenches 18 and forming a dielectric layer 24 on the substrate K), (4) covering the first-top layer; The material of the electric layer 24 can be formed by the method of forming the phase 22 and the method of forming the dielectric layer 24; the unevenness of the center and the edge of the layer 22 is lower than the unevenness of the edge to the edge of the dielectric layer. The definition of unevenness is as follows: unevenness % = (maximum film thickness - minimum film thickness) / (average film thickness) X 100% In the implementation of wealth, the wealth used in the layer 22 (growth or deposition) It is possible to control the non-uniformity of the person below the job. Usually the uniformity of the film is related to the rate of film formation. The higher the rate of film formation, the lower the uniformity of the job. In one embodiment, the film formation method employed by the liner 22 is at the film formation rate of the = electrical layer. From another perspective, the density of the liner 22 is still at the density of the dielectric layer 24. The process used for liner 22 includes a thermal oxidation process or an atomic layer deposition process or other suitable method for growing the liner 201248789. The thermal oxidation process includes a rapid thermal oxidation process (RTO) or an in-situ steam generation (ISSG) process. The method of forming the dielectric layer 24 is, for example, a chemical vapor deposition method. The thickness of layer 22 is less than the thickness of dielectric layer 24. The thickness of the layer 22 is, for example, 1 to 200 angstroms; the thickness of the dielectric layer 24 is, for example, 1 〇〇 to 4 Å. The sum of the thicknesses of the liner 22 and the dielectric layer 24 is, for example, from 1 〇〇 to 6 〇〇. The dielectric layer 24 and the dielectric layer 2 on the sidewalls of the trench 18 serve as a dielectric layer between the floating gate and the control gate. The dielectric layer 24 and the lining layer 22 at the bottom of the trench 18 serve as a gate dielectric layer between the subsequently formed control gate and the substrate i , with a center-to-edge non-uniformity of less than 25 Å. . Then, a second conductor layer 26 is formed on the substrate, and the second conductor layer 26 is covered with a dielectric layer 24 and filled in the trench 18. The material of the third conductor layer % is, for example, a doped poly. The second conductor layer 26 is formed by, for example, a chemical-sinking step. The second method of forming a chemical vapor phase can also be performed by using a thick layer of the second conductor layer and doping in the field. After that, please refer to Figure 5, ^ί_ to the face. The second conductor layer 26 and the dielectric layer 2 = 4 above the first-top cover layer 16 of the Zhe-Zeng Chuan ^ 24, and remove the second 18-layer conductor layer 26 in the trench 18, so as to be embedded in Ditch = 2: 26 is lower than the first-top cover; lower from the first-conductor layer is 100 to 1000 angstroms. In the case of "-, questioning", the difference is, for example, about one example, the second part of the conductor is removed, and the chemical mechanical grinding method is used, and the third layer 16 is used as the polishing stop layer, The second conductor layer 26 201248789 and the dielectric layer 24 on the top cover layer 16 of the bezel are removed. Thereafter, a portion of the second conductor layer 26 in the trench u is removed using an etch back process. In another embodiment, the shifted second conductor 3526 # method can, for example, remove the second conductor layer 26 on the first cap layer 16 using the etch back process and continue to move in the trench 18 Part of the second conductor layer 26. Thereafter, the dielectric layer 24 on the first top cover 16 is removed. The second guide 26 embedded in the trench 18 is used as a control gate. θ Next, a second cap layer 28 is formed on the second conductor layer 26 in the trench 18. The material of the second cap layer 28 is different from that of the first cap layer 16, and the material thereof is, for example, yttrium oxide, thickness. For example, it is about 5 〇〇 to & (10) angstroms. The method for forming the second cap layer 28 is, for example, first depositing a second capping material layer (not shown) by chemical vapor deposition, and then removing the terminating layer by using the first capping layer 16 as the removal terminating layer. A second top cover material on a cover layer 16 has two layers. The second cap material layer on the first cap layer 16 is removed by chemical mechanical polishing. 』 Thereafter, referring to FIG. 6, the first cap layer 16 is removed to expose the first conductor, 14. The method of removing the first cap layer 16 can be a secret engraving process, = a wet butterfly process. Thereafter, a spacer material layer is formed on the substrate 1G to cover the first conductor layer 14, the dielectric layer 20, and the dielectric layer 24, the second = cap layer 28. The spacer material layer 3 (4) is made of a material different from that of the second cap layer 28, and is made of, for example, tantalum nitride, and is formed by, for example, a chemical vapor deposition method having a thickness of, for example, about 100 to 600 angstroms. ,,Rear. Referring to FIG. 7, the spacer material layer 3 is anisotropically etched to form a spacer 3〇a on the sidewall of the dielectric layer 20, and the spacer 3〇a covers the 201248789 partial 雷-leader method. Thereafter, the method of (iv) gap isotropic cooking, for example, the dry-touching portion of the first conductor and the second cap layer 28 is a mask, and the method of removing the layer 14 exposes the dielectric layer 12. Remove some of the first-conductor method. The first use of the anisotropic rhyme method, such as the dry characterization, is the control gate. The dielectric layer 14 is located at the gate of the second conductor layer, and is used as the first conductive layer. The combination of the floating layer and the dielectric layer 2G is used as the first conductive layer. The dielectric layer and the second conductor layer 26 (control) Q) Between the inter-media dielectric between the gate dielectric layer and the lining layer 2 2 is used as the gate between the control gate and the substrate 1 Forming a solid step to form a layer with a higher degree of uniformity, which is formed by a deposition method with a higher rate of film formation. However, this is not limited to this, and the gate and the substrate are controlled. The interlayer of the gate dielectric layer can be, without limitation, two steps, actually in application, - you are rounded up, as long as it is the film uniformity step of the first film forming step, and the subsequent film formation rate is higher than the first A film forming step is within the scope of the present invention. In summary, the gate dielectric layer between the control gate and the substrate of the present invention can be formed into one step or more to form, first formed at the bottom of the trench. Uniformity, the lining of the direction, slowing the height difference between the center and the edge, and thus the thickness of the dielectric layer formed by the subsequent deposition process can be extinguished. The problem of uniformity, afterwards, using a deposition method with a higher deposition rate to form a dielectric layer, on the one hand, can provide the total thickness required for the gate dielectric layer, and on the other hand can increase the throughput of the process, avoiding The film formation rate of the liner is 201248789, and the car is low and the output is sounded. Therefore, the method of the present invention is issued by the Japanese (4) to implement the above, but it is not intended to limit the Generally, the knowledge person, when not leaving the hair and the ribs, can make some changes and retouching, so this is the definition of the scope of the patent application attached to the garden. 1 to 7 are schematic cross-sectional views showing a method of fabricating a non-volatile memory according to an embodiment of the invention. [Description of main components] 10: substrate 12, 2, 24: dielectric layer 14' 26: conductor layer 16' 28: top cover layer 18 · trench 22. copper layer 3 〇 spacer material layer 3Ga: spacer 40: stacked structure 11