201248735 六、發明說明： 【發明所屬之技術領域】 本發明是關於一種製作半導體元件的方法，尤指一種製作金 氧半導體電晶體的方法。 【先前技術】 習知的金氧半導體(Metal Oxide Semiconductor，MOS)電晶體 通常包含有一基底、一源極區、一汲極區、一通道位於源極 區和汲極區之間、以及一閘極位於通道的上方。其中，閘極 係包含一閘極介電層位於通道上、一閘極導電層位於閘極介 電層上，以及一侧壁子位於閘極導電層的側壁。一般而言， M0S電晶體在一固定的電場下，流經通道的驅動電流量會 和通道中的載子遷移率成正比。因此，如何在現有的製程設 備中’提升載子遷移率以增加M0S電晶體之開關速度已成 為目前半導體技術領域中之一大課題。 磊晶成長製程，例如矽鍺源/汲極製程是利用在側壁子形成之 後，於鄰接於各側壁子的半導體基底中分別磊晶生成一鍺化 矽磊晶層。其係利用鍺化矽層的晶格常數與矽不同的特性， 使矽磊晶在矽基底中產生結構上應變而形成應變矽。由於石夕 錯層的晶格常數(lattice constant)比矽大，這使得矽的帶結構 (band structure)發生改變，而造成載子移動性增加，因此可 增加M0S電晶體的開關速度以提高積體電路效能與速度。 4 201248735 然而’習知在利用選擇性蟲晶成長製程來形成蟲晶層的時 候’所長出㈣晶層通常會沿著氮切側壁子的㈣表面成 長而緊貼於側壁子表面。此生長方式在大部分情況下會對電 晶體的通道區域產生應力衰減’而導致所謂的導通電流衰減 (Ion degradation)現象，使整個元件運作不佳。因此如何改 良目前以選擇縣晶成長方絲製作應料電晶體即為 重要課題。 【發明内容】 本發明是揭露一種製作半導體電晶體的方法，以解決上述習 知問題。 依據本發明之較佳實施例，是揭露一種製作半導體元件的方 法，其包含下列步驟。首先提供一基底，該基底上設有一閘 極結構。然後形成一堆疊薄膜於基底表面並覆蓋閘極結構， 且堆疊薄膜具有一氧化層與一氮化層，接著去除部分堆疊薄 膜以於閘極結構兩侧之基底中形成二凹槽並同時於閘極結 構之侧壁形成一可去除側壁子。隨後於該等凹槽中形成 —具有刻面之材料層，且該材料層包含矽原子。 【實施方式】 請參照第1圖至第6圖，第i圖至第6圖為本發明較佳實施 201248735 例製作一半導體元件，例如一金氧半導體電晶體之方法示意 圖。如第1圖所不’首先提供一基底10 ’例如一碎晶圓（wafer) 或一石夕覆絕緣（silicon on insulator，SOI)基底等。基底1〇上設 有一閘極結構12，且閘極結構12所在之主動區域(active region)外圍的基底10内環繞有一淺溝隔離（shall〇w trench isolation，STI)22。其中，閘極結構12包含有一閘極介電層 14、一位於閘極介電層14上之閘極16以及一位於閘極16 頂部的頂保護層18。閘極介電層14可由矽氧化合物或氮氧 化合物或高介電係數介電材料等單一絕緣材料或上述材料 的任意組合所構成，閘極16可由換雜或未摻雜的單晶石夕或 多晶石夕、補材料、金屬魏物、金屬等導電材料所構成， 而頂保護層18肢由氮化發或氧化料介電材料所構成。 然後形成-偏位側壁子2G於閘極結構12側壁表面，偏位側 壁子20例如是由氮切所構成的，並閘極結構Η及偏 位側壁子20當作遮罩進杆—ά 仃輕摻雜離子佈植，將ρ型或Ν 型摻質植入偏位側壁子2〇而也丨从w υ兩側的基底10中，以於閘極結構 12相對兩側分別形成一輕摻 心雜及極（lightly doped drain, T.rmm ° ' 隨後如第2圖所示，先以化學 予乳祁/尤積（chemical vapor deposition，CVD)依序形成一 Λ 备 ^ ^ 战由氧化層22及氮化層24所構成 的堆疊薄膜26於基底10、偏 苒成 偏位側壁子20及閘極結構12表 6 201248735 面。在本實施例中，製作堆疊薄膜26時較佳以一含氣原子 的前驅物’例如六氣矽烷(hexachlorosilane，HCD)來形成堆最 薄膜26中的氮化層24，且完成堆疊薄膜26中氧化層22的 厚度較佳為10至50埃如30埃而氮化層24的厚度則較佳為 60至180埃例如120埃。需注意的是，本實施例雖較佳以六 氣矽烧作為前驅物來形成堆疊薄膜26中的氮化層24，但不 侷限於此，又可選擇其他不含氣或含氯的前驅物如二氣矽燒 (dichlorosilane)來形成氮化層24，此作法也屬本發明所涵蓋 的範圍。 然後如第3圖所示，進行一次或一次以上的蝕刻製程，例如 以乾#刻、濕钮刻或兩者同時進行的方式去除部分氧化層 及氮化層24，以於閘極結構12兩側之基底1 〇中形成二凹槽 28並同時於閘極結構12的側壁形成一由l型氧化層22及 剩餘II化層24所構成的可去除側壁子(diSp0sable spacer)30。 需注意的是’除了上述形成可去除側壁子30的方式，本發 明另一實施例又可先沈積一厚度約30至70埃如50埃的氧 化層22在基底10、偏位侧壁子2〇及閘極結構12表面，如 第4圖所示，然後對沈積的氧化層22進行一處理，例如一 分搞式電裝氮化(decoupled plasma nitridation，DPN)製程，以 於氧化層22中形成含氮物質（nitr〇gen_cont；aining substance)32。接著沈積一厚度約50至150埃如1〇〇埃的敗 201248735 化層24在具有含氮物質32的氧化層22上，並進行上述的 乾蝕刻及/或濕蝕刻製程，去除部分氧化層22及氮化層24 以於閘極結構12兩側的基底10中形成二凹槽28並同時於 閘極結構12的侧壁形成一可去除側壁子(disp〇sable spacer)34。 需注意的是，上述實施例雖較佳以分耦式電漿氮化製程於氧 化層22及氮化層24之間植入含氮物質32,但不侷限於此作 法，又可選擇在一含氮環境下對氧化層22進行一快速熱處 理製程或一爐官'退火（furnace anneal)製程，以製作出同樣且 有含氮物質32的氧化層22 ’此實施例也屬本發明所涵蓋的 範圍。 然後5圖所示，進行一預清洗(pre-clean)步驟，利用稀釋氫 氟酸水溶液(diluted hydrofluoric acid)或一含有硫酸、過氧化 氫、與去離子水的SPM混合溶液等清洗液來去除凹槽28表 面的原生氧化物或其他不純物質，並於凹槽28中填入含有 石夕原子的材料層，以形成一蠢晶層3 6。在本較佳實施例中， 可結合選擇性應力系統(selective strain scheme，SSS)等製 程，例如利用選擇性ϋ晶成長(selective epitaxial growth，SEG) 方法來製作磊晶層36。其中磊晶層36可視電晶體的特性包 含鍺化矽（SiGe)之磊晶層或包含有碳化矽（SiC)之磊晶層。 8 201248735 祐 >主意的是，相較於習知的選擇性磊晶成長製程是以緊貼著 由氮化矽所構成的側壁子來形成矩型的磊晶層，本發明的可 去除側壁子較佳由一 L型氧化層與一設於其上的氮化層所 構成，且L型氧化層是以貼附基底表面的方式緊鄰源極/汲 極區域，因此以選擇性磊晶成長製程形成磊晶層的時候由凹 槽内沿著基底晶格結構所長出的遙晶層便不會緊貼著可去 除側壁子的侧壁來成長，而在成長時會與可去除側壁子的侧 壁產生一間距’而形成一具有刻面（faceted shape)，例如一六 角型的磊晶層。需注意的是，本實施例主要強調磊晶層36 在基底10上的部分具有刻面’例如在基底1 〇以上的蟲晶層 角度較佳為15-60度，例如磊晶層（111)面與基底（丨〇〇)面的夾 角約54.74度，而磊晶層（113)面與基底（1〇〇)面的夾角則約 25.24度。整個磊晶層36是否呈現六角形，例如磊晶層36 在基底10下的部分則視蝕刻製程的條件可有不同形狀。 然後如第6圖所示，可依據製程需求選擇性去除可去除側壁 子30，而僅於閘極結構12側壁留下偏位側壁子2〇。接著可 選擇性形成一主側壁子38於偏位側壁子20周圍，並依製程 需求進行一離子佈植製程，以於主側壁子38兩側的基底1〇 中形成一源極/汲極區域40。之後可選擇性進行一應力記憶 製程（stress memorization technology，SMT)，例如可先以離子 佈植對裸露出的石夕材料進行非晶化再形成一應力轉移結構 如具有應力的氮化石夕層（圖未示）在閘極結構1 2與基底1 〇表 201248735 面，然後進行一退火製程並去除應力轉移結構，如此便可藉 由應力轉移結構對閘極介電層所產生的應力記憶效應來提 升元件離子的效能(I〇n performance)。在本實施例中，應力 轉移結構可包含一具有拉伸或壓縮應力的應力層。 如同上述以選擇性應力系統形成磊晶層的方式，若所製作的 電晶體為一 NMOS電晶體，可選擇形成—具有拉伸應力的應 力層（tensile stress layer)於閘極結構與基底表面來進行應力 記憶製程，而若所製作的電晶體為一 pM〇s電晶體，則可形 成一具有壓縮應力的應力層（C〇mpreSSive stress layer)於閘極 結構與基底表面來進行應力製程。由於應力記憶製程為此領 域者所熟知技術，在此不另加贅述。 之後可再依照製程需求進行一石夕化金屬（sa】jcide)製程，例如 可先錢鍍或沈積一由姑、鈦、錄、翻、把、鉬等所構成的金 屬層（圖未示）在蟲晶層上，然後藉由至少一次的快速升溫退 火(rapid thermal anneal，RTP)製程使金屬層與磊晶層反應以 形成一矽化金屬層（圖未示）《>隨後可於基底上依序形成一 接觸洞蝕刻停止層（contact etch stop layer, CESL)(圖未示）與 一内層介電（inter-layer dielectric, ILD)層（圖未示）。由於形成 上述元件之步驟亦為熟習該項技藝者所知，故於此亦不再贅 201248735 ^主思的是，本實施例雖選擇在形成應力轉移結構前去除可 去除側壁子3G，但切可去除側壁子30的時_並不偈限 又可依據製程需求選擇在形成接觸㈣贿止層之前 去除，此實施例也屬本發明所涵蓋的範圍。 π上所述，本發明料實施触要在祕結卿成後先覆蓋 -由氧化層與氮化層所構成的堆疊薄膜在基底與閘極结構 表面’以使後續進行選擇料晶成長製㈣絲晶層時，由 凹槽内沿著基底晶格結構所長出的蟲晶層在接觸到氧化層 之後，便不會緊貼著可去除側壁子的側壁來成長，而在成長 時會與可去除侧壁子的侧壁產生—間距，而形成—具有刻面 (fac田etedshape)之六角型的源極/没極區域，然後去除部分的 堆豐薄膜以於閘極結構兩側的基底中形成二凹槽並同時在 閘極結構的側壁形成一可去除侧壁子。 3外’ & &製作蟲㉟層凹槽的乾似彳及濕似彳製程通常會毁 才貝到可去除側壁子中的氧化層材料，本發明另一實施例較佳 先以分耦式電漿氮化製程於氧化層中形成含氮物質 ，如此便 可保護氧化層不受到後續蝕刻製程的傷害。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 11 201248735 【圖式簡單說明】 第1圖至第6圖為本發明較佳實施例製作一金氧半導體電晶 體之方法示意圖。 【主要元件符號說明】 10 半導體基底 12 閘極結構 14 閘極介電層 16 閘極 18 頂保護層 20 偏位側壁子 22 淺溝隔離 24 輕換雜没極 26 堆疊薄膜 28 凹槽 30 可去除侧壁子 32 含氮物質 34 可去除側壁子 36 遙晶層 38 主側壁子 40 源極/>及極區域 12201248735 VI. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a metal oxide semiconductor transistor. [Prior Art] A conventional Metal Oxide Semiconductor (MOS) transistor generally includes a substrate, a source region, a drain region, a channel between the source region and the drain region, and a gate. The pole is located above the channel. Wherein, the gate electrode comprises a gate dielectric layer on the channel, a gate conductive layer on the gate dielectric layer, and a sidewall spacer on the sidewall of the gate conductive layer. In general, the amount of drive current flowing through a channel under a fixed electric field of a MOS transistor is proportional to the carrier mobility in the channel. Therefore, how to increase the carrier mobility to increase the switching speed of the MOS transistor in the existing process equipment has become one of the major issues in the field of semiconductor technology. The epitaxial growth process, for example, the germanium/drain process, is performed by epitaxially forming a germanium germanium epitaxial layer in a semiconductor substrate adjacent to each sidewall after the sidewall spacers are formed. The system utilizes the different lattice constants of the bismuth telluride layer to form a strain strain in the bismuth substrate. Since the lattice constant of the Shixia layer is larger than that of the ,, this changes the band structure of the ,, which causes the carrier mobility to increase, so the switching speed of the MOS transistor can be increased to increase the product. Body circuit performance and speed. 4 201248735 However, it is known that the (four) crystal layer is grown along the (four) surface of the nitrogen-cut sidewalls and adheres to the surface of the sidewall sub-surface when the selective insect crystal growth process is used to form the crystal layer. This growth mode causes stress decay in the channel region of the transistor in most cases, resulting in a so-called on-current Ion degradation phenomenon, which causes the entire device to operate poorly. Therefore, how to improve the current selection of crystal crystals for the growth of square crystals is an important issue. SUMMARY OF THE INVENTION The present invention is directed to a method of fabricating a semiconductor transistor to solve the above-mentioned conventional problems. In accordance with a preferred embodiment of the present invention, a method of fabricating a semiconductor device is disclosed that includes the following steps. First, a substrate is provided, which is provided with a gate structure. Forming a stacked film on the surface of the substrate and covering the gate structure, and the stacked film has an oxide layer and a nitride layer, and then removing the partially stacked film to form two grooves in the substrate on both sides of the gate structure and simultaneously The sidewalls of the pole structure form a removable sidewall. A layer of material having a facet is then formed in the grooves, and the layer of material comprises germanium atoms. [Embodiment] Please refer to Figs. 1 to 6 and Fig. ith to Fig. 6 are diagrams showing a method of fabricating a semiconductor device, such as a MOS transistor, in the preferred embodiment of the present invention. As shown in Fig. 1, a substrate 10' such as a wafer or a silicon on insulator (SOI) substrate or the like is first provided. A gate structure 12 is disposed on the substrate 1 , and a substrate 10 surrounding the active region of the gate structure 12 is surrounded by a shallow trench isolation (STI) 22 . The gate structure 12 includes a gate dielectric layer 14, a gate 16 on the gate dielectric layer 14, and a top protection layer 18 on the top of the gate 16. The gate dielectric layer 14 may be composed of a single insulating material such as a silicon oxide compound or an oxynitride or a high-k dielectric material or any combination of the above materials, and the gate 16 may be replaced by a single or undoped single crystal. Or a polycrystalline stone, a supplemental material, a metal material, a metal, or the like, and the top protective layer 18 is composed of a nitrided or oxidized dielectric material. Then, a sidewall spacer 2G is formed on the sidewall surface of the gate structure 12, and the bias sidewall spacer 20 is formed, for example, by nitrogen cutting, and the gate structure and the bias sidewall spacer 20 are used as masks for the rod-ά 仃Lightly doped ion implantation, the p-type or Ν-type dopant is implanted into the biased sidewalls 2〇 and also from the substrate 10 on both sides of the w , to form a lightly doped on the opposite sides of the gate structure 12 The lightly doped drain (T.rmm ° ' is followed by the chemical vapor deposition (CVD) in the form of a chemical sputum / chemical vapor deposition (CVD). The stacked film 26 formed by the layer 22 and the nitride layer 24 is formed on the substrate 10, the biased sidewall spacer 20, and the gate structure 12, Table 6 201248735. In the present embodiment, the stacked film 26 is preferably formed by a The precursor of the gas atom, such as hexachlorosilane (HCD), forms the nitride layer 24 in the stack of the most thin film 26, and the thickness of the oxide layer 22 in the completed stacked film 26 is preferably 10 to 50 angstroms, such as 30 angstroms. The thickness of the nitride layer 24 is preferably 60 to 180 angstroms, for example, 120 angstroms. It should be noted that although the embodiment is preferably six The sinter is used as a precursor to form the nitride layer 24 in the stacked film 26, but is not limited thereto, and other gas-free or chlorine-containing precursors such as dichlorosilane may be selected to form the nitride layer 24. This method is also within the scope of the present invention. Then, as shown in FIG. 3, one or more etching processes are performed, for example, by removing the partial oxide layer by dry etching, wet button etching, or both. The nitride layer 24 forms a recess 28 in the substrate 1 两侧 on both sides of the gate structure 12 and simultaneously forms an oxide layer 22 and a remaining II layer 24 on the sidewall of the gate structure 12 The sidewall spacers 30 are removed. It should be noted that in addition to the above-described manner of forming the removable sidewall spacers 30, another embodiment of the present invention may first deposit an oxide layer 22 having a thickness of about 30 to 70 angstroms, such as 50 angstroms. The substrate 10, the biased sidewalls 2〇 and the surface of the gate structure 12, as shown in FIG. 4, are then subjected to a treatment of the deposited oxide layer 22, such as a decoupled plasma nitridation (DPN). a process for forming a nitrogen-containing substance in the oxide layer 22 ( Nitr〇gen_cont;aining substance) 32. Next, a 201248735 layer 24 having a thickness of about 50 to 150 angstroms, such as 1 angstrom, is deposited on the oxide layer 22 having the nitrogen-containing material 32, and subjected to the above dry etching and/or The wet etching process removes the partial oxide layer 22 and the nitride layer 24 to form two recesses 28 in the substrate 10 on both sides of the gate structure 12 and simultaneously form a removable sidewall on the sidewall of the gate structure 12. Sable spacer)34. It should be noted that, in the above embodiment, the nitrogen-containing substance 32 is preferably implanted between the oxide layer 22 and the nitride layer 24 by a split-coupled plasma nitridation process, but is not limited thereto, and may be selected in one The oxide layer 22 is subjected to a rapid heat treatment process or a furnace anneal process in a nitrogen-containing environment to produce an oxide layer 22 having the same nitrogen-containing substance 32. This embodiment is also encompassed by the present invention. range. Then, as shown in FIG. 5, a pre-cleaning step is performed to remove the diluted hydrofluoric acid or a cleaning solution containing sulfuric acid, hydrogen peroxide, and SPM mixed with deionized water. A native oxide or other impure material on the surface of the recess 28 is filled with a layer of material containing a stone atom in the recess 28 to form a stray layer 36. In the preferred embodiment, the epitaxial layer 36 can be fabricated by a selective growth scheme (SSS) process, such as a selective epitaxial growth (SEG) method. The epitaxial layer 36 may comprise an epitaxial layer of germanium telluride (SiGe) or an epitaxial layer containing germanium carbide (SiC) depending on the characteristics of the transistor. 8 201248735 It is an idea that the selective epitaxial growth process is a rectangular epitaxial layer formed by a side wall formed of tantalum nitride, which is a removable sidewall of the present invention. Preferably, the sub-layer is composed of an L-type oxide layer and a nitride layer disposed thereon, and the L-type oxide layer is adjacent to the source/drain region in a manner of attaching the surface of the substrate, thereby selectively epitaxially growing. When the process forms the epitaxial layer, the crystal layer grown in the groove along the base lattice structure does not grow close to the sidewall of the removable sidewall, and grows with the removable sidewall The sidewalls create a pitch' to form a faceted shape, such as a hexagonal epitaxial layer. It should be noted that this embodiment mainly emphasizes that the portion of the epitaxial layer 36 on the substrate 10 has a facet ', for example, the angle of the insect layer above the substrate 1 较佳 is preferably 15-60 degrees, such as an epitaxial layer (111). The angle between the face and the base (丨〇〇) face is about 54.74 degrees, and the angle between the facet layer (113) face and the base (1 inch) face is about 25.24 degrees. Whether the entire epitaxial layer 36 exhibits a hexagonal shape, for example, the portion of the epitaxial layer 36 under the substrate 10 may have different shapes depending on the conditions of the etching process. Then, as shown in Fig. 6, the removable sidewalls 30 can be selectively removed depending on the process requirements, and only the sidewalls of the gate structure 12 are left behind. Then, a main sidewall 38 is selectively formed around the bias sidewall 20, and an ion implantation process is performed according to process requirements to form a source/drain region in the substrate 1〇 on both sides of the main sidewall 38. 40. Then, a stress memorization technology (SMT) can be selectively performed. For example, the exposed Zeshi material can be amorphized by ion implantation to form a stress transfer structure such as a stress-resistant nitride layer ( The figure is shown in the gate structure 1 2 and the substrate 1 2012 201248735 surface, and then an annealing process is performed and the stress transfer structure is removed, so that the stress memory effect of the gate dielectric layer by the stress transfer structure can be Improve the performance of component ions (I〇n performance). In this embodiment, the stress transfer structure may comprise a stress layer having tensile or compressive stress. As described above, in the manner of forming the epitaxial layer by the selective stress system, if the fabricated transistor is an NMOS transistor, it is possible to form a tensile stress layer on the gate structure and the surface of the substrate. The stress memory process is performed, and if the fabricated transistor is a pM〇s transistor, a stress layer (C〇mpreSSive stress layer) can be formed on the gate structure and the surface of the substrate for stress processing. Since the stress memory process is well known to those skilled in the art, no further details are provided herein. Then, according to the process requirements, a stone metal (sa) jcide process can be carried out. For example, a metal layer (not shown) composed of abundance, titanium, recording, turning, molybdenum, etc. can be deposited or deposited. On the worm layer, the metal layer and the epitaxial layer are reacted by at least one rapid thermal anneal (RTP) process to form a deuterated metal layer (not shown). A contact etch stop layer (CESL) (not shown) and an inter-layer dielectric (ILD) layer (not shown) are formed. Since the steps of forming the above-mentioned components are also known to those skilled in the art, this is no longer the case. 201248735. The main idea is that although this embodiment selects to remove the removable sidewall sub- 3G before forming the stress-transfer structure, The time when the side wall 30 can be removed is not limited and can be removed prior to forming the contact (four) bribe layer according to the process requirements. This embodiment is also within the scope of the present invention. According to π, the implementation of the material of the present invention is first covered after the secret formation - a stacked film composed of an oxide layer and a nitride layer on the surface of the substrate and the gate structure to enable subsequent selection of the crystal growth (4) In the case of a silk crystal layer, the crystal layer grown in the groove along the base crystal lattice structure does not adhere to the sidewall of the removable sidewall after the contact with the oxide layer, and grows when it grows. Removing the sidewalls of the sidewalls to create a gap, and forming a hexagonal source/no-polar region having a facet (fed field etedshape), and then removing a portion of the stacking film for the substrate on both sides of the gate structure Two recesses are formed and a removable sidewall is formed on the sidewall of the gate structure. 3 The outer &&&&&&&&&&&&&&&&&&&&&&&&<> The plasma nitridation process forms a nitrogen-containing substance in the oxide layer, thereby protecting the oxide layer from subsequent etching processes. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patent scope of the present invention are intended to be within the scope of the present invention. 11 201248735 [Brief Description of the Drawings] Figs. 1 to 6 are schematic views showing a method of fabricating a MOS semiconductor crystal according to a preferred embodiment of the present invention. [Main component symbol description] 10 Semiconductor substrate 12 Gate structure 14 Gate dielectric layer 16 Gate 18 Top protection layer 20 Deviated sidewalls 22 Shallow trench isolation 24 Light-replacement poles 26 Stacking film 28 Groove 30 Can be removed Sidewall 32 nitrogen-containing material 34 removable sidewalls 36 tele-crystal layer 38 main sidewall 40 source/> and polar region 12